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Searched refs:intel_ring_emit (Results 1 – 8 of 8) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_ringbuffer.c112 intel_ring_emit(ring, cmd); in gen2_render_ring_flush()
113 intel_ring_emit(ring, MI_NOOP); in gen2_render_ring_flush()
170 intel_ring_emit(ring, cmd); in gen4_render_ring_flush()
171 intel_ring_emit(ring, MI_NOOP); in gen4_render_ring_flush()
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); in intel_emit_post_sync_nonzero_flush()
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | in intel_emit_post_sync_nonzero_flush()
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ in intel_emit_post_sync_nonzero_flush()
229 intel_ring_emit(ring, 0); /* low dword */ in intel_emit_post_sync_nonzero_flush()
230 intel_ring_emit(ring, 0); /* high dword */ in intel_emit_post_sync_nonzero_flush()
231 intel_ring_emit(ring, MI_NOOP); in intel_emit_post_sync_nonzero_flush()
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Di915_gem_context.c530 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); in mi_set_context()
534 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); in mi_set_context()
539 intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); in mi_set_context()
540 intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); in mi_set_context()
545 intel_ring_emit(ring, MI_NOOP); in mi_set_context()
546 intel_ring_emit(ring, MI_SET_CONTEXT); in mi_set_context()
547 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->legacy_hw_ctx.rcs_state) | in mi_set_context()
553 intel_ring_emit(ring, MI_NOOP); in mi_set_context()
559 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); in mi_set_context()
564 intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); in mi_set_context()
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Dintel_overlay.c253 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON); in intel_overlay_on()
254 intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE); in intel_overlay_on()
255 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); in intel_overlay_on()
256 intel_ring_emit(ring, MI_NOOP); in intel_overlay_on()
287 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); in intel_overlay_continue()
288 intel_ring_emit(ring, flip_addr); in intel_overlay_continue()
345 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); in intel_overlay_off()
346 intel_ring_emit(ring, flip_addr); in intel_overlay_off()
347 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); in intel_overlay_off()
352 intel_ring_emit(ring, MI_NOOP); in intel_overlay_off()
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Di915_gem_execbuffer.c1086 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in i915_reset_gen7_sol_offsets()
1087 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); in i915_reset_gen7_sol_offsets()
1088 intel_ring_emit(ring, 0); in i915_reset_gen7_sol_offsets()
1115 intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965); in i915_emit_box()
1116 intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); in i915_emit_box()
1117 intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16); in i915_emit_box()
1118 intel_ring_emit(ring, DR4); in i915_emit_box()
1124 intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO); in i915_emit_box()
1125 intel_ring_emit(ring, DR1); in i915_emit_box()
1126 intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); in i915_emit_box()
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Di915_gem_gtt.c453 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in gen8_write_pdp()
454 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); in gen8_write_pdp()
455 intel_ring_emit(ring, (u32)(val >> 32)); in gen8_write_pdp()
456 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in gen8_write_pdp()
457 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); in gen8_write_pdp()
458 intel_ring_emit(ring, (u32)(val)); in gen8_write_pdp()
969 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); in hsw_mm_switch()
970 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); in hsw_mm_switch()
971 intel_ring_emit(ring, PP_DIR_DCLV_2G); in hsw_mm_switch()
972 intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); in hsw_mm_switch()
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Dintel_display.c9669 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); in intel_gen2_queue_flip()
9670 intel_ring_emit(ring, MI_NOOP); in intel_gen2_queue_flip()
9671 intel_ring_emit(ring, MI_DISPLAY_FLIP | in intel_gen2_queue_flip()
9673 intel_ring_emit(ring, fb->pitches[0]); in intel_gen2_queue_flip()
9674 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen2_queue_flip()
9675 intel_ring_emit(ring, 0); /* aux display base address, unused */ in intel_gen2_queue_flip()
9701 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); in intel_gen3_queue_flip()
9702 intel_ring_emit(ring, MI_NOOP); in intel_gen3_queue_flip()
9703 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | in intel_gen3_queue_flip()
9705 intel_ring_emit(ring, fb->pitches[0]); in intel_gen3_queue_flip()
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Dintel_ringbuffer.h402 static inline void intel_ring_emit(struct intel_engine_cs *ring, in intel_ring_emit() function
Di915_gem.c4648 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in i915_gem_l3_remap()
4649 intel_ring_emit(ring, reg_base + i); in i915_gem_l3_remap()
4650 intel_ring_emit(ring, remap_info[i/4]); in i915_gem_l3_remap()