112 	intel_ring_emit(ring, cmd);  in gen2_render_ring_flush()
113 	intel_ring_emit(ring, MI_NOOP);  in gen2_render_ring_flush()
170 	intel_ring_emit(ring, cmd);  in gen4_render_ring_flush()
171 	intel_ring_emit(ring, MI_NOOP);  in gen4_render_ring_flush()
225 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));  in intel_emit_post_sync_nonzero_flush()
226 	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |  in intel_emit_post_sync_nonzero_flush()
228 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */  in intel_emit_post_sync_nonzero_flush()
229 	intel_ring_emit(ring, 0); /* low dword */  in intel_emit_post_sync_nonzero_flush()
230 	intel_ring_emit(ring, 0); /* high dword */  in intel_emit_post_sync_nonzero_flush()
231 	intel_ring_emit(ring, MI_NOOP);  in intel_emit_post_sync_nonzero_flush()
238 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));  in intel_emit_post_sync_nonzero_flush()
239 	intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);  in intel_emit_post_sync_nonzero_flush()
240 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */  in intel_emit_post_sync_nonzero_flush()
241 	intel_ring_emit(ring, 0);  in intel_emit_post_sync_nonzero_flush()
242 	intel_ring_emit(ring, 0);  in intel_emit_post_sync_nonzero_flush()
243 	intel_ring_emit(ring, MI_NOOP);  in intel_emit_post_sync_nonzero_flush()
292 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));  in gen6_render_ring_flush()
293 	intel_ring_emit(ring, flags);  in gen6_render_ring_flush()
294 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);  in gen6_render_ring_flush()
295 	intel_ring_emit(ring, 0);  in gen6_render_ring_flush()
310 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));  in gen7_render_ring_cs_stall_wa()
311 	intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |  in gen7_render_ring_cs_stall_wa()
313 	intel_ring_emit(ring, 0);  in gen7_render_ring_cs_stall_wa()
314 	intel_ring_emit(ring, 0);  in gen7_render_ring_cs_stall_wa()
373 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));  in gen7_render_ring_flush()
374 	intel_ring_emit(ring, flags);  in gen7_render_ring_flush()
375 	intel_ring_emit(ring, scratch_addr);  in gen7_render_ring_flush()
376 	intel_ring_emit(ring, 0);  in gen7_render_ring_flush()
392 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));  in gen8_emit_pipe_control()
393 	intel_ring_emit(ring, flags);  in gen8_emit_pipe_control()
394 	intel_ring_emit(ring, scratch_addr);  in gen8_emit_pipe_control()
395 	intel_ring_emit(ring, 0);  in gen8_emit_pipe_control()
396 	intel_ring_emit(ring, 0);  in gen8_emit_pipe_control()
397 	intel_ring_emit(ring, 0);  in gen8_emit_pipe_control()
728 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));  in intel_ring_workarounds_emit()
730 		intel_ring_emit(ring, w->reg[i].addr);  in intel_ring_workarounds_emit()
731 		intel_ring_emit(ring, w->reg[i].value);  in intel_ring_workarounds_emit()
733 	intel_ring_emit(ring, MI_NOOP);  in intel_ring_workarounds_emit()
1146 		intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));  in gen8_rcs_signal()
1147 		intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |  in gen8_rcs_signal()
1150 		intel_ring_emit(signaller, lower_32_bits(gtt_offset));  in gen8_rcs_signal()
1151 		intel_ring_emit(signaller, upper_32_bits(gtt_offset));  in gen8_rcs_signal()
1152 		intel_ring_emit(signaller, seqno);  in gen8_rcs_signal()
1153 		intel_ring_emit(signaller, 0);  in gen8_rcs_signal()
1154 		intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |  in gen8_rcs_signal()
1156 		intel_ring_emit(signaller, 0);  in gen8_rcs_signal()
1187 		intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |  in gen8_xcs_signal()
1189 		intel_ring_emit(signaller, lower_32_bits(gtt_offset) |  in gen8_xcs_signal()
1191 		intel_ring_emit(signaller, upper_32_bits(gtt_offset));  in gen8_xcs_signal()
1192 		intel_ring_emit(signaller, seqno);  in gen8_xcs_signal()
1193 		intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |  in gen8_xcs_signal()
1195 		intel_ring_emit(signaller, 0);  in gen8_xcs_signal()
1223 			intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));  in gen6_signal()
1224 			intel_ring_emit(signaller, mbox_reg);  in gen6_signal()
1225 			intel_ring_emit(signaller, seqno);  in gen6_signal()
1231 		intel_ring_emit(signaller, MI_NOOP);  in gen6_signal()
1258 	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);  in gen6_add_request()
1259 	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);  in gen6_add_request()
1260 	intel_ring_emit(ring,  in gen6_add_request()
1262 	intel_ring_emit(ring, MI_USER_INTERRUPT);  in gen6_add_request()
1295 	intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |  in gen8_ring_sync()
1299 	intel_ring_emit(waiter, seqno);  in gen8_ring_sync()
1300 	intel_ring_emit(waiter,  in gen8_ring_sync()
1302 	intel_ring_emit(waiter,  in gen8_ring_sync()
1333 		intel_ring_emit(waiter, dw1 | wait_mbox);  in gen6_ring_sync()
1334 		intel_ring_emit(waiter, seqno);  in gen6_ring_sync()
1335 		intel_ring_emit(waiter, 0);  in gen6_ring_sync()
1336 		intel_ring_emit(waiter, MI_NOOP);  in gen6_ring_sync()
1338 		intel_ring_emit(waiter, MI_NOOP);  in gen6_ring_sync()
1339 		intel_ring_emit(waiter, MI_NOOP);  in gen6_ring_sync()
1340 		intel_ring_emit(waiter, MI_NOOP);  in gen6_ring_sync()
1341 		intel_ring_emit(waiter, MI_NOOP);  in gen6_ring_sync()
1350 	intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |		\
1352 	intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);			\
1353 	intel_ring_emit(ring__, 0);							\
1354 	intel_ring_emit(ring__, 0);							\
1375 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |  in pc_render_add_request()
1378 	intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);  in pc_render_add_request()
1379 	intel_ring_emit(ring,  in pc_render_add_request()
1381 	intel_ring_emit(ring, 0);  in pc_render_add_request()
1394 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |  in pc_render_add_request()
1398 	intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);  in pc_render_add_request()
1399 	intel_ring_emit(ring,  in pc_render_add_request()
1401 	intel_ring_emit(ring, 0);  in pc_render_add_request()
1561 	intel_ring_emit(ring, MI_FLUSH);  in bsd_ring_flush()
1562 	intel_ring_emit(ring, MI_NOOP);  in bsd_ring_flush()
1576 	intel_ring_emit(ring, MI_STORE_DWORD_INDEX);  in i9xx_add_request()
1577 	intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);  in i9xx_add_request()
1578 	intel_ring_emit(ring,  in i9xx_add_request()
1580 	intel_ring_emit(ring, MI_USER_INTERRUPT);  in i9xx_add_request()
1721 	intel_ring_emit(ring,  in i965_dispatch_execbuffer()
1726 	intel_ring_emit(ring, offset);  in i965_dispatch_execbuffer()
1749 	intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);  in i830_dispatch_execbuffer()
1750 	intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);  in i830_dispatch_execbuffer()
1751 	intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */  in i830_dispatch_execbuffer()
1752 	intel_ring_emit(ring, cs_offset);  in i830_dispatch_execbuffer()
1753 	intel_ring_emit(ring, 0xdeadbeef);  in i830_dispatch_execbuffer()
1754 	intel_ring_emit(ring, MI_NOOP);  in i830_dispatch_execbuffer()
1769 		intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);  in i830_dispatch_execbuffer()
1770 		intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);  in i830_dispatch_execbuffer()
1771 		intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);  in i830_dispatch_execbuffer()
1772 		intel_ring_emit(ring, cs_offset);  in i830_dispatch_execbuffer()
1773 		intel_ring_emit(ring, 4096);  in i830_dispatch_execbuffer()
1774 		intel_ring_emit(ring, offset);  in i830_dispatch_execbuffer()
1776 		intel_ring_emit(ring, MI_FLUSH);  in i830_dispatch_execbuffer()
1777 		intel_ring_emit(ring, MI_NOOP);  in i830_dispatch_execbuffer()
1788 	intel_ring_emit(ring, MI_BATCH_BUFFER);  in i830_dispatch_execbuffer()
1789 	intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?  in i830_dispatch_execbuffer()
1791 	intel_ring_emit(ring, offset + len - 8);  in i830_dispatch_execbuffer()
1792 	intel_ring_emit(ring, MI_NOOP);  in i830_dispatch_execbuffer()
1809 	intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);  in i915_dispatch_execbuffer()
1810 	intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?  in i915_dispatch_execbuffer()
2275 		intel_ring_emit(ring, MI_NOOP);  in intel_ring_cacheline_align()
2363 	intel_ring_emit(ring, cmd);  in gen6_bsd_ring_flush()
2364 	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);  in gen6_bsd_ring_flush()
2366 		intel_ring_emit(ring, 0); /* upper addr */  in gen6_bsd_ring_flush()
2367 		intel_ring_emit(ring, 0); /* value */  in gen6_bsd_ring_flush()
2369 		intel_ring_emit(ring, 0);  in gen6_bsd_ring_flush()
2370 		intel_ring_emit(ring, MI_NOOP);  in gen6_bsd_ring_flush()
2390 	intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));  in gen8_ring_dispatch_execbuffer()
2391 	intel_ring_emit(ring, lower_32_bits(offset));  in gen8_ring_dispatch_execbuffer()
2392 	intel_ring_emit(ring, upper_32_bits(offset));  in gen8_ring_dispatch_execbuffer()
2393 	intel_ring_emit(ring, MI_NOOP);  in gen8_ring_dispatch_execbuffer()
2410 	intel_ring_emit(ring,  in hsw_ring_dispatch_execbuffer()
2415 	intel_ring_emit(ring, offset);  in hsw_ring_dispatch_execbuffer()
2432 	intel_ring_emit(ring,  in gen6_ring_dispatch_execbuffer()
2437 	intel_ring_emit(ring, offset);  in gen6_ring_dispatch_execbuffer()
2475 	intel_ring_emit(ring, cmd);  in gen6_ring_flush()
2476 	intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);  in gen6_ring_flush()
2478 		intel_ring_emit(ring, 0); /* upper addr */  in gen6_ring_flush()
2479 		intel_ring_emit(ring, 0); /* value */  in gen6_ring_flush()
2481 		intel_ring_emit(ring, 0);  in gen6_ring_flush()
2482 		intel_ring_emit(ring, MI_NOOP);  in gen6_ring_flush()