Searched refs:inst (Results 1 - 200 of 404) sorted by relevance

123

/linux-4.1.27/arch/arm/vfp/
H A Dvfpinstr.h13 #define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000)
14 #define INST_CPRT(inst) ((inst) & (1 << 4))
15 #define INST_CPRT_L(inst) ((inst) & (1 << 20))
16 #define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12)
17 #define INST_CPRT_OP(inst) (((inst) >> 21) & 7)
18 #define INST_CPNUM(inst) ((inst) & 0xf00)
33 #define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4)
52 #define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
54 #define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
55 #define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18)
56 #define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
57 #define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1)
58 #define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
59 #define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3)
61 #define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
85 u32 vfp_single_cpdo(u32 inst, u32 fpscr);
86 u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs);
88 u32 vfp_double_cpdo(u32 inst, u32 fpscr);
/linux-4.1.27/arch/powerpc/include/asm/
H A Ddisassemble.h25 static inline unsigned int get_op(u32 inst) get_op() argument
27 return inst >> 26; get_op()
30 static inline unsigned int get_xop(u32 inst) get_xop() argument
32 return (inst >> 1) & 0x3ff; get_xop()
35 static inline unsigned int get_sprn(u32 inst) get_sprn() argument
37 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); get_sprn()
40 static inline unsigned int get_dcrn(u32 inst) get_dcrn() argument
42 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); get_dcrn()
45 static inline unsigned int get_rt(u32 inst) get_rt() argument
47 return (inst >> 21) & 0x1f; get_rt()
50 static inline unsigned int get_rs(u32 inst) get_rs() argument
52 return (inst >> 21) & 0x1f; get_rs()
55 static inline unsigned int get_ra(u32 inst) get_ra() argument
57 return (inst >> 16) & 0x1f; get_ra()
60 static inline unsigned int get_rb(u32 inst) get_rb() argument
62 return (inst >> 11) & 0x1f; get_rb()
65 static inline unsigned int get_rc(u32 inst) get_rc() argument
67 return inst & 0x1; get_rc()
70 static inline unsigned int get_ws(u32 inst) get_ws() argument
72 return (inst >> 11) & 0x1f; get_ws()
75 static inline unsigned int get_d(u32 inst) get_d() argument
77 return inst & 0xffff; get_d()
80 static inline unsigned int get_oc(u32 inst) get_oc() argument
82 return (inst >> 11) & 0x7fff; get_oc()
85 #define IS_XFORM(inst) (get_op(inst) == 31)
86 #define IS_DSFORM(inst) (get_op(inst) >= 56)
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
H A Diop_version_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sap_in_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sap_out_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_spu_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_cfg_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_cpu_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_mpu_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/
H A Ddma.h75 #define DMA_ENABLE( inst ) \
76 do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
78 REG_WR( dma, inst, rw_cfg, e); } while( 0 )
81 #define DMA_RESET( inst ) \
82 do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
84 REG_WR( dma, inst, rw_cfg, r); } while( 0 )
87 #define DMA_STOP( inst ) \
88 do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
90 REG_WR( dma, inst, rw_cfg, s); } while( 0 )
93 #define DMA_CONTINUE( inst ) \
94 do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
96 REG_WR( dma, inst, rw_cfg, c); } while( 0 )
99 #define DMA_WR_CMD( inst, cmd_par ) \
101 do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \
103 REG_WR(dma, inst, rw_stream_cmd, __x); \
107 #define DMA_START_GROUP( inst, group_descr ) \
108 do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
109 DMA_WR_CMD( inst, regk_dma_load_g ); \
110 DMA_WR_CMD( inst, regk_dma_load_c ); \
111 DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
115 #define DMA_START_CONTEXT( inst, ctx_descr ) \
116 do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
117 DMA_WR_CMD( inst, regk_dma_load_c ); \
118 DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
122 #define DMA_CONTINUE_DATA( inst ) \
125 REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
H A Dstrcop_defs.h6 * file: ../../inst/strcop/rtl/strcop_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dirq_nmi_defs.h18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Drt_trace_defs.h6 * file: ../../inst/rt_trace/rtl/rt_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dconfig_defs.h18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Data_defs.h6 * file: ../../inst/ata/rtl/ata_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dbif_slave_defs.h6 * file: ../../inst/bif/rtl/bif_slave_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dmarb_defs.h6 * file: ../../inst/memarb/rtl/guinness/marb_top.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
265 * file: ../../inst/memarb/rtl/guinness/marb_top.r
269 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
277 #define REG_RD( scope, inst, reg ) \
279 (inst) + REG_RD_ADDR_##scope##_##reg )
283 #define REG_WR( scope, inst, reg, val ) \
285 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
289 #define REG_RD_VECT( scope, inst, reg, index ) \
291 (inst) + REG_RD_ADDR_##scope##_##reg + \
296 #define REG_WR_VECT( scope, inst, reg, index, val ) \
298 (inst) + REG_WR_ADDR_##scope##_##reg + \
303 #define REG_RD_INT( scope, inst, reg ) \
304 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
308 #define REG_WR_INT( scope, inst, reg, val ) \
309 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
313 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
314 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
319 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
320 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
334 #define REG_ADDR( scope, inst, reg ) \
335 ( (inst) + REG_RD_ADDR_##scope##_##reg )
339 #define REG_ADDR_VECT( scope, inst, reg, index ) \
340 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dmarb_bp_defs.h6 * file: ../../inst/memarb/rtl/guinness/marb_top.r
10 * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
H A Dbif_core_defs.h6 * file: ../../inst/bif/rtl/bif_core_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dextmem_defs.h6 * file: ../../inst/ext_mem/mod/extmem_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dser_defs.h6 * file: ../../inst/ser/rtl/ser_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dsser_defs.h6 * file: ../../inst/syncser/rtl/sser_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Deth_defs.h18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Ddma_defs.h6 * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dbif_dma_defs.h6 * file: ../../inst/bif/rtl/bif_dma_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dcpu_vect.h2 from ../../inst/crisp/doc/cpu_vect.r
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/iop/
H A Diop_version_defs.h6 * file: ../../inst/io_proc/rtl/guinness/iop_version.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_fifo_in_extra_defs.h6 * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_fifo_out_extra_defs.h6 * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_scrc_in_defs.h6 * file: ../../inst/io_proc/rtl/iop_scrc_in.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_scrc_out_defs.h6 * file: ../../inst/io_proc/rtl/iop_scrc_out.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_trigger_grp_defs.h6 * file: ../../inst/io_proc/rtl/iop_trigger_grp.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_crc_par_defs.h6 * file: ../../inst/io_proc/rtl/iop_crc_par.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_fifo_in_defs.h6 * file: ../../inst/io_proc/rtl/iop_fifo_in.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_mpu_defs.h6 * file: ../../inst/io_proc/rtl/iop_mpu.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sap_in_defs.h6 * file: ../../inst/io_proc/rtl/iop_sap_in.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_timer_grp_defs.h6 * file: ../../inst/io_proc/rtl/iop_timer_grp.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_dmc_in_defs.h6 * file: ../../inst/io_proc/rtl/iop_dmc_in.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_dmc_out_defs.h6 * file: ../../inst/io_proc/rtl/iop_dmc_out.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_fifo_out_defs.h6 * file: ../../inst/io_proc/rtl/iop_fifo_out.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sap_out_defs.h6 * file: ../../inst/io_proc/rtl/iop_sap_out.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_spu_defs.h6 * file: ../../inst/io_proc/rtl/iop_spu.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_spu_defs.h6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_cfg_defs.h6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_cpu_defs.h6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_mpu_defs.h6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
H A Dstrmux_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dclkgen_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dl2cache_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dmarb_bar_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
299 #define REG_RD( scope, inst, reg ) \
301 (inst) + REG_RD_ADDR_##scope##_##reg )
305 #define REG_WR( scope, inst, reg, val ) \
307 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
311 #define REG_RD_VECT( scope, inst, reg, index ) \
313 (inst) + REG_RD_ADDR_##scope##_##reg + \
318 #define REG_WR_VECT( scope, inst, reg, index, val ) \
320 (inst) + REG_WR_ADDR_##scope##_##reg + \
325 #define REG_RD_INT( scope, inst, reg ) \
326 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
330 #define REG_WR_INT( scope, inst, reg, val ) \
331 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
335 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
336 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
341 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
342 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
356 #define REG_ADDR( scope, inst, reg ) \
357 ( (inst) + REG_RD_ADDR_##scope##_##reg )
361 #define REG_ADDR_VECT( scope, inst, reg, index ) \
362 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dmarb_foo_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
425 #define REG_RD( scope, inst, reg ) \
427 (inst) + REG_RD_ADDR_##scope##_##reg )
431 #define REG_WR( scope, inst, reg, val ) \
433 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
437 #define REG_RD_VECT( scope, inst, reg, index ) \
439 (inst) + REG_RD_ADDR_##scope##_##reg + \
444 #define REG_WR_VECT( scope, inst, reg, index, val ) \
446 (inst) + REG_WR_ADDR_##scope##_##reg + \
451 #define REG_RD_INT( scope, inst, reg ) \
452 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
456 #define REG_WR_INT( scope, inst, reg, val ) \
457 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
461 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
462 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
467 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
468 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
482 #define REG_ADDR( scope, inst, reg ) \
483 ( (inst) + REG_RD_ADDR_##scope##_##reg )
487 #define REG_ADDR_VECT( scope, inst, reg, index ) \
488 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dddr2_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dintr_vect_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dpinmux_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dpio_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dtimer_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dgio_defs.h15 #define REG_RD( scope, inst, reg ) \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-4.1.27/arch/arm64/kernel/
H A Dkuser32.S38 .inst 0xe92d00f0 // push {r4, r5, r6, r7}
39 .inst 0xe1c040d0 // ldrd r4, r5, [r0]
40 .inst 0xe1c160d0 // ldrd r6, r7, [r1]
41 .inst 0xe1b20f9f // 1: ldrexd r0, r1, [r2]
42 .inst 0xe0303004 // eors r3, r0, r4
43 .inst 0x00313005 // eoreqs r3, r1, r5
44 .inst 0x01a23e96 // stlexdeq r3, r6, [r2]
45 .inst 0x03330001 // teqeq r3, #1
46 .inst 0x0afffff9 // beq 1b
47 .inst 0xf57ff05b // dmb ish
48 .inst 0xe2730000 // rsbs r0, r3, #0
49 .inst 0xe8bd00f0 // pop {r4, r5, r6, r7}
50 .inst 0xe12fff1e // bx lr
54 .inst 0xf57ff05b // dmb ish
55 .inst 0xe12fff1e // bx lr
59 .inst 0xe1923f9f // 1: ldrex r3, [r2]
60 .inst 0xe0533000 // subs r3, r3, r0
61 .inst 0x01823e91 // stlexeq r3, r1, [r2]
62 .inst 0x03330001 // teqeq r3, #1
63 .inst 0x0afffffa // beq 1b
64 .inst 0xf57ff05b // dmb ish
65 .inst 0xe2730000 // rsbs r0, r3, #0
66 .inst 0xe12fff1e // bx lr
70 .inst 0xee1d0f70 // mrc p15, 0, r0, c13, c0, 3
71 .inst 0xe12fff1e // bx lr
/linux-4.1.27/arch/powerpc/kernel/
H A Dkvm.c80 static inline void kvm_patch_ins(u32 *inst, u32 new_inst) kvm_patch_ins() argument
82 *inst = new_inst; kvm_patch_ins()
83 flush_icache_range((ulong)inst, (ulong)inst + 4); kvm_patch_ins()
86 static void kvm_patch_ins_ll(u32 *inst, long addr, u32 rt) kvm_patch_ins_ll() argument
89 kvm_patch_ins(inst, KVM_INST_LD | rt | (addr & 0x0000fffc)); kvm_patch_ins_ll()
91 kvm_patch_ins(inst, KVM_INST_LWZ | rt | (addr & 0x0000fffc)); kvm_patch_ins_ll()
95 static void kvm_patch_ins_ld(u32 *inst, long addr, u32 rt) kvm_patch_ins_ld() argument
98 kvm_patch_ins(inst, KVM_INST_LD | rt | (addr & 0x0000fffc)); kvm_patch_ins_ld()
100 kvm_patch_ins(inst, KVM_INST_LWZ | rt | ((addr + 4) & 0x0000fffc)); kvm_patch_ins_ld()
104 static void kvm_patch_ins_lwz(u32 *inst, long addr, u32 rt) kvm_patch_ins_lwz() argument
106 kvm_patch_ins(inst, KVM_INST_LWZ | rt | (addr & 0x0000ffff)); kvm_patch_ins_lwz()
109 static void kvm_patch_ins_std(u32 *inst, long addr, u32 rt) kvm_patch_ins_std() argument
112 kvm_patch_ins(inst, KVM_INST_STD | rt | (addr & 0x0000fffc)); kvm_patch_ins_std()
114 kvm_patch_ins(inst, KVM_INST_STW | rt | ((addr + 4) & 0x0000fffc)); kvm_patch_ins_std()
118 static void kvm_patch_ins_stw(u32 *inst, long addr, u32 rt) kvm_patch_ins_stw() argument
120 kvm_patch_ins(inst, KVM_INST_STW | rt | (addr & 0x0000fffc)); kvm_patch_ins_stw()
123 static void kvm_patch_ins_nop(u32 *inst) kvm_patch_ins_nop() argument
125 kvm_patch_ins(inst, KVM_INST_NOP); kvm_patch_ins_nop()
128 static void kvm_patch_ins_b(u32 *inst, int addr) kvm_patch_ins_b() argument
134 if ((ulong)inst < (ulong)&__end_interrupts) kvm_patch_ins_b()
138 kvm_patch_ins(inst, KVM_INST_B | (addr & KVM_INST_B_MASK)); kvm_patch_ins_b()
164 static void kvm_patch_ins_mtmsrd(u32 *inst, u32 rt) kvm_patch_ins_mtmsrd() argument
176 distance_start = (ulong)p - (ulong)inst; kvm_patch_ins_mtmsrd()
177 next_inst = ((ulong)inst + 4); kvm_patch_ins_mtmsrd()
203 p[kvm_emulate_mtmsrd_orig_ins_offs] = *inst; kvm_patch_ins_mtmsrd()
207 kvm_patch_ins_b(inst, distance_start); kvm_patch_ins_mtmsrd()
217 static void kvm_patch_ins_mtmsr(u32 *inst, u32 rt) kvm_patch_ins_mtmsr() argument
229 distance_start = (ulong)p - (ulong)inst; kvm_patch_ins_mtmsr()
230 next_inst = ((ulong)inst + 4); kvm_patch_ins_mtmsr()
263 p[kvm_emulate_mtmsr_orig_ins_offs] = *inst; kvm_patch_ins_mtmsr()
267 kvm_patch_ins_b(inst, distance_start); kvm_patch_ins_mtmsr()
278 static void kvm_patch_ins_wrtee(u32 *inst, u32 rt, int imm_one) kvm_patch_ins_wrtee() argument
290 distance_start = (ulong)p - (ulong)inst; kvm_patch_ins_wrtee()
291 next_inst = ((ulong)inst + 4); kvm_patch_ins_wrtee()
324 p[kvm_emulate_wrtee_orig_ins_offs] = *inst; kvm_patch_ins_wrtee()
328 kvm_patch_ins_b(inst, distance_start); kvm_patch_ins_wrtee()
335 static void kvm_patch_ins_wrteei_0(u32 *inst) kvm_patch_ins_wrteei_0() argument
347 distance_start = (ulong)p - (ulong)inst; kvm_patch_ins_wrteei_0()
348 next_inst = ((ulong)inst + 4); kvm_patch_ins_wrteei_0()
362 kvm_patch_ins_b(inst, distance_start); kvm_patch_ins_wrteei_0()
376 static void kvm_patch_ins_mtsrin(u32 *inst, u32 rt, u32 rb) kvm_patch_ins_mtsrin() argument
388 distance_start = (ulong)p - (ulong)inst; kvm_patch_ins_mtsrin()
389 next_inst = ((ulong)inst + 4); kvm_patch_ins_mtsrin()
403 p[kvm_emulate_mtsrin_orig_ins_offs] = *inst; kvm_patch_ins_mtsrin()
407 kvm_patch_ins_b(inst, distance_start); kvm_patch_ins_mtsrin()
427 static void kvm_check_ins(u32 *inst, u32 features) kvm_check_ins() argument
429 u32 _inst = *inst; kvm_check_ins()
436 kvm_patch_ins_ld(inst, magic_var(msr), inst_rt); kvm_check_ins()
439 kvm_patch_ins_ld(inst, magic_var(sprg0), inst_rt); kvm_check_ins()
442 kvm_patch_ins_ld(inst, magic_var(sprg1), inst_rt); kvm_check_ins()
445 kvm_patch_ins_ld(inst, magic_var(sprg2), inst_rt); kvm_check_ins()
448 kvm_patch_ins_ld(inst, magic_var(sprg3), inst_rt); kvm_check_ins()
451 kvm_patch_ins_ld(inst, magic_var(srr0), inst_rt); kvm_check_ins()
454 kvm_patch_ins_ld(inst, magic_var(srr1), inst_rt); kvm_check_ins()
461 kvm_patch_ins_ld(inst, magic_var(dar), inst_rt); kvm_check_ins()
464 kvm_patch_ins_lwz(inst, magic_var(dsisr), inst_rt); kvm_check_ins()
470 kvm_patch_ins_lwz(inst, magic_var(mas0), inst_rt); kvm_check_ins()
474 kvm_patch_ins_lwz(inst, magic_var(mas1), inst_rt); kvm_check_ins()
478 kvm_patch_ins_ld(inst, magic_var(mas2), inst_rt); kvm_check_ins()
482 kvm_patch_ins_lwz(inst, magic_var(mas7_3) + 4, inst_rt); kvm_check_ins()
486 kvm_patch_ins_lwz(inst, magic_var(mas4), inst_rt); kvm_check_ins()
490 kvm_patch_ins_lwz(inst, magic_var(mas6), inst_rt); kvm_check_ins()
494 kvm_patch_ins_lwz(inst, magic_var(mas7_3), inst_rt); kvm_check_ins()
503 kvm_patch_ins_ld(inst, magic_var(sprg4), inst_rt); kvm_check_ins()
510 kvm_patch_ins_ld(inst, magic_var(sprg5), inst_rt); kvm_check_ins()
517 kvm_patch_ins_ld(inst, magic_var(sprg6), inst_rt); kvm_check_ins()
524 kvm_patch_ins_ld(inst, magic_var(sprg7), inst_rt); kvm_check_ins()
530 kvm_patch_ins_lwz(inst, magic_var(esr), inst_rt); kvm_check_ins()
536 kvm_patch_ins_lwz(inst, magic_var(pir), inst_rt); kvm_check_ins()
542 kvm_patch_ins_std(inst, magic_var(sprg0), inst_rt); kvm_check_ins()
545 kvm_patch_ins_std(inst, magic_var(sprg1), inst_rt); kvm_check_ins()
548 kvm_patch_ins_std(inst, magic_var(sprg2), inst_rt); kvm_check_ins()
551 kvm_patch_ins_std(inst, magic_var(sprg3), inst_rt); kvm_check_ins()
554 kvm_patch_ins_std(inst, magic_var(srr0), inst_rt); kvm_check_ins()
557 kvm_patch_ins_std(inst, magic_var(srr1), inst_rt); kvm_check_ins()
564 kvm_patch_ins_std(inst, magic_var(dar), inst_rt); kvm_check_ins()
567 kvm_patch_ins_stw(inst, magic_var(dsisr), inst_rt); kvm_check_ins()
572 kvm_patch_ins_stw(inst, magic_var(mas0), inst_rt); kvm_check_ins()
576 kvm_patch_ins_stw(inst, magic_var(mas1), inst_rt); kvm_check_ins()
580 kvm_patch_ins_std(inst, magic_var(mas2), inst_rt); kvm_check_ins()
584 kvm_patch_ins_stw(inst, magic_var(mas7_3) + 4, inst_rt); kvm_check_ins()
588 kvm_patch_ins_stw(inst, magic_var(mas4), inst_rt); kvm_check_ins()
592 kvm_patch_ins_stw(inst, magic_var(mas6), inst_rt); kvm_check_ins()
596 kvm_patch_ins_stw(inst, magic_var(mas7_3), inst_rt); kvm_check_ins()
602 kvm_patch_ins_std(inst, magic_var(sprg4), inst_rt); kvm_check_ins()
606 kvm_patch_ins_std(inst, magic_var(sprg5), inst_rt); kvm_check_ins()
610 kvm_patch_ins_std(inst, magic_var(sprg6), inst_rt); kvm_check_ins()
614 kvm_patch_ins_std(inst, magic_var(sprg7), inst_rt); kvm_check_ins()
620 kvm_patch_ins_stw(inst, magic_var(esr), inst_rt); kvm_check_ins()
626 kvm_patch_ins_nop(inst); kvm_check_ins()
631 kvm_patch_ins_mtmsrd(inst, inst_rt); kvm_check_ins()
635 kvm_patch_ins_mtmsr(inst, inst_rt); kvm_check_ins()
639 kvm_patch_ins_wrtee(inst, inst_rt, 0); kvm_check_ins()
649 kvm_patch_ins_mtsrin(inst, inst_rt, inst_rb); kvm_check_ins()
659 kvm_patch_ins_wrteei_0(inst); kvm_check_ins()
663 kvm_patch_ins_wrtee(inst, 0, 1); kvm_check_ins()
H A Depapr_paravirt.c51 u32 inst = be32_to_cpu(insts[i]); early_init_dt_scan_epapr() local
52 patch_instruction(epapr_hypercall_start + i, inst); early_init_dt_scan_epapr()
54 patch_instruction(epapr_ev_idle_start + i, inst); early_init_dt_scan_epapr()
/linux-4.1.27/arch/x86/crypto/
H A Dfpu.c83 struct crypto_instance *inst = crypto_tfm_alg_instance(tfm); crypto_fpu_init_tfm() local
84 struct crypto_spawn *spawn = crypto_instance_ctx(inst); crypto_fpu_init_tfm()
104 struct crypto_instance *inst; crypto_fpu_alloc() local
117 inst = crypto_alloc_instance("fpu", alg); crypto_fpu_alloc()
118 if (IS_ERR(inst)) crypto_fpu_alloc()
121 inst->alg.cra_flags = alg->cra_flags; crypto_fpu_alloc()
122 inst->alg.cra_priority = alg->cra_priority; crypto_fpu_alloc()
123 inst->alg.cra_blocksize = alg->cra_blocksize; crypto_fpu_alloc()
124 inst->alg.cra_alignmask = alg->cra_alignmask; crypto_fpu_alloc()
125 inst->alg.cra_type = alg->cra_type; crypto_fpu_alloc()
126 inst->alg.cra_blkcipher.ivsize = alg->cra_blkcipher.ivsize; crypto_fpu_alloc()
127 inst->alg.cra_blkcipher.min_keysize = alg->cra_blkcipher.min_keysize; crypto_fpu_alloc()
128 inst->alg.cra_blkcipher.max_keysize = alg->cra_blkcipher.max_keysize; crypto_fpu_alloc()
129 inst->alg.cra_ctxsize = sizeof(struct crypto_fpu_ctx); crypto_fpu_alloc()
130 inst->alg.cra_init = crypto_fpu_init_tfm; crypto_fpu_alloc()
131 inst->alg.cra_exit = crypto_fpu_exit_tfm; crypto_fpu_alloc()
132 inst->alg.cra_blkcipher.setkey = crypto_fpu_setkey; crypto_fpu_alloc()
133 inst->alg.cra_blkcipher.encrypt = crypto_fpu_encrypt; crypto_fpu_alloc()
134 inst->alg.cra_blkcipher.decrypt = crypto_fpu_decrypt; crypto_fpu_alloc()
138 return inst; crypto_fpu_alloc()
141 static void crypto_fpu_free(struct crypto_instance *inst) crypto_fpu_free() argument
143 crypto_drop_spawn(crypto_instance_ctx(inst)); crypto_fpu_free()
144 kfree(inst); crypto_fpu_free()
/linux-4.1.27/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
H A Dstrmux_defs.h6 * file: ../../inst/strmux/rtl/guinness/strmux_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dconfig_defs.h18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dbif_slave_defs.h6 * file: ../../inst/bif/rtl/bif_slave_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dintr_vect_defs.h6 * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dmarb_defs.h6 * file: ../../inst/memarb/rtl/guinness/marb_top.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
265 * file: ../../inst/memarb/rtl/guinness/marb_top.r
269 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
277 #define REG_RD( scope, inst, reg ) \
279 (inst) + REG_RD_ADDR_##scope##_##reg )
283 #define REG_WR( scope, inst, reg, val ) \
285 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
289 #define REG_RD_VECT( scope, inst, reg, index ) \
291 (inst) + REG_RD_ADDR_##scope##_##reg + \
296 #define REG_WR_VECT( scope, inst, reg, index, val ) \
298 (inst) + REG_WR_ADDR_##scope##_##reg + \
303 #define REG_RD_INT( scope, inst, reg ) \
304 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
308 #define REG_WR_INT( scope, inst, reg, val ) \
309 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
313 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
314 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
319 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
320 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
334 #define REG_ADDR( scope, inst, reg ) \
335 ( (inst) + REG_RD_ADDR_##scope##_##reg )
339 #define REG_ADDR_VECT( scope, inst, reg, index ) \
340 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dmarb_bp_defs.h6 * file: ../../inst/memarb/rtl/guinness/marb_top.r
10 * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
H A Dbif_core_defs.h6 * file: ../../inst/bif/rtl/bif_core_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dgio_defs.h6 * file: ../../inst/gio/rtl/gio_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dpinmux_defs.h6 * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dtimer_defs.h6 * file: ../../inst/timer/rtl/timer_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dbif_dma_defs.h6 * file: ../../inst/bif/rtl/bif_dma_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
18 #define REG_RD( scope, inst, reg ) \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dreg_map.h16 * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
/linux-4.1.27/net/netfilter/
H A Dnfnetlink_log.c104 struct nfulnl_instance *inst; __instance_lookup() local
107 hlist_for_each_entry_rcu(inst, head, hlist) { hlist_for_each_entry_rcu()
108 if (inst->group_num == group_num) hlist_for_each_entry_rcu()
109 return inst; hlist_for_each_entry_rcu()
115 instance_get(struct nfulnl_instance *inst) instance_get() argument
117 atomic_inc(&inst->use); instance_get()
123 struct nfulnl_instance *inst; instance_lookup_get() local
126 inst = __instance_lookup(log, group_num); instance_lookup_get()
127 if (inst && !atomic_inc_not_zero(&inst->use)) instance_lookup_get()
128 inst = NULL; instance_lookup_get()
131 return inst; instance_lookup_get()
136 struct nfulnl_instance *inst = nfulnl_instance_free_rcu() local
139 put_net(inst->net); nfulnl_instance_free_rcu()
140 kfree(inst); nfulnl_instance_free_rcu()
145 instance_put(struct nfulnl_instance *inst) instance_put() argument
147 if (inst && atomic_dec_and_test(&inst->use)) instance_put()
148 call_rcu_bh(&inst->rcu, nfulnl_instance_free_rcu); instance_put()
157 struct nfulnl_instance *inst; instance_create() local
167 inst = kzalloc(sizeof(*inst), GFP_ATOMIC); instance_create()
168 if (!inst) { instance_create()
174 kfree(inst); instance_create()
179 INIT_HLIST_NODE(&inst->hlist); instance_create()
180 spin_lock_init(&inst->lock); instance_create()
182 atomic_set(&inst->use, 2); instance_create()
184 setup_timer(&inst->timer, nfulnl_timer, (unsigned long)inst); instance_create()
186 inst->net = get_net(net); instance_create()
187 inst->peer_user_ns = user_ns; instance_create()
188 inst->peer_portid = portid; instance_create()
189 inst->group_num = group_num; instance_create()
191 inst->qthreshold = NFULNL_QTHRESH_DEFAULT; instance_create()
192 inst->flushtimeout = NFULNL_TIMEOUT_DEFAULT; instance_create()
193 inst->nlbufsiz = NFULNL_NLBUFSIZ_DEFAULT; instance_create()
194 inst->copy_mode = NFULNL_COPY_PACKET; instance_create()
195 inst->copy_range = NFULNL_COPY_RANGE_MAX; instance_create()
197 hlist_add_head_rcu(&inst->hlist, instance_create()
203 return inst; instance_create()
210 static void __nfulnl_flush(struct nfulnl_instance *inst);
214 __instance_destroy(struct nfulnl_instance *inst) __instance_destroy() argument
217 hlist_del_rcu(&inst->hlist); __instance_destroy()
221 spin_lock(&inst->lock); __instance_destroy()
224 inst->copy_mode = NFULNL_COPY_DISABLED; __instance_destroy()
226 if (inst->skb) __instance_destroy()
227 __nfulnl_flush(inst); __instance_destroy()
228 spin_unlock(&inst->lock); __instance_destroy()
231 instance_put(inst); __instance_destroy()
236 struct nfulnl_instance *inst) instance_destroy()
239 __instance_destroy(inst); instance_destroy()
244 nfulnl_set_mode(struct nfulnl_instance *inst, u_int8_t mode, nfulnl_set_mode() argument
249 spin_lock_bh(&inst->lock); nfulnl_set_mode()
254 inst->copy_mode = mode; nfulnl_set_mode()
255 inst->copy_range = 0; nfulnl_set_mode()
259 inst->copy_mode = mode; nfulnl_set_mode()
262 inst->copy_range = min_t(unsigned int, nfulnl_set_mode()
271 spin_unlock_bh(&inst->lock); nfulnl_set_mode()
277 nfulnl_set_nlbufsiz(struct nfulnl_instance *inst, u_int32_t nlbufsiz) nfulnl_set_nlbufsiz() argument
281 spin_lock_bh(&inst->lock); nfulnl_set_nlbufsiz()
287 inst->nlbufsiz = nlbufsiz; nfulnl_set_nlbufsiz()
290 spin_unlock_bh(&inst->lock); nfulnl_set_nlbufsiz()
296 nfulnl_set_timeout(struct nfulnl_instance *inst, u_int32_t timeout) nfulnl_set_timeout() argument
298 spin_lock_bh(&inst->lock); nfulnl_set_timeout()
299 inst->flushtimeout = timeout; nfulnl_set_timeout()
300 spin_unlock_bh(&inst->lock); nfulnl_set_timeout()
306 nfulnl_set_qthresh(struct nfulnl_instance *inst, u_int32_t qthresh) nfulnl_set_qthresh() argument
308 spin_lock_bh(&inst->lock); nfulnl_set_qthresh()
309 inst->qthreshold = qthresh; nfulnl_set_qthresh()
310 spin_unlock_bh(&inst->lock); nfulnl_set_qthresh()
316 nfulnl_set_flags(struct nfulnl_instance *inst, u_int16_t flags) nfulnl_set_flags() argument
318 spin_lock_bh(&inst->lock); nfulnl_set_flags()
319 inst->flags = flags; nfulnl_set_flags()
320 spin_unlock_bh(&inst->lock); nfulnl_set_flags()
351 __nfulnl_send(struct nfulnl_instance *inst) __nfulnl_send() argument
353 if (inst->qlen > 1) { __nfulnl_send()
354 struct nlmsghdr *nlh = nlmsg_put(inst->skb, 0, 0, __nfulnl_send()
359 inst->skb->len, skb_tailroom(inst->skb))) { __nfulnl_send()
360 kfree_skb(inst->skb); __nfulnl_send()
364 nfnetlink_unicast(inst->skb, inst->net, inst->peer_portid, __nfulnl_send()
367 inst->qlen = 0; __nfulnl_send()
368 inst->skb = NULL; __nfulnl_send()
372 __nfulnl_flush(struct nfulnl_instance *inst) __nfulnl_flush() argument
375 if (del_timer(&inst->timer)) __nfulnl_flush()
376 instance_put(inst); __nfulnl_flush()
377 if (inst->skb) __nfulnl_flush()
378 __nfulnl_send(inst); __nfulnl_flush()
384 struct nfulnl_instance *inst = (struct nfulnl_instance *)data; nfulnl_timer() local
386 spin_lock_bh(&inst->lock); nfulnl_timer()
387 if (inst->skb) nfulnl_timer()
388 __nfulnl_send(inst); nfulnl_timer()
389 spin_unlock_bh(&inst->lock); nfulnl_timer()
390 instance_put(inst); nfulnl_timer()
397 struct nfulnl_instance *inst, __build_packet_message()
409 sk_buff_data_t old_tail = inst->skb->tail; __build_packet_message()
413 nlh = nlmsg_put(inst->skb, 0, 0, __build_packet_message()
421 nfmsg->res_id = htons(inst->group_num); __build_packet_message()
427 if (nla_put(inst->skb, NFULA_PACKET_HDR, sizeof(pmsg), &pmsg)) __build_packet_message()
431 nla_put(inst->skb, NFULA_PREFIX, plen, prefix)) __build_packet_message()
436 if (nla_put_be32(inst->skb, NFULA_IFINDEX_INDEV, __build_packet_message()
444 if (nla_put_be32(inst->skb, NFULA_IFINDEX_PHYSINDEV, __build_packet_message()
448 nla_put_be32(inst->skb, NFULA_IFINDEX_INDEV, __build_packet_message()
456 if (nla_put_be32(inst->skb, NFULA_IFINDEX_INDEV, __build_packet_message()
462 nla_put_be32(inst->skb, NFULA_IFINDEX_PHYSINDEV, __build_packet_message()
471 if (nla_put_be32(inst->skb, NFULA_IFINDEX_OUTDEV, __build_packet_message()
479 if (nla_put_be32(inst->skb, NFULA_IFINDEX_PHYSOUTDEV, __build_packet_message()
483 nla_put_be32(inst->skb, NFULA_IFINDEX_OUTDEV, __build_packet_message()
491 if (nla_put_be32(inst->skb, NFULA_IFINDEX_OUTDEV, __build_packet_message()
497 nla_put_be32(inst->skb, NFULA_IFINDEX_PHYSOUTDEV, __build_packet_message()
505 nla_put_be32(inst->skb, NFULA_MARK, htonl(skb->mark))) __build_packet_message()
517 if (nla_put(inst->skb, NFULA_HWADDR, sizeof(phw), &phw)) __build_packet_message()
523 if (nla_put_be16(inst->skb, NFULA_HWTYPE, htons(skb->dev->type)) || __build_packet_message()
524 nla_put_be16(inst->skb, NFULA_HWLEN, __build_packet_message()
534 nla_put(inst->skb, NFULA_HWHEADER, __build_packet_message()
545 if (nla_put(inst->skb, NFULA_TIMESTAMP, sizeof(ts), &ts)) __build_packet_message()
556 struct user_namespace *user_ns = inst->peer_user_ns; __build_packet_message()
560 if (nla_put_be32(inst->skb, NFULA_UID, uid) || __build_packet_message()
561 nla_put_be32(inst->skb, NFULA_GID, gid)) __build_packet_message()
568 if ((inst->flags & NFULNL_CFG_F_SEQ) && __build_packet_message()
569 nla_put_be32(inst->skb, NFULA_SEQ, htonl(inst->seq++))) __build_packet_message()
573 if ((inst->flags & NFULNL_CFG_F_SEQ_GLOBAL) && __build_packet_message()
574 nla_put_be32(inst->skb, NFULA_SEQ_GLOBAL, __build_packet_message()
582 if (skb_tailroom(inst->skb) < nla_total_size(data_len)) __build_packet_message()
585 nla = (struct nlattr *)skb_put(inst->skb, nla_total_size(data_len)); __build_packet_message()
593 nlh->nlmsg_len = inst->skb->tail - old_tail; __build_packet_message()
626 struct nfulnl_instance *inst; nfulnl_log_packet() local
637 inst = instance_lookup_get(log, li->u.ulog.group); nfulnl_log_packet()
638 if (!inst) nfulnl_log_packet()
670 spin_lock_bh(&inst->lock); nfulnl_log_packet()
672 if (inst->flags & NFULNL_CFG_F_SEQ) nfulnl_log_packet()
674 if (inst->flags & NFULNL_CFG_F_SEQ_GLOBAL) nfulnl_log_packet()
677 qthreshold = inst->qthreshold; nfulnl_log_packet()
684 switch (inst->copy_mode) { nfulnl_log_packet()
691 if (inst->copy_range > skb->len) nfulnl_log_packet()
694 data_len = inst->copy_range; nfulnl_log_packet()
704 if (inst->skb && size > skb_tailroom(inst->skb)) { nfulnl_log_packet()
707 __nfulnl_flush(inst); nfulnl_log_packet()
710 if (!inst->skb) { nfulnl_log_packet()
711 inst->skb = nfulnl_alloc_skb(net, inst->peer_portid, nfulnl_log_packet()
712 inst->nlbufsiz, size); nfulnl_log_packet()
713 if (!inst->skb) nfulnl_log_packet()
717 inst->qlen++; nfulnl_log_packet()
719 __build_packet_message(log, inst, skb, data_len, pf, nfulnl_log_packet()
722 if (inst->qlen >= qthreshold) nfulnl_log_packet()
723 __nfulnl_flush(inst); nfulnl_log_packet()
724 /* timer_pending always called within inst->lock, so there nfulnl_log_packet()
726 else if (!timer_pending(&inst->timer)) { nfulnl_log_packet()
727 instance_get(inst); nfulnl_log_packet()
728 inst->timer.expires = jiffies + (inst->flushtimeout*HZ/100); nfulnl_log_packet()
729 add_timer(&inst->timer); nfulnl_log_packet()
733 spin_unlock_bh(&inst->lock); nfulnl_log_packet()
734 instance_put(inst); nfulnl_log_packet()
757 struct nfulnl_instance *inst; nfulnl_rcv_nl_event() local
760 hlist_for_each_entry_safe(inst, t2, head, hlist) { hlist_for_each_entry_safe()
761 if (n->portid == inst->peer_portid) hlist_for_each_entry_safe()
762 __instance_destroy(inst); hlist_for_each_entry_safe()
805 struct nfulnl_instance *inst; nfulnl_recv_config() local
825 inst = instance_lookup_get(log, group_num); nfulnl_recv_config()
826 if (inst && inst->peer_portid != NETLINK_CB(skb).portid) { nfulnl_recv_config()
834 if (inst) { nfulnl_recv_config()
839 inst = instance_create(net, group_num, nfulnl_recv_config()
842 if (IS_ERR(inst)) { nfulnl_recv_config()
843 ret = PTR_ERR(inst); nfulnl_recv_config()
848 if (!inst) { nfulnl_recv_config()
853 instance_destroy(log, inst); nfulnl_recv_config()
865 if (!inst) { nfulnl_recv_config()
869 nfulnl_set_mode(inst, params->copy_mode, nfulnl_recv_config()
876 if (!inst) { nfulnl_recv_config()
880 nfulnl_set_timeout(inst, ntohl(timeout)); nfulnl_recv_config()
886 if (!inst) { nfulnl_recv_config()
890 nfulnl_set_nlbufsiz(inst, ntohl(nlbufsiz)); nfulnl_recv_config()
896 if (!inst) { nfulnl_recv_config()
900 nfulnl_set_qthresh(inst, ntohl(qthresh)); nfulnl_recv_config()
906 if (!inst) { nfulnl_recv_config()
910 nfulnl_set_flags(inst, ntohs(flags)); nfulnl_recv_config()
914 instance_put(inst); nfulnl_recv_config()
1008 const struct nfulnl_instance *inst = v; seq_show() local
1011 inst->group_num, seq_show()
1012 inst->peer_portid, inst->qlen, seq_show()
1013 inst->copy_mode, inst->copy_range, seq_show()
1014 inst->flushtimeout, atomic_read(&inst->use)); seq_show()
235 instance_destroy(struct nfnl_log_net *log, struct nfulnl_instance *inst) instance_destroy() argument
396 __build_packet_message(struct nfnl_log_net *log, struct nfulnl_instance *inst, const struct sk_buff *skb, unsigned int data_len, u_int8_t pf, unsigned int hooknum, const struct net_device *indev, const struct net_device *outdev, const char *prefix, unsigned int plen) __build_packet_message() argument
H A Dnfnetlink_queue_core.c102 struct nfqnl_instance *inst; instance_lookup() local
105 hlist_for_each_entry_rcu(inst, head, hlist) { hlist_for_each_entry_rcu()
106 if (inst->queue_num == queue_num) hlist_for_each_entry_rcu()
107 return inst; hlist_for_each_entry_rcu()
115 struct nfqnl_instance *inst; instance_create() local
125 inst = kzalloc(sizeof(*inst), GFP_ATOMIC); instance_create()
126 if (!inst) { instance_create()
131 inst->queue_num = queue_num; instance_create()
132 inst->peer_portid = portid; instance_create()
133 inst->queue_maxlen = NFQNL_QMAX_DEFAULT; instance_create()
134 inst->copy_range = NFQNL_MAX_COPY_RANGE; instance_create()
135 inst->copy_mode = NFQNL_COPY_NONE; instance_create()
136 spin_lock_init(&inst->lock); instance_create()
137 INIT_LIST_HEAD(&inst->queue_list); instance_create()
145 hlist_add_head_rcu(&inst->hlist, &q->instance_table[h]); instance_create()
149 return inst; instance_create()
152 kfree(inst); instance_create()
164 struct nfqnl_instance *inst = container_of(head, struct nfqnl_instance, instance_destroy_rcu() local
167 nfqnl_flush(inst, NULL, 0); instance_destroy_rcu()
168 kfree(inst); instance_destroy_rcu()
173 __instance_destroy(struct nfqnl_instance *inst) __instance_destroy() argument
175 hlist_del_rcu(&inst->hlist); __instance_destroy()
176 call_rcu(&inst->rcu, instance_destroy_rcu); __instance_destroy()
180 instance_destroy(struct nfnl_queue_net *q, struct nfqnl_instance *inst) instance_destroy() argument
183 __instance_destroy(inst); instance_destroy()
799 struct nfqnl_instance *inst; nfqnl_dev_drop() local
802 hlist_for_each_entry_rcu(inst, head, hlist) nfqnl_dev_drop()
803 nfqnl_flush(inst, dev_cmp, ifindex); nfqnl_dev_drop()
839 struct nfqnl_instance *inst; nfqnl_nf_hook_drop() local
842 hlist_for_each_entry_rcu(inst, head, hlist) nfqnl_nf_hook_drop()
843 nfqnl_flush(inst, nf_hook_cmp, (unsigned long)hook); nfqnl_nf_hook_drop()
862 struct nfqnl_instance *inst; nfqnl_rcv_nl_event() local
865 hlist_for_each_entry_safe(inst, t2, head, hlist) { hlist_for_each_entry_safe()
866 if (n->portid == inst->peer_portid) hlist_for_each_entry_safe()
867 __instance_destroy(inst); hlist_for_each_entry_safe()
1274 const struct nfqnl_instance *inst = v; seq_show() local
1277 inst->queue_num, seq_show()
1278 inst->peer_portid, inst->queue_total, seq_show()
1279 inst->copy_mode, inst->copy_range, seq_show()
1280 inst->queue_dropped, inst->queue_user_dropped, seq_show()
1281 inst->id_sequence, 1); seq_show()
/linux-4.1.27/arch/arm/mach-omap2/
H A Dprcm_mpu44xx.c31 u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg) omap4_prcm_mpu_read_inst_reg() argument
33 return readl_relaxed(OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); omap4_prcm_mpu_read_inst_reg()
36 void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg) omap4_prcm_mpu_write_inst_reg() argument
38 writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); omap4_prcm_mpu_write_inst_reg()
41 u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) omap4_prcm_mpu_rmw_inst_reg_bits() argument
45 v = omap4_prcm_mpu_read_inst_reg(inst, reg); omap4_prcm_mpu_rmw_inst_reg_bits()
48 omap4_prcm_mpu_write_inst_reg(v, inst, reg); omap4_prcm_mpu_rmw_inst_reg_bits()
H A Dcm33xx.c51 static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx) am33xx_cm_read_reg() argument
53 return readl_relaxed(cm_base + inst + idx); am33xx_cm_read_reg()
57 static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx) am33xx_cm_write_reg() argument
59 writel_relaxed(val, cm_base + inst + idx); am33xx_cm_write_reg()
63 static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) am33xx_cm_rmw_reg_bits() argument
67 v = am33xx_cm_read_reg(inst, idx); am33xx_cm_rmw_reg_bits()
70 am33xx_cm_write_reg(v, inst, idx); am33xx_cm_rmw_reg_bits()
77 * @inst: CM instance register offset (*_INST macro)
83 static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs) _clkctrl_idlest() argument
85 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs); _clkctrl_idlest()
93 * @inst: CM instance register offset (*_INST macro)
99 static bool _is_module_ready(u16 inst, u16 clkctrl_offs) _is_module_ready() argument
103 v = _clkctrl_idlest(inst, clkctrl_offs); _is_module_ready()
112 * @inst: CM instance register offset (*_INST macro)
118 static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs) _clktrctrl_write() argument
122 v = am33xx_cm_read_reg(inst, cdoffs); _clktrctrl_write()
125 am33xx_cm_write_reg(v, inst, cdoffs); _clktrctrl_write()
132 * @inst: CM instance register offset (*_INST macro)
135 * Returns true if the clockdomain referred to by (@inst, @cdoffs)
138 static bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs) am33xx_cm_is_clkdm_in_hwsup() argument
142 v = am33xx_cm_read_reg(inst, cdoffs); am33xx_cm_is_clkdm_in_hwsup()
151 * @inst: CM instance register offset (*_INST macro)
154 * Put a clockdomain referred to by (@inst, @cdoffs) into
157 static void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs) am33xx_cm_clkdm_enable_hwsup() argument
159 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs); am33xx_cm_clkdm_enable_hwsup()
164 * @inst: CM instance register offset (*_INST macro)
167 * Put a clockdomain referred to by (@inst, @cdoffs) into
171 static void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs) am33xx_cm_clkdm_disable_hwsup() argument
173 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs); am33xx_cm_clkdm_disable_hwsup()
178 * @inst: CM instance register offset (*_INST macro)
181 * Put a clockdomain referred to by (@inst, @cdoffs) into idle
184 static void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs) am33xx_cm_clkdm_force_sleep() argument
186 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs); am33xx_cm_clkdm_force_sleep()
191 * @inst: CM instance register offset (*_INST macro)
194 * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
197 static void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs) am33xx_cm_clkdm_force_wakeup() argument
199 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs); am33xx_cm_clkdm_force_wakeup()
209 * @inst: CM instance register offset (*_INST macro)
218 static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, am33xx_cm_wait_module_ready() argument
223 omap_test_timeout(_is_module_ready(inst, clkctrl_offs), am33xx_cm_wait_module_ready()
233 * @inst: CM instance register offset (*_INST macro)
241 static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, am33xx_cm_wait_module_idle() argument
249 omap_test_timeout((_clkctrl_idlest(inst, clkctrl_offs) == am33xx_cm_wait_module_idle()
260 * @inst: CM instance register offset (*_INST macro)
265 static void am33xx_cm_module_enable(u8 mode, u8 part, u16 inst, am33xx_cm_module_enable() argument
270 v = am33xx_cm_read_reg(inst, clkctrl_offs); am33xx_cm_module_enable()
273 am33xx_cm_write_reg(v, inst, clkctrl_offs); am33xx_cm_module_enable()
279 * @inst: CM instance register offset (*_INST macro)
284 static void am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) am33xx_cm_module_disable() argument
288 v = am33xx_cm_read_reg(inst, clkctrl_offs); am33xx_cm_module_disable()
290 am33xx_cm_write_reg(v, inst, clkctrl_offs); am33xx_cm_module_disable()
H A Dprminst44xx.h23 extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx);
24 extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
26 s16 inst, u16 idx);
30 extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
32 extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
35 s16 inst, u16 rstctrl_offs,
H A Dprminst44xx.c59 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) omap4_prminst_read_inst_reg() argument
64 return readl_relaxed(_prm_bases[part] + inst + idx); omap4_prminst_read_inst_reg()
68 void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) omap4_prminst_write_inst_reg() argument
73 writel_relaxed(val, _prm_bases[part] + inst + idx); omap4_prminst_write_inst_reg()
77 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, omap4_prminst_rmw_inst_reg_bits() argument
82 v = omap4_prminst_read_inst_reg(part, inst, idx); omap4_prminst_rmw_inst_reg_bits()
85 omap4_prminst_write_inst_reg(v, part, inst, idx); omap4_prminst_rmw_inst_reg_bits()
100 int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst, omap4_prminst_is_hardreset_asserted() argument
105 v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs); omap4_prminst_is_hardreset_asserted()
124 int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst, omap4_prminst_assert_hardreset() argument
129 omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs); omap4_prminst_assert_hardreset()
140 * @inst: PRM instance offset
153 int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst, omap4_prminst_deassert_hardreset() argument
161 if (omap4_prminst_is_hardreset_asserted(shift, part, inst, omap4_prminst_deassert_hardreset()
166 omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst, omap4_prminst_deassert_hardreset()
169 omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs); omap4_prminst_deassert_hardreset()
172 inst, rstst_offs), omap4_prminst_deassert_hardreset()
182 s32 inst = omap4_prmst_get_prm_dev_inst(); omap4_prminst_global_warm_sw_reset() local
184 if (inst == PRM_INSTANCE_UNKNOWN) omap4_prminst_global_warm_sw_reset()
187 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst, omap4_prminst_global_warm_sw_reset()
191 inst, OMAP4_PRM_RSTCTRL_OFFSET); omap4_prminst_global_warm_sw_reset()
195 inst, OMAP4_PRM_RSTCTRL_OFFSET); omap4_prminst_global_warm_sw_reset()
H A Dcminst44xx.c76 static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
81 * @inst: CM instance register offset (*_INST macro)
87 static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs) _clkctrl_idlest() argument
89 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); _clkctrl_idlest()
98 * @inst: CM instance register offset (*_INST macro)
104 static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs) _is_module_ready() argument
108 v = _clkctrl_idlest(part, inst, clkctrl_offs); _is_module_ready()
115 static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) omap4_cminst_read_inst_reg() argument
120 return readl_relaxed(_cm_bases[part] + inst + idx); omap4_cminst_read_inst_reg()
124 static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) omap4_cminst_write_inst_reg() argument
129 writel_relaxed(val, _cm_bases[part] + inst + idx); omap4_cminst_write_inst_reg()
133 static u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, omap4_cminst_rmw_inst_reg_bits() argument
138 v = omap4_cminst_read_inst_reg(part, inst, idx); omap4_cminst_rmw_inst_reg_bits()
141 omap4_cminst_write_inst_reg(v, part, inst, idx); omap4_cminst_rmw_inst_reg_bits()
146 static u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) omap4_cminst_set_inst_reg_bits() argument
148 return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); omap4_cminst_set_inst_reg_bits()
151 static u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, omap4_cminst_clear_inst_reg_bits() argument
154 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); omap4_cminst_clear_inst_reg_bits()
157 static u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) omap4_cminst_read_inst_reg_bits() argument
161 v = omap4_cminst_read_inst_reg(part, inst, idx); omap4_cminst_read_inst_reg_bits()
176 * @inst: CM instance register offset (*_INST macro)
182 static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs) _clktrctrl_write() argument
186 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); _clktrctrl_write()
189 omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); _clktrctrl_write()
195 * @inst: CM instance register offset (*_INST macro)
198 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
201 static bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs) omap4_cminst_is_clkdm_in_hwsup() argument
205 v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); omap4_cminst_is_clkdm_in_hwsup()
215 * @inst: CM instance register offset (*_INST macro)
218 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
221 static void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs) omap4_cminst_clkdm_enable_hwsup() argument
223 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); omap4_cminst_clkdm_enable_hwsup()
229 * @inst: CM instance register offset (*_INST macro)
232 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
236 static void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs) omap4_cminst_clkdm_disable_hwsup() argument
238 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); omap4_cminst_clkdm_disable_hwsup()
244 * @inst: CM instance register offset (*_INST macro)
247 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
250 static void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs) omap4_cminst_clkdm_force_wakeup() argument
252 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); omap4_cminst_clkdm_force_wakeup()
259 static void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs) omap4_cminst_clkdm_force_sleep() argument
261 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); omap4_cminst_clkdm_force_sleep()
267 * @inst: CM instance register offset (*_INST macro)
276 static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, omap4_cminst_wait_module_ready() argument
284 omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs), omap4_cminst_wait_module_ready()
294 * @inst: CM instance register offset (*_INST macro)
302 static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, omap4_cminst_wait_module_idle() argument
310 omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) == omap4_cminst_wait_module_idle()
321 * @inst: CM instance register offset (*_INST macro)
326 static void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, omap4_cminst_module_enable() argument
331 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); omap4_cminst_module_enable()
334 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); omap4_cminst_module_enable()
340 * @inst: CM instance register offset (*_INST macro)
345 static void omap4_cminst_module_disable(u8 part, u16 inst, u16 clkctrl_offs) omap4_cminst_module_disable() argument
349 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); omap4_cminst_module_disable()
351 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); omap4_cminst_module_disable()
H A Dprm44xx.c90 static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) omap4_prm_read_inst_reg() argument
92 return readl_relaxed(prm_base + inst + reg); omap4_prm_read_inst_reg()
96 static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) omap4_prm_write_inst_reg() argument
98 writel_relaxed(val, prm_base + inst + reg); omap4_prm_write_inst_reg()
102 static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) omap4_prm_rmw_inst_reg_bits() argument
106 v = omap4_prm_read_inst_reg(inst, reg); omap4_prm_rmw_inst_reg_bits()
109 omap4_prm_write_inst_reg(v, inst, reg); omap4_prm_rmw_inst_reg_bits()
164 s32 inst = omap4_prmst_get_prm_dev_inst(); omap4_prm_vcvp_read() local
166 if (inst == PRM_INSTANCE_UNKNOWN) omap4_prm_vcvp_read()
170 inst, offset); omap4_prm_vcvp_read()
175 s32 inst = omap4_prmst_get_prm_dev_inst(); omap4_prm_vcvp_write() local
177 if (inst == PRM_INSTANCE_UNKNOWN) omap4_prm_vcvp_write()
181 inst, offset); omap4_prm_vcvp_write()
186 s32 inst = omap4_prmst_get_prm_dev_inst(); omap4_prm_vcvp_rmw() local
188 if (inst == PRM_INSTANCE_UNKNOWN) omap4_prm_vcvp_rmw()
193 inst, omap4_prm_vcvp_rmw()
300 s32 inst = omap4_prmst_get_prm_dev_inst(); omap44xx_prm_reconfigure_io_chain() local
302 if (inst == PRM_INSTANCE_UNKNOWN) omap44xx_prm_reconfigure_io_chain()
308 inst, omap44xx_prm_reconfigure_io_chain()
311 (((omap4_prm_read_inst_reg(inst, omap44xx_prm_reconfigure_io_chain()
321 inst, omap44xx_prm_reconfigure_io_chain()
324 (((omap4_prm_read_inst_reg(inst, omap44xx_prm_reconfigure_io_chain()
345 s32 inst = omap4_prmst_get_prm_dev_inst(); omap44xx_prm_enable_io_wakeup() local
347 if (inst == PRM_INSTANCE_UNKNOWN) omap44xx_prm_enable_io_wakeup()
352 inst, omap44xx_prm_enable_io_wakeup()
367 s32 inst = omap4_prmst_get_prm_dev_inst(); omap44xx_prm_read_reset_sources() local
369 if (inst == PRM_INSTANCE_UNKNOWN) omap44xx_prm_read_reset_sources()
373 v = omap4_prm_read_inst_reg(inst, omap44xx_prm_read_reset_sources()
389 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
393 * identified by (@part, @inst, @idx), which means that some context
396 static bool omap44xx_prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx) omap44xx_prm_was_any_context_lost_old() argument
398 return (omap4_prminst_read_inst_reg(part, inst, idx)) ? 1 : 0; omap44xx_prm_was_any_context_lost_old()
404 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
408 * (@part, @inst, @idx). No return value. XXX Writes to reserved bits;
411 static void omap44xx_prm_clear_context_loss_flags_old(u8 part, s16 inst, omap44xx_prm_clear_context_loss_flags_old() argument
414 omap4_prminst_write_inst_reg(0xffffffff, part, inst, idx); omap44xx_prm_clear_context_loss_flags_old()
H A Dprm33xx.c31 static u32 am33xx_prm_read_reg(s16 inst, u16 idx) am33xx_prm_read_reg() argument
33 return readl_relaxed(prm_base + inst + idx); am33xx_prm_read_reg()
37 static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) am33xx_prm_write_reg() argument
39 writel_relaxed(val, prm_base + inst + idx); am33xx_prm_write_reg()
43 static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) am33xx_prm_rmw_reg_bits() argument
47 v = am33xx_prm_read_reg(inst, idx); am33xx_prm_rmw_reg_bits()
50 am33xx_prm_write_reg(v, inst, idx); am33xx_prm_rmw_reg_bits()
60 * @inst: CM instance register offset (*_INST macro)
67 static int am33xx_prm_is_hardreset_asserted(u8 shift, u8 part, s16 inst, am33xx_prm_is_hardreset_asserted() argument
72 v = am33xx_prm_read_reg(inst, rstctrl_offs); am33xx_prm_is_hardreset_asserted()
83 * @inst: CM instance register offset (*_INST macro)
93 static int am33xx_prm_assert_hardreset(u8 shift, u8 part, s16 inst, am33xx_prm_assert_hardreset() argument
98 am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs); am33xx_prm_assert_hardreset()
109 * @inst: CM instance register offset (*_INST macro)
123 s16 inst, u16 rstctrl_offs, am33xx_prm_deassert_hardreset()
130 if (am33xx_prm_is_hardreset_asserted(shift, 0, inst, rstctrl_offs) == 0) am33xx_prm_deassert_hardreset()
134 am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs); am33xx_prm_deassert_hardreset()
139 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs); am33xx_prm_deassert_hardreset()
142 omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, 0, inst, am33xx_prm_deassert_hardreset()
122 am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst, u16 rstctrl_offs, u16 rstst_offs) am33xx_prm_deassert_hardreset() argument
H A Dprcm_mpu_44xx_54xx.h29 extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
30 extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
31 extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
H A Dcm.h59 void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
60 void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
69 int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
70 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
H A Dprcm_mpu7xx.h29 #define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \
30 OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
/linux-4.1.27/crypto/
H A Dctr.c160 struct crypto_instance *inst = (void *)tfm->__crt_alg; crypto_ctr_init_tfm() local
161 struct crypto_spawn *spawn = crypto_instance_ctx(inst); crypto_ctr_init_tfm()
183 struct crypto_instance *inst; crypto_ctr_alloc() local
205 inst = crypto_alloc_instance("ctr", alg); crypto_ctr_alloc()
206 if (IS_ERR(inst)) crypto_ctr_alloc()
209 inst->alg.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER; crypto_ctr_alloc()
210 inst->alg.cra_priority = alg->cra_priority; crypto_ctr_alloc()
211 inst->alg.cra_blocksize = 1; crypto_ctr_alloc()
212 inst->alg.cra_alignmask = alg->cra_alignmask | (__alignof__(u32) - 1); crypto_ctr_alloc()
213 inst->alg.cra_type = &crypto_blkcipher_type; crypto_ctr_alloc()
215 inst->alg.cra_blkcipher.ivsize = alg->cra_blocksize; crypto_ctr_alloc()
216 inst->alg.cra_blkcipher.min_keysize = alg->cra_cipher.cia_min_keysize; crypto_ctr_alloc()
217 inst->alg.cra_blkcipher.max_keysize = alg->cra_cipher.cia_max_keysize; crypto_ctr_alloc()
219 inst->alg.cra_ctxsize = sizeof(struct crypto_ctr_ctx); crypto_ctr_alloc()
221 inst->alg.cra_init = crypto_ctr_init_tfm; crypto_ctr_alloc()
222 inst->alg.cra_exit = crypto_ctr_exit_tfm; crypto_ctr_alloc()
224 inst->alg.cra_blkcipher.setkey = crypto_ctr_setkey; crypto_ctr_alloc()
225 inst->alg.cra_blkcipher.encrypt = crypto_ctr_crypt; crypto_ctr_alloc()
226 inst->alg.cra_blkcipher.decrypt = crypto_ctr_crypt; crypto_ctr_alloc()
228 inst->alg.cra_blkcipher.geniv = "chainiv"; crypto_ctr_alloc()
232 return inst; crypto_ctr_alloc()
235 inst = ERR_PTR(err); crypto_ctr_alloc()
239 static void crypto_ctr_free(struct crypto_instance *inst) crypto_ctr_free() argument
241 crypto_drop_spawn(crypto_instance_ctx(inst)); crypto_ctr_free()
242 kfree(inst); crypto_ctr_free()
308 struct crypto_instance *inst = (void *)tfm->__crt_alg; crypto_rfc3686_init_tfm() local
309 struct crypto_skcipher_spawn *spawn = crypto_instance_ctx(inst); crypto_rfc3686_init_tfm()
339 struct crypto_instance *inst; crypto_rfc3686_alloc() local
356 inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL); crypto_rfc3686_alloc()
357 if (!inst) crypto_rfc3686_alloc()
360 spawn = crypto_instance_ctx(inst); crypto_rfc3686_alloc()
362 crypto_set_skcipher_spawn(spawn, inst); crypto_rfc3686_alloc()
381 if (snprintf(inst->alg.cra_name, CRYPTO_MAX_ALG_NAME, "rfc3686(%s)", crypto_rfc3686_alloc()
384 if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, crypto_rfc3686_alloc()
389 inst->alg.cra_priority = alg->cra_priority; crypto_rfc3686_alloc()
390 inst->alg.cra_blocksize = 1; crypto_rfc3686_alloc()
391 inst->alg.cra_alignmask = alg->cra_alignmask; crypto_rfc3686_alloc()
393 inst->alg.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | crypto_rfc3686_alloc()
395 inst->alg.cra_type = &crypto_ablkcipher_type; crypto_rfc3686_alloc()
397 inst->alg.cra_ablkcipher.ivsize = CTR_RFC3686_IV_SIZE; crypto_rfc3686_alloc()
398 inst->alg.cra_ablkcipher.min_keysize = crypto_rfc3686_alloc()
400 inst->alg.cra_ablkcipher.max_keysize = crypto_rfc3686_alloc()
403 inst->alg.cra_ablkcipher.geniv = "seqiv"; crypto_rfc3686_alloc()
405 inst->alg.cra_ablkcipher.setkey = crypto_rfc3686_setkey; crypto_rfc3686_alloc()
406 inst->alg.cra_ablkcipher.encrypt = crypto_rfc3686_crypt; crypto_rfc3686_alloc()
407 inst->alg.cra_ablkcipher.decrypt = crypto_rfc3686_crypt; crypto_rfc3686_alloc()
409 inst->alg.cra_ctxsize = sizeof(struct crypto_rfc3686_ctx); crypto_rfc3686_alloc()
411 inst->alg.cra_init = crypto_rfc3686_init_tfm; crypto_rfc3686_alloc()
412 inst->alg.cra_exit = crypto_rfc3686_exit_tfm; crypto_rfc3686_alloc()
414 return inst; crypto_rfc3686_alloc()
419 kfree(inst); crypto_rfc3686_alloc()
423 static void crypto_rfc3686_free(struct crypto_instance *inst) crypto_rfc3686_free() argument
425 struct crypto_skcipher_spawn *spawn = crypto_instance_ctx(inst); crypto_rfc3686_free()
428 kfree(inst); crypto_rfc3686_free()
H A Dseqiv.c263 struct crypto_instance *inst; seqiv_ablkcipher_alloc() local
265 inst = skcipher_geniv_alloc(&seqiv_tmpl, tb, 0, 0); seqiv_ablkcipher_alloc()
267 if (IS_ERR(inst)) seqiv_ablkcipher_alloc()
270 if (inst->alg.cra_ablkcipher.ivsize < sizeof(u64)) { seqiv_ablkcipher_alloc()
271 skcipher_geniv_free(inst); seqiv_ablkcipher_alloc()
272 inst = ERR_PTR(-EINVAL); seqiv_ablkcipher_alloc()
276 inst->alg.cra_ablkcipher.givencrypt = seqiv_givencrypt_first; seqiv_ablkcipher_alloc()
278 inst->alg.cra_init = seqiv_init; seqiv_ablkcipher_alloc()
279 inst->alg.cra_exit = skcipher_geniv_exit; seqiv_ablkcipher_alloc()
281 inst->alg.cra_ctxsize += inst->alg.cra_ablkcipher.ivsize; seqiv_ablkcipher_alloc()
284 return inst; seqiv_ablkcipher_alloc()
289 struct crypto_instance *inst; seqiv_aead_alloc() local
291 inst = aead_geniv_alloc(&seqiv_tmpl, tb, 0, 0); seqiv_aead_alloc()
293 if (IS_ERR(inst)) seqiv_aead_alloc()
296 if (inst->alg.cra_aead.ivsize < sizeof(u64)) { seqiv_aead_alloc()
297 aead_geniv_free(inst); seqiv_aead_alloc()
298 inst = ERR_PTR(-EINVAL); seqiv_aead_alloc()
302 inst->alg.cra_aead.givencrypt = seqiv_aead_givencrypt_first; seqiv_aead_alloc()
304 inst->alg.cra_init = seqiv_aead_init; seqiv_aead_alloc()
305 inst->alg.cra_exit = aead_geniv_exit; seqiv_aead_alloc()
307 inst->alg.cra_ctxsize = inst->alg.cra_aead.ivsize; seqiv_aead_alloc()
310 return inst; seqiv_aead_alloc()
316 struct crypto_instance *inst; seqiv_alloc() local
328 inst = seqiv_ablkcipher_alloc(tb); seqiv_alloc()
330 inst = seqiv_aead_alloc(tb); seqiv_alloc()
332 if (IS_ERR(inst)) seqiv_alloc()
335 inst->alg.cra_alignmask |= __alignof__(u32) - 1; seqiv_alloc()
336 inst->alg.cra_ctxsize += sizeof(struct seqiv_ctx); seqiv_alloc()
339 return inst; seqiv_alloc()
346 static void seqiv_free(struct crypto_instance *inst) seqiv_free() argument
348 if ((inst->alg.cra_flags ^ CRYPTO_ALG_TYPE_AEAD) & CRYPTO_ALG_TYPE_MASK) seqiv_free()
349 skcipher_geniv_free(inst); seqiv_free()
351 aead_geniv_free(inst); seqiv_free()
H A Decb.c99 struct crypto_instance *inst = (void *)tfm->__crt_alg; crypto_ecb_init_tfm() local
100 struct crypto_spawn *spawn = crypto_instance_ctx(inst); crypto_ecb_init_tfm()
120 struct crypto_instance *inst; crypto_ecb_alloc() local
133 inst = crypto_alloc_instance("ecb", alg); crypto_ecb_alloc()
134 if (IS_ERR(inst)) crypto_ecb_alloc()
137 inst->alg.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER; crypto_ecb_alloc()
138 inst->alg.cra_priority = alg->cra_priority; crypto_ecb_alloc()
139 inst->alg.cra_blocksize = alg->cra_blocksize; crypto_ecb_alloc()
140 inst->alg.cra_alignmask = alg->cra_alignmask; crypto_ecb_alloc()
141 inst->alg.cra_type = &crypto_blkcipher_type; crypto_ecb_alloc()
143 inst->alg.cra_blkcipher.min_keysize = alg->cra_cipher.cia_min_keysize; crypto_ecb_alloc()
144 inst->alg.cra_blkcipher.max_keysize = alg->cra_cipher.cia_max_keysize; crypto_ecb_alloc()
146 inst->alg.cra_ctxsize = sizeof(struct crypto_ecb_ctx); crypto_ecb_alloc()
148 inst->alg.cra_init = crypto_ecb_init_tfm; crypto_ecb_alloc()
149 inst->alg.cra_exit = crypto_ecb_exit_tfm; crypto_ecb_alloc()
151 inst->alg.cra_blkcipher.setkey = crypto_ecb_setkey; crypto_ecb_alloc()
152 inst->alg.cra_blkcipher.encrypt = crypto_ecb_encrypt; crypto_ecb_alloc()
153 inst->alg.cra_blkcipher.decrypt = crypto_ecb_decrypt; crypto_ecb_alloc()
157 return inst; crypto_ecb_alloc()
160 static void crypto_ecb_free(struct crypto_instance *inst) crypto_ecb_free() argument
162 crypto_drop_spawn(crypto_instance_ctx(inst)); crypto_ecb_free()
163 kfree(inst); crypto_ecb_free()
H A Dcryptd.c166 struct crypto_instance *inst = crypto_tfm_alg_instance(tfm); cryptd_get_queue() local
167 struct cryptd_instance_ctx *ictx = crypto_instance_ctx(inst); cryptd_get_queue()
275 struct crypto_instance *inst = crypto_tfm_alg_instance(tfm); cryptd_blkcipher_init_tfm() local
276 struct cryptd_instance_ctx *ictx = crypto_instance_ctx(inst); cryptd_blkcipher_init_tfm()
302 struct crypto_instance *inst; cryptd_alloc_instance() local
305 p = kzalloc(head + sizeof(*inst) + tail, GFP_KERNEL); cryptd_alloc_instance()
309 inst = (void *)(p + head); cryptd_alloc_instance()
312 if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, cryptd_alloc_instance()
316 memcpy(inst->alg.cra_name, alg->cra_name, CRYPTO_MAX_ALG_NAME); cryptd_alloc_instance()
318 inst->alg.cra_priority = alg->cra_priority + 50; cryptd_alloc_instance()
319 inst->alg.cra_blocksize = alg->cra_blocksize; cryptd_alloc_instance()
320 inst->alg.cra_alignmask = alg->cra_alignmask; cryptd_alloc_instance()
336 struct crypto_instance *inst; cryptd_create_blkcipher() local
348 inst = cryptd_alloc_instance(alg, 0, sizeof(*ctx)); cryptd_create_blkcipher()
349 err = PTR_ERR(inst); cryptd_create_blkcipher()
350 if (IS_ERR(inst)) cryptd_create_blkcipher()
353 ctx = crypto_instance_ctx(inst); cryptd_create_blkcipher()
356 err = crypto_init_spawn(&ctx->spawn, alg, inst, cryptd_create_blkcipher()
364 inst->alg.cra_flags = type; cryptd_create_blkcipher()
365 inst->alg.cra_type = &crypto_ablkcipher_type; cryptd_create_blkcipher()
367 inst->alg.cra_ablkcipher.ivsize = alg->cra_blkcipher.ivsize; cryptd_create_blkcipher()
368 inst->alg.cra_ablkcipher.min_keysize = alg->cra_blkcipher.min_keysize; cryptd_create_blkcipher()
369 inst->alg.cra_ablkcipher.max_keysize = alg->cra_blkcipher.max_keysize; cryptd_create_blkcipher()
371 inst->alg.cra_ablkcipher.geniv = alg->cra_blkcipher.geniv; cryptd_create_blkcipher()
373 inst->alg.cra_ctxsize = sizeof(struct cryptd_blkcipher_ctx); cryptd_create_blkcipher()
375 inst->alg.cra_init = cryptd_blkcipher_init_tfm; cryptd_create_blkcipher()
376 inst->alg.cra_exit = cryptd_blkcipher_exit_tfm; cryptd_create_blkcipher()
378 inst->alg.cra_ablkcipher.setkey = cryptd_blkcipher_setkey; cryptd_create_blkcipher()
379 inst->alg.cra_ablkcipher.encrypt = cryptd_blkcipher_encrypt_enqueue; cryptd_create_blkcipher()
380 inst->alg.cra_ablkcipher.decrypt = cryptd_blkcipher_decrypt_enqueue; cryptd_create_blkcipher()
382 err = crypto_register_instance(tmpl, inst); cryptd_create_blkcipher()
386 kfree(inst); cryptd_create_blkcipher()
396 struct crypto_instance *inst = crypto_tfm_alg_instance(tfm); cryptd_hash_init_tfm() local
397 struct hashd_instance_ctx *ictx = crypto_instance_ctx(inst); cryptd_hash_init_tfm()
597 struct ahash_instance *inst; cryptd_create_hash() local
611 inst = cryptd_alloc_instance(alg, ahash_instance_headroom(), cryptd_create_hash()
613 err = PTR_ERR(inst); cryptd_create_hash()
614 if (IS_ERR(inst)) cryptd_create_hash()
617 ctx = ahash_instance_ctx(inst); cryptd_create_hash()
621 ahash_crypto_instance(inst)); cryptd_create_hash()
628 inst->alg.halg.base.cra_flags = type; cryptd_create_hash()
630 inst->alg.halg.digestsize = salg->digestsize; cryptd_create_hash()
631 inst->alg.halg.base.cra_ctxsize = sizeof(struct cryptd_hash_ctx); cryptd_create_hash()
633 inst->alg.halg.base.cra_init = cryptd_hash_init_tfm; cryptd_create_hash()
634 inst->alg.halg.base.cra_exit = cryptd_hash_exit_tfm; cryptd_create_hash()
636 inst->alg.init = cryptd_hash_init_enqueue; cryptd_create_hash()
637 inst->alg.update = cryptd_hash_update_enqueue; cryptd_create_hash()
638 inst->alg.final = cryptd_hash_final_enqueue; cryptd_create_hash()
639 inst->alg.finup = cryptd_hash_finup_enqueue; cryptd_create_hash()
640 inst->alg.export = cryptd_hash_export; cryptd_create_hash()
641 inst->alg.import = cryptd_hash_import; cryptd_create_hash()
642 inst->alg.setkey = cryptd_hash_setkey; cryptd_create_hash()
643 inst->alg.digest = cryptd_hash_digest_enqueue; cryptd_create_hash()
645 err = ahash_register_instance(tmpl, inst); cryptd_create_hash()
649 kfree(inst); cryptd_create_hash()
720 struct crypto_instance *inst = crypto_tfm_alg_instance(tfm); cryptd_aead_init_tfm() local
721 struct aead_instance_ctx *ictx = crypto_instance_ctx(inst); cryptd_aead_init_tfm()
747 struct crypto_instance *inst; cryptd_create_aead() local
759 inst = cryptd_alloc_instance(alg, 0, sizeof(*ctx)); cryptd_create_aead()
760 err = PTR_ERR(inst); cryptd_create_aead()
761 if (IS_ERR(inst)) cryptd_create_aead()
764 ctx = crypto_instance_ctx(inst); cryptd_create_aead()
767 err = crypto_init_spawn(&ctx->aead_spawn.base, alg, inst, cryptd_create_aead()
775 inst->alg.cra_flags = type; cryptd_create_aead()
776 inst->alg.cra_type = alg->cra_type; cryptd_create_aead()
777 inst->alg.cra_ctxsize = sizeof(struct cryptd_aead_ctx); cryptd_create_aead()
778 inst->alg.cra_init = cryptd_aead_init_tfm; cryptd_create_aead()
779 inst->alg.cra_exit = cryptd_aead_exit_tfm; cryptd_create_aead()
780 inst->alg.cra_aead.setkey = alg->cra_aead.setkey; cryptd_create_aead()
781 inst->alg.cra_aead.setauthsize = alg->cra_aead.setauthsize; cryptd_create_aead()
782 inst->alg.cra_aead.geniv = alg->cra_aead.geniv; cryptd_create_aead()
783 inst->alg.cra_aead.ivsize = alg->cra_aead.ivsize; cryptd_create_aead()
784 inst->alg.cra_aead.maxauthsize = alg->cra_aead.maxauthsize; cryptd_create_aead()
785 inst->alg.cra_aead.encrypt = cryptd_aead_encrypt_enqueue; cryptd_create_aead()
786 inst->alg.cra_aead.decrypt = cryptd_aead_decrypt_enqueue; cryptd_create_aead()
787 inst->alg.cra_aead.givencrypt = alg->cra_aead.givencrypt; cryptd_create_aead()
788 inst->alg.cra_aead.givdecrypt = alg->cra_aead.givdecrypt; cryptd_create_aead()
790 err = crypto_register_instance(tmpl, inst); cryptd_create_aead()
794 kfree(inst); cryptd_create_aead()
823 static void cryptd_free(struct crypto_instance *inst) cryptd_free() argument
825 struct cryptd_instance_ctx *ctx = crypto_instance_ctx(inst); cryptd_free()
826 struct hashd_instance_ctx *hctx = crypto_instance_ctx(inst); cryptd_free()
827 struct aead_instance_ctx *aead_ctx = crypto_instance_ctx(inst); cryptd_free()
829 switch (inst->alg.cra_flags & CRYPTO_ALG_TYPE_MASK) { cryptd_free()
832 kfree(ahash_instance(inst)); cryptd_free()
836 kfree(inst); cryptd_free()
840 kfree(inst); cryptd_free()
H A Dcbc.c195 struct crypto_instance *inst = (void *)tfm->__crt_alg; crypto_cbc_init_tfm() local
196 struct crypto_spawn *spawn = crypto_instance_ctx(inst); crypto_cbc_init_tfm()
216 struct crypto_instance *inst; crypto_cbc_alloc() local
229 inst = ERR_PTR(-EINVAL); crypto_cbc_alloc()
233 inst = crypto_alloc_instance("cbc", alg); crypto_cbc_alloc()
234 if (IS_ERR(inst)) crypto_cbc_alloc()
237 inst->alg.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER; crypto_cbc_alloc()
238 inst->alg.cra_priority = alg->cra_priority; crypto_cbc_alloc()
239 inst->alg.cra_blocksize = alg->cra_blocksize; crypto_cbc_alloc()
240 inst->alg.cra_alignmask = alg->cra_alignmask; crypto_cbc_alloc()
241 inst->alg.cra_type = &crypto_blkcipher_type; crypto_cbc_alloc()
244 inst->alg.cra_alignmask |= __alignof__(u32) - 1; crypto_cbc_alloc()
246 inst->alg.cra_blkcipher.ivsize = alg->cra_blocksize; crypto_cbc_alloc()
247 inst->alg.cra_blkcipher.min_keysize = alg->cra_cipher.cia_min_keysize; crypto_cbc_alloc()
248 inst->alg.cra_blkcipher.max_keysize = alg->cra_cipher.cia_max_keysize; crypto_cbc_alloc()
250 inst->alg.cra_ctxsize = sizeof(struct crypto_cbc_ctx); crypto_cbc_alloc()
252 inst->alg.cra_init = crypto_cbc_init_tfm; crypto_cbc_alloc()
253 inst->alg.cra_exit = crypto_cbc_exit_tfm; crypto_cbc_alloc()
255 inst->alg.cra_blkcipher.setkey = crypto_cbc_setkey; crypto_cbc_alloc()
256 inst->alg.cra_blkcipher.encrypt = crypto_cbc_encrypt; crypto_cbc_alloc()
257 inst->alg.cra_blkcipher.decrypt = crypto_cbc_decrypt; crypto_cbc_alloc()
261 return inst; crypto_cbc_alloc()
264 static void crypto_cbc_free(struct crypto_instance *inst) crypto_cbc_free() argument
266 crypto_drop_spawn(crypto_instance_ctx(inst)); crypto_cbc_free()
267 kfree(inst); crypto_cbc_free()
H A Dccm.c434 struct crypto_instance *inst = (void *)tfm->__crt_alg; crypto_ccm_init_tfm() local
435 struct ccm_instance_ctx *ictx = crypto_instance_ctx(inst); crypto_ccm_init_tfm()
481 struct crypto_instance *inst; crypto_ccm_alloc_common() local
503 inst = kzalloc(sizeof(*inst) + sizeof(*ictx), GFP_KERNEL); crypto_ccm_alloc_common()
505 if (!inst) crypto_ccm_alloc_common()
508 ictx = crypto_instance_ctx(inst); crypto_ccm_alloc_common()
510 err = crypto_init_spawn(&ictx->cipher, cipher, inst, crypto_ccm_alloc_common()
515 crypto_set_skcipher_spawn(&ictx->ctr, inst); crypto_ccm_alloc_common()
534 if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, crypto_ccm_alloc_common()
539 memcpy(inst->alg.cra_name, full_name, CRYPTO_MAX_ALG_NAME); crypto_ccm_alloc_common()
541 inst->alg.cra_flags = CRYPTO_ALG_TYPE_AEAD; crypto_ccm_alloc_common()
542 inst->alg.cra_flags |= ctr->cra_flags & CRYPTO_ALG_ASYNC; crypto_ccm_alloc_common()
543 inst->alg.cra_priority = cipher->cra_priority + ctr->cra_priority; crypto_ccm_alloc_common()
544 inst->alg.cra_blocksize = 1; crypto_ccm_alloc_common()
545 inst->alg.cra_alignmask = cipher->cra_alignmask | ctr->cra_alignmask | crypto_ccm_alloc_common()
547 inst->alg.cra_type = &crypto_aead_type; crypto_ccm_alloc_common()
548 inst->alg.cra_aead.ivsize = 16; crypto_ccm_alloc_common()
549 inst->alg.cra_aead.maxauthsize = 16; crypto_ccm_alloc_common()
550 inst->alg.cra_ctxsize = sizeof(struct crypto_ccm_ctx); crypto_ccm_alloc_common()
551 inst->alg.cra_init = crypto_ccm_init_tfm; crypto_ccm_alloc_common()
552 inst->alg.cra_exit = crypto_ccm_exit_tfm; crypto_ccm_alloc_common()
553 inst->alg.cra_aead.setkey = crypto_ccm_setkey; crypto_ccm_alloc_common()
554 inst->alg.cra_aead.setauthsize = crypto_ccm_setauthsize; crypto_ccm_alloc_common()
555 inst->alg.cra_aead.encrypt = crypto_ccm_encrypt; crypto_ccm_alloc_common()
556 inst->alg.cra_aead.decrypt = crypto_ccm_decrypt; crypto_ccm_alloc_common()
560 return inst; crypto_ccm_alloc_common()
567 kfree(inst); crypto_ccm_alloc_common()
569 inst = ERR_PTR(err); crypto_ccm_alloc_common()
594 static void crypto_ccm_free(struct crypto_instance *inst) crypto_ccm_free() argument
596 struct ccm_instance_ctx *ctx = crypto_instance_ctx(inst); crypto_ccm_free()
600 kfree(inst); crypto_ccm_free()
718 struct crypto_instance *inst = (void *)tfm->__crt_alg; crypto_rfc4309_init_tfm() local
719 struct crypto_aead_spawn *spawn = crypto_instance_ctx(inst); crypto_rfc4309_init_tfm()
750 struct crypto_instance *inst; crypto_rfc4309_alloc() local
767 inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL); crypto_rfc4309_alloc()
768 if (!inst) crypto_rfc4309_alloc()
771 spawn = crypto_instance_ctx(inst); crypto_rfc4309_alloc()
772 crypto_set_aead_spawn(spawn, inst); crypto_rfc4309_alloc()
791 if (snprintf(inst->alg.cra_name, CRYPTO_MAX_ALG_NAME, crypto_rfc4309_alloc()
793 snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, crypto_rfc4309_alloc()
798 inst->alg.cra_flags = CRYPTO_ALG_TYPE_AEAD; crypto_rfc4309_alloc()
799 inst->alg.cra_flags |= alg->cra_flags & CRYPTO_ALG_ASYNC; crypto_rfc4309_alloc()
800 inst->alg.cra_priority = alg->cra_priority; crypto_rfc4309_alloc()
801 inst->alg.cra_blocksize = 1; crypto_rfc4309_alloc()
802 inst->alg.cra_alignmask = alg->cra_alignmask; crypto_rfc4309_alloc()
803 inst->alg.cra_type = &crypto_nivaead_type; crypto_rfc4309_alloc()
805 inst->alg.cra_aead.ivsize = 8; crypto_rfc4309_alloc()
806 inst->alg.cra_aead.maxauthsize = 16; crypto_rfc4309_alloc()
808 inst->alg.cra_ctxsize = sizeof(struct crypto_rfc4309_ctx); crypto_rfc4309_alloc()
810 inst->alg.cra_init = crypto_rfc4309_init_tfm; crypto_rfc4309_alloc()
811 inst->alg.cra_exit = crypto_rfc4309_exit_tfm; crypto_rfc4309_alloc()
813 inst->alg.cra_aead.setkey = crypto_rfc4309_setkey; crypto_rfc4309_alloc()
814 inst->alg.cra_aead.setauthsize = crypto_rfc4309_setauthsize; crypto_rfc4309_alloc()
815 inst->alg.cra_aead.encrypt = crypto_rfc4309_encrypt; crypto_rfc4309_alloc()
816 inst->alg.cra_aead.decrypt = crypto_rfc4309_decrypt; crypto_rfc4309_alloc()
818 inst->alg.cra_aead.geniv = "seqiv"; crypto_rfc4309_alloc()
821 return inst; crypto_rfc4309_alloc()
826 kfree(inst); crypto_rfc4309_alloc()
827 inst = ERR_PTR(err); crypto_rfc4309_alloc()
831 static void crypto_rfc4309_free(struct crypto_instance *inst) crypto_rfc4309_free() argument
833 crypto_drop_spawn(crypto_instance_ctx(inst)); crypto_rfc4309_free()
834 kfree(inst); crypto_rfc4309_free()
H A Dhmac.c160 struct crypto_instance *inst = (void *)tfm->__crt_alg; hmac_init_tfm() local
161 struct crypto_shash_spawn *spawn = crypto_instance_ctx(inst); hmac_init_tfm()
183 struct shash_instance *inst; hmac_create() local
206 inst = shash_alloc_instance("hmac", alg); hmac_create()
207 err = PTR_ERR(inst); hmac_create()
208 if (IS_ERR(inst)) hmac_create()
211 err = crypto_init_shash_spawn(shash_instance_ctx(inst), salg, hmac_create()
212 shash_crypto_instance(inst)); hmac_create()
216 inst->alg.base.cra_priority = alg->cra_priority; hmac_create()
217 inst->alg.base.cra_blocksize = alg->cra_blocksize; hmac_create()
218 inst->alg.base.cra_alignmask = alg->cra_alignmask; hmac_create()
221 inst->alg.digestsize = ds; hmac_create()
222 inst->alg.statesize = ss; hmac_create()
224 inst->alg.base.cra_ctxsize = sizeof(struct hmac_ctx) + hmac_create()
227 inst->alg.base.cra_init = hmac_init_tfm; hmac_create()
228 inst->alg.base.cra_exit = hmac_exit_tfm; hmac_create()
230 inst->alg.init = hmac_init; hmac_create()
231 inst->alg.update = hmac_update; hmac_create()
232 inst->alg.final = hmac_final; hmac_create()
233 inst->alg.finup = hmac_finup; hmac_create()
234 inst->alg.export = hmac_export; hmac_create()
235 inst->alg.import = hmac_import; hmac_create()
236 inst->alg.setkey = hmac_setkey; hmac_create()
238 err = shash_register_instance(tmpl, inst); hmac_create()
241 shash_free_instance(shash_crypto_instance(inst)); hmac_create()
H A Dlrw.c299 struct crypto_instance *inst = (void *)tfm->__crt_alg; init_tfm() local
300 struct crypto_spawn *spawn = crypto_instance_ctx(inst); init_tfm()
328 struct crypto_instance *inst; alloc() local
341 inst = crypto_alloc_instance("lrw", alg); alloc()
342 if (IS_ERR(inst)) alloc()
345 inst->alg.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER; alloc()
346 inst->alg.cra_priority = alg->cra_priority; alloc()
347 inst->alg.cra_blocksize = alg->cra_blocksize; alloc()
349 if (alg->cra_alignmask < 7) inst->alg.cra_alignmask = 7; alloc()
350 else inst->alg.cra_alignmask = alg->cra_alignmask; alloc()
351 inst->alg.cra_type = &crypto_blkcipher_type; alloc()
354 inst->alg.cra_alignmask |= 3; alloc()
355 inst->alg.cra_blkcipher.ivsize = alg->cra_blocksize; alloc()
356 inst->alg.cra_blkcipher.min_keysize = alloc()
358 inst->alg.cra_blkcipher.max_keysize = alloc()
361 inst->alg.cra_ctxsize = sizeof(struct priv); alloc()
363 inst->alg.cra_init = init_tfm; alloc()
364 inst->alg.cra_exit = exit_tfm; alloc()
366 inst->alg.cra_blkcipher.setkey = setkey; alloc()
367 inst->alg.cra_blkcipher.encrypt = encrypt; alloc()
368 inst->alg.cra_blkcipher.decrypt = decrypt; alloc()
372 return inst; alloc()
375 static void free(struct crypto_instance *inst) free() argument
377 crypto_drop_spawn(crypto_instance_ctx(inst)); free()
378 kfree(inst); free()
H A Dgcm.c653 struct crypto_instance *inst = (void *)tfm->__crt_alg; crypto_gcm_init_tfm() local
654 struct gcm_instance_ctx *ictx = crypto_instance_ctx(inst); crypto_gcm_init_tfm()
703 struct crypto_instance *inst; crypto_gcm_alloc_common() local
724 inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL); crypto_gcm_alloc_common()
725 if (!inst) crypto_gcm_alloc_common()
728 ctx = crypto_instance_ctx(inst); crypto_gcm_alloc_common()
731 inst); crypto_gcm_alloc_common()
735 crypto_set_skcipher_spawn(&ctx->ctr, inst); crypto_gcm_alloc_common()
754 if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, crypto_gcm_alloc_common()
760 memcpy(inst->alg.cra_name, full_name, CRYPTO_MAX_ALG_NAME); crypto_gcm_alloc_common()
762 inst->alg.cra_flags = CRYPTO_ALG_TYPE_AEAD; crypto_gcm_alloc_common()
763 inst->alg.cra_flags |= ctr->cra_flags & CRYPTO_ALG_ASYNC; crypto_gcm_alloc_common()
764 inst->alg.cra_priority = ctr->cra_priority; crypto_gcm_alloc_common()
765 inst->alg.cra_blocksize = 1; crypto_gcm_alloc_common()
766 inst->alg.cra_alignmask = ctr->cra_alignmask | (__alignof__(u64) - 1); crypto_gcm_alloc_common()
767 inst->alg.cra_type = &crypto_aead_type; crypto_gcm_alloc_common()
768 inst->alg.cra_aead.ivsize = 16; crypto_gcm_alloc_common()
769 inst->alg.cra_aead.maxauthsize = 16; crypto_gcm_alloc_common()
770 inst->alg.cra_ctxsize = sizeof(struct crypto_gcm_ctx); crypto_gcm_alloc_common()
771 inst->alg.cra_init = crypto_gcm_init_tfm; crypto_gcm_alloc_common()
772 inst->alg.cra_exit = crypto_gcm_exit_tfm; crypto_gcm_alloc_common()
773 inst->alg.cra_aead.setkey = crypto_gcm_setkey; crypto_gcm_alloc_common()
774 inst->alg.cra_aead.setauthsize = crypto_gcm_setauthsize; crypto_gcm_alloc_common()
775 inst->alg.cra_aead.encrypt = crypto_gcm_encrypt; crypto_gcm_alloc_common()
776 inst->alg.cra_aead.decrypt = crypto_gcm_decrypt; crypto_gcm_alloc_common()
780 return inst; crypto_gcm_alloc_common()
787 kfree(inst); crypto_gcm_alloc_common()
789 inst = ERR_PTR(err); crypto_gcm_alloc_common()
814 static void crypto_gcm_free(struct crypto_instance *inst) crypto_gcm_free() argument
816 struct gcm_instance_ctx *ctx = crypto_instance_ctx(inst); crypto_gcm_free()
820 kfree(inst); crypto_gcm_free()
935 struct crypto_instance *inst = (void *)tfm->__crt_alg; crypto_rfc4106_init_tfm() local
936 struct crypto_aead_spawn *spawn = crypto_instance_ctx(inst); crypto_rfc4106_init_tfm()
967 struct crypto_instance *inst; crypto_rfc4106_alloc() local
984 inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL); crypto_rfc4106_alloc()
985 if (!inst) crypto_rfc4106_alloc()
988 spawn = crypto_instance_ctx(inst); crypto_rfc4106_alloc()
989 crypto_set_aead_spawn(spawn, inst); crypto_rfc4106_alloc()
1008 if (snprintf(inst->alg.cra_name, CRYPTO_MAX_ALG_NAME, crypto_rfc4106_alloc()
1010 snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, crypto_rfc4106_alloc()
1015 inst->alg.cra_flags = CRYPTO_ALG_TYPE_AEAD; crypto_rfc4106_alloc()
1016 inst->alg.cra_flags |= alg->cra_flags & CRYPTO_ALG_ASYNC; crypto_rfc4106_alloc()
1017 inst->alg.cra_priority = alg->cra_priority; crypto_rfc4106_alloc()
1018 inst->alg.cra_blocksize = 1; crypto_rfc4106_alloc()
1019 inst->alg.cra_alignmask = alg->cra_alignmask; crypto_rfc4106_alloc()
1020 inst->alg.cra_type = &crypto_nivaead_type; crypto_rfc4106_alloc()
1022 inst->alg.cra_aead.ivsize = 8; crypto_rfc4106_alloc()
1023 inst->alg.cra_aead.maxauthsize = 16; crypto_rfc4106_alloc()
1025 inst->alg.cra_ctxsize = sizeof(struct crypto_rfc4106_ctx); crypto_rfc4106_alloc()
1027 inst->alg.cra_init = crypto_rfc4106_init_tfm; crypto_rfc4106_alloc()
1028 inst->alg.cra_exit = crypto_rfc4106_exit_tfm; crypto_rfc4106_alloc()
1030 inst->alg.cra_aead.setkey = crypto_rfc4106_setkey; crypto_rfc4106_alloc()
1031 inst->alg.cra_aead.setauthsize = crypto_rfc4106_setauthsize; crypto_rfc4106_alloc()
1032 inst->alg.cra_aead.encrypt = crypto_rfc4106_encrypt; crypto_rfc4106_alloc()
1033 inst->alg.cra_aead.decrypt = crypto_rfc4106_decrypt; crypto_rfc4106_alloc()
1035 inst->alg.cra_aead.geniv = "seqiv"; crypto_rfc4106_alloc()
1038 return inst; crypto_rfc4106_alloc()
1043 kfree(inst); crypto_rfc4106_alloc()
1044 inst = ERR_PTR(err); crypto_rfc4106_alloc()
1048 static void crypto_rfc4106_free(struct crypto_instance *inst) crypto_rfc4106_free() argument
1050 crypto_drop_spawn(crypto_instance_ctx(inst)); crypto_rfc4106_free()
1051 kfree(inst); crypto_rfc4106_free()
1236 struct crypto_instance *inst = (void *)tfm->__crt_alg; crypto_rfc4543_init_tfm() local
1237 struct crypto_rfc4543_instance_ctx *ictx = crypto_instance_ctx(inst); crypto_rfc4543_init_tfm()
1282 struct crypto_instance *inst; crypto_rfc4543_alloc() local
1300 inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL); crypto_rfc4543_alloc()
1301 if (!inst) crypto_rfc4543_alloc()
1304 ctx = crypto_instance_ctx(inst); crypto_rfc4543_alloc()
1306 crypto_set_aead_spawn(spawn, inst); crypto_rfc4543_alloc()
1314 crypto_set_skcipher_spawn(&ctx->null, inst); crypto_rfc4543_alloc()
1333 if (snprintf(inst->alg.cra_name, CRYPTO_MAX_ALG_NAME, crypto_rfc4543_alloc()
1335 snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, crypto_rfc4543_alloc()
1340 inst->alg.cra_flags = CRYPTO_ALG_TYPE_AEAD; crypto_rfc4543_alloc()
1341 inst->alg.cra_flags |= alg->cra_flags & CRYPTO_ALG_ASYNC; crypto_rfc4543_alloc()
1342 inst->alg.cra_priority = alg->cra_priority; crypto_rfc4543_alloc()
1343 inst->alg.cra_blocksize = 1; crypto_rfc4543_alloc()
1344 inst->alg.cra_alignmask = alg->cra_alignmask; crypto_rfc4543_alloc()
1345 inst->alg.cra_type = &crypto_nivaead_type; crypto_rfc4543_alloc()
1347 inst->alg.cra_aead.ivsize = 8; crypto_rfc4543_alloc()
1348 inst->alg.cra_aead.maxauthsize = 16; crypto_rfc4543_alloc()
1350 inst->alg.cra_ctxsize = sizeof(struct crypto_rfc4543_ctx); crypto_rfc4543_alloc()
1352 inst->alg.cra_init = crypto_rfc4543_init_tfm; crypto_rfc4543_alloc()
1353 inst->alg.cra_exit = crypto_rfc4543_exit_tfm; crypto_rfc4543_alloc()
1355 inst->alg.cra_aead.setkey = crypto_rfc4543_setkey; crypto_rfc4543_alloc()
1356 inst->alg.cra_aead.setauthsize = crypto_rfc4543_setauthsize; crypto_rfc4543_alloc()
1357 inst->alg.cra_aead.encrypt = crypto_rfc4543_encrypt; crypto_rfc4543_alloc()
1358 inst->alg.cra_aead.decrypt = crypto_rfc4543_decrypt; crypto_rfc4543_alloc()
1360 inst->alg.cra_aead.geniv = "seqiv"; crypto_rfc4543_alloc()
1363 return inst; crypto_rfc4543_alloc()
1370 kfree(inst); crypto_rfc4543_alloc()
1371 inst = ERR_PTR(err); crypto_rfc4543_alloc()
1375 static void crypto_rfc4543_free(struct crypto_instance *inst) crypto_rfc4543_free() argument
1377 struct crypto_rfc4543_instance_ctx *ctx = crypto_instance_ctx(inst); crypto_rfc4543_free()
1382 kfree(inst); crypto_rfc4543_free()
H A Dpcbc.c205 struct crypto_instance *inst = (void *)tfm->__crt_alg; crypto_pcbc_init_tfm() local
206 struct crypto_spawn *spawn = crypto_instance_ctx(inst); crypto_pcbc_init_tfm()
226 struct crypto_instance *inst; crypto_pcbc_alloc() local
239 inst = crypto_alloc_instance("pcbc", alg); crypto_pcbc_alloc()
240 if (IS_ERR(inst)) crypto_pcbc_alloc()
243 inst->alg.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER; crypto_pcbc_alloc()
244 inst->alg.cra_priority = alg->cra_priority; crypto_pcbc_alloc()
245 inst->alg.cra_blocksize = alg->cra_blocksize; crypto_pcbc_alloc()
246 inst->alg.cra_alignmask = alg->cra_alignmask; crypto_pcbc_alloc()
247 inst->alg.cra_type = &crypto_blkcipher_type; crypto_pcbc_alloc()
250 inst->alg.cra_alignmask |= __alignof__(u32) - 1; crypto_pcbc_alloc()
252 inst->alg.cra_blkcipher.ivsize = alg->cra_blocksize; crypto_pcbc_alloc()
253 inst->alg.cra_blkcipher.min_keysize = alg->cra_cipher.cia_min_keysize; crypto_pcbc_alloc()
254 inst->alg.cra_blkcipher.max_keysize = alg->cra_cipher.cia_max_keysize; crypto_pcbc_alloc()
256 inst->alg.cra_ctxsize = sizeof(struct crypto_pcbc_ctx); crypto_pcbc_alloc()
258 inst->alg.cra_init = crypto_pcbc_init_tfm; crypto_pcbc_alloc()
259 inst->alg.cra_exit = crypto_pcbc_exit_tfm; crypto_pcbc_alloc()
261 inst->alg.cra_blkcipher.setkey = crypto_pcbc_setkey; crypto_pcbc_alloc()
262 inst->alg.cra_blkcipher.encrypt = crypto_pcbc_encrypt; crypto_pcbc_alloc()
263 inst->alg.cra_blkcipher.decrypt = crypto_pcbc_decrypt; crypto_pcbc_alloc()
267 return inst; crypto_pcbc_alloc()
270 static void crypto_pcbc_free(struct crypto_instance *inst) crypto_pcbc_free() argument
272 crypto_drop_spawn(crypto_instance_ctx(inst)); crypto_pcbc_free()
273 kfree(inst); crypto_pcbc_free()
H A Dxts.c244 struct crypto_instance *inst = (void *)tfm->__crt_alg; init_tfm() local
245 struct crypto_spawn *spawn = crypto_instance_ctx(inst); init_tfm()
289 struct crypto_instance *inst; alloc() local
302 inst = crypto_alloc_instance("xts", alg); alloc()
303 if (IS_ERR(inst)) alloc()
306 inst->alg.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER; alloc()
307 inst->alg.cra_priority = alg->cra_priority; alloc()
308 inst->alg.cra_blocksize = alg->cra_blocksize; alloc()
311 inst->alg.cra_alignmask = 7; alloc()
313 inst->alg.cra_alignmask = alg->cra_alignmask; alloc()
315 inst->alg.cra_type = &crypto_blkcipher_type; alloc()
317 inst->alg.cra_blkcipher.ivsize = alg->cra_blocksize; alloc()
318 inst->alg.cra_blkcipher.min_keysize = alloc()
320 inst->alg.cra_blkcipher.max_keysize = alloc()
323 inst->alg.cra_ctxsize = sizeof(struct priv); alloc()
325 inst->alg.cra_init = init_tfm; alloc()
326 inst->alg.cra_exit = exit_tfm; alloc()
328 inst->alg.cra_blkcipher.setkey = setkey; alloc()
329 inst->alg.cra_blkcipher.encrypt = encrypt; alloc()
330 inst->alg.cra_blkcipher.decrypt = decrypt; alloc()
334 return inst; alloc()
337 static void free(struct crypto_instance *inst) free() argument
339 crypto_drop_spawn(crypto_instance_ctx(inst)); free()
340 kfree(inst); free()
H A Dalgapi.c74 struct crypto_instance *inst = (void *)alg; crypto_destroy_instance() local
75 struct crypto_template *tmpl = inst->tmpl; crypto_destroy_instance()
77 tmpl->free(inst); crypto_destroy_instance()
97 list)->inst->alg; crypto_more_spawns()
101 return &n->list == stack ? top : &n->inst->alg.cra_users; crypto_more_spawns()
104 static void crypto_remove_instance(struct crypto_instance *inst, crypto_remove_instance() argument
107 struct crypto_template *tmpl = inst->tmpl; crypto_remove_instance()
109 if (crypto_is_dead(&inst->alg)) crypto_remove_instance()
112 inst->alg.cra_flags |= CRYPTO_ALG_DEAD; crypto_remove_instance()
113 if (hlist_unhashed(&inst->list)) crypto_remove_instance()
119 crypto_notify(CRYPTO_MSG_ALG_UNREGISTER, &inst->alg); crypto_remove_instance()
120 list_move(&inst->alg.cra_list, list); crypto_remove_instance()
121 hlist_del(&inst->list); crypto_remove_instance()
122 inst->alg.cra_destroy = crypto_destroy_instance; crypto_remove_instance()
124 BUG_ON(!list_empty(&inst->alg.cra_users)); crypto_remove_instance()
148 struct crypto_instance *inst; local
152 inst = spawn->inst;
154 BUG_ON(&inst->alg == alg);
158 if (&inst->alg == nalg)
162 spawns = &inst->alg.cra_users;
171 crypto_remove_instance(spawn->inst, list);
463 struct crypto_instance *inst; crypto_unregister_template() local
474 hlist_for_each_entry(inst, list, list) { hlist_for_each_entry()
475 int err = crypto_remove_alg(&inst->alg, &users); hlist_for_each_entry()
484 hlist_for_each_entry_safe(inst, n, list, list) { hlist_for_each_entry_safe()
485 BUG_ON(atomic_read(&inst->alg.cra_refcnt) != 1); hlist_for_each_entry_safe()
486 tmpl->free(inst); hlist_for_each_entry_safe()
519 struct crypto_instance *inst) crypto_register_instance()
524 err = crypto_check_alg(&inst->alg); crypto_register_instance()
528 inst->alg.cra_module = tmpl->module; crypto_register_instance()
529 inst->alg.cra_flags |= CRYPTO_ALG_INSTANCE; crypto_register_instance()
531 if (unlikely(!crypto_mod_get(&inst->alg))) crypto_register_instance()
536 larval = __crypto_register_alg(&inst->alg); crypto_register_instance()
540 hlist_add_head(&inst->list, &tmpl->instances); crypto_register_instance()
541 inst->tmpl = tmpl; crypto_register_instance()
553 if (!(inst->alg.cra_flags & CRYPTO_ALG_TESTED)) crypto_register_instance()
554 crypto_unregister_instance(inst); crypto_register_instance()
558 crypto_mod_put(&inst->alg); crypto_register_instance()
563 int crypto_unregister_instance(struct crypto_instance *inst) crypto_unregister_instance() argument
569 crypto_remove_spawns(&inst->alg, &list, NULL); crypto_unregister_instance()
570 crypto_remove_instance(inst, &list); crypto_unregister_instance()
581 struct crypto_instance *inst, u32 mask) crypto_init_spawn()
585 spawn->inst = inst; crypto_init_spawn()
601 struct crypto_instance *inst, crypto_init_spawn2()
610 err = crypto_init_spawn(spawn, alg, inst, frontend->maskset); crypto_init_spawn2()
794 struct crypto_instance *inst; crypto_alloc_instance2() local
798 p = kzalloc(head + sizeof(*inst) + sizeof(struct crypto_spawn), crypto_alloc_instance2()
803 inst = (void *)(p + head); crypto_alloc_instance2()
806 if (snprintf(inst->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s(%s)", name, crypto_alloc_instance2()
810 if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s(%s)", crypto_alloc_instance2()
825 struct crypto_instance *inst; crypto_alloc_instance() local
829 inst = crypto_alloc_instance2(name, alg, 0); crypto_alloc_instance()
830 if (IS_ERR(inst)) crypto_alloc_instance()
833 spawn = crypto_instance_ctx(inst); crypto_alloc_instance()
834 err = crypto_init_spawn(spawn, alg, inst, crypto_alloc_instance()
840 return inst; crypto_alloc_instance()
843 kfree(inst); crypto_alloc_instance()
844 inst = ERR_PTR(err); crypto_alloc_instance()
847 return inst; crypto_alloc_instance()
518 crypto_register_instance(struct crypto_template *tmpl, struct crypto_instance *inst) crypto_register_instance() argument
580 crypto_init_spawn(struct crypto_spawn *spawn, struct crypto_alg *alg, struct crypto_instance *inst, u32 mask) crypto_init_spawn() argument
600 crypto_init_spawn2(struct crypto_spawn *spawn, struct crypto_alg *alg, struct crypto_instance *inst, const struct crypto_type *frontend) crypto_init_spawn2() argument
H A Dcmac.c206 struct crypto_instance *inst = (void *)tfm->__crt_alg; cmac_init_tfm() local
207 struct crypto_spawn *spawn = crypto_instance_ctx(inst); cmac_init_tfm()
227 struct shash_instance *inst; cmac_create() local
249 inst = shash_alloc_instance("cmac", alg); cmac_create()
250 err = PTR_ERR(inst); cmac_create()
251 if (IS_ERR(inst)) cmac_create()
254 err = crypto_init_spawn(shash_instance_ctx(inst), alg, cmac_create()
255 shash_crypto_instance(inst), cmac_create()
261 inst->alg.base.cra_alignmask = alignmask; cmac_create()
262 inst->alg.base.cra_priority = alg->cra_priority; cmac_create()
263 inst->alg.base.cra_blocksize = alg->cra_blocksize; cmac_create()
265 inst->alg.digestsize = alg->cra_blocksize; cmac_create()
266 inst->alg.descsize = cmac_create()
271 inst->alg.base.cra_ctxsize = cmac_create()
275 inst->alg.base.cra_init = cmac_init_tfm; cmac_create()
276 inst->alg.base.cra_exit = cmac_exit_tfm; cmac_create()
278 inst->alg.init = crypto_cmac_digest_init; cmac_create()
279 inst->alg.update = crypto_cmac_digest_update; cmac_create()
280 inst->alg.final = crypto_cmac_digest_final; cmac_create()
281 inst->alg.setkey = crypto_cmac_digest_setkey; cmac_create()
283 err = shash_register_instance(tmpl, inst); cmac_create()
286 shash_free_instance(shash_crypto_instance(inst)); cmac_create()
H A Dxcbc.c180 struct crypto_instance *inst = (void *)tfm->__crt_alg; xcbc_init_tfm() local
181 struct crypto_spawn *spawn = crypto_instance_ctx(inst); xcbc_init_tfm()
201 struct shash_instance *inst; xcbc_create() local
222 inst = shash_alloc_instance("xcbc", alg); xcbc_create()
223 err = PTR_ERR(inst); xcbc_create()
224 if (IS_ERR(inst)) xcbc_create()
227 err = crypto_init_spawn(shash_instance_ctx(inst), alg, xcbc_create()
228 shash_crypto_instance(inst), xcbc_create()
234 inst->alg.base.cra_alignmask = alignmask; xcbc_create()
235 inst->alg.base.cra_priority = alg->cra_priority; xcbc_create()
236 inst->alg.base.cra_blocksize = alg->cra_blocksize; xcbc_create()
238 inst->alg.digestsize = alg->cra_blocksize; xcbc_create()
239 inst->alg.descsize = ALIGN(sizeof(struct xcbc_desc_ctx), xcbc_create()
245 inst->alg.base.cra_ctxsize = ALIGN(sizeof(struct xcbc_tfm_ctx), xcbc_create()
248 inst->alg.base.cra_init = xcbc_init_tfm; xcbc_create()
249 inst->alg.base.cra_exit = xcbc_exit_tfm; xcbc_create()
251 inst->alg.init = crypto_xcbc_digest_init; xcbc_create()
252 inst->alg.update = crypto_xcbc_digest_update; xcbc_create()
253 inst->alg.final = crypto_xcbc_digest_final; xcbc_create()
254 inst->alg.setkey = crypto_xcbc_digest_setkey; xcbc_create()
256 err = shash_register_instance(tmpl, inst); xcbc_create()
259 shash_free_instance(shash_crypto_instance(inst)); xcbc_create()
H A Daead.c267 err = crypto_init_spawn(&spawn->base, alg, spawn->base.inst, mask); crypto_grab_nivaead()
279 struct crypto_instance *inst; aead_geniv_alloc() local
295 inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL); aead_geniv_alloc()
296 if (!inst) aead_geniv_alloc()
299 spawn = crypto_instance_ctx(inst); aead_geniv_alloc()
304 crypto_set_aead_spawn(spawn, inst); aead_geniv_alloc()
324 memcpy(inst->alg.cra_name, alg->cra_name, CRYPTO_MAX_ALG_NAME); aead_geniv_alloc()
325 memcpy(inst->alg.cra_driver_name, alg->cra_driver_name, aead_geniv_alloc()
329 if (snprintf(inst->alg.cra_name, CRYPTO_MAX_ALG_NAME, aead_geniv_alloc()
333 if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, aead_geniv_alloc()
339 inst->alg.cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_GENIV; aead_geniv_alloc()
340 inst->alg.cra_flags |= alg->cra_flags & CRYPTO_ALG_ASYNC; aead_geniv_alloc()
341 inst->alg.cra_priority = alg->cra_priority; aead_geniv_alloc()
342 inst->alg.cra_blocksize = alg->cra_blocksize; aead_geniv_alloc()
343 inst->alg.cra_alignmask = alg->cra_alignmask; aead_geniv_alloc()
344 inst->alg.cra_type = &crypto_aead_type; aead_geniv_alloc()
346 inst->alg.cra_aead.ivsize = alg->cra_aead.ivsize; aead_geniv_alloc()
347 inst->alg.cra_aead.maxauthsize = alg->cra_aead.maxauthsize; aead_geniv_alloc()
348 inst->alg.cra_aead.geniv = alg->cra_aead.geniv; aead_geniv_alloc()
350 inst->alg.cra_aead.setkey = alg->cra_aead.setkey; aead_geniv_alloc()
351 inst->alg.cra_aead.setauthsize = alg->cra_aead.setauthsize; aead_geniv_alloc()
352 inst->alg.cra_aead.encrypt = alg->cra_aead.encrypt; aead_geniv_alloc()
353 inst->alg.cra_aead.decrypt = alg->cra_aead.decrypt; aead_geniv_alloc()
356 return inst; aead_geniv_alloc()
361 kfree(inst); aead_geniv_alloc()
362 inst = ERR_PTR(err); aead_geniv_alloc()
367 void aead_geniv_free(struct crypto_instance *inst) aead_geniv_free() argument
369 crypto_drop_aead(crypto_instance_ctx(inst)); aead_geniv_free()
370 kfree(inst); aead_geniv_free()
376 struct crypto_instance *inst = (void *)tfm->__crt_alg; aead_geniv_init() local
379 aead = crypto_spawn_aead(crypto_instance_ctx(inst)); aead_geniv_init()
408 struct crypto_instance *inst; crypto_nivaead_default() local
446 inst = tmpl->alloc(tb); crypto_nivaead_default()
447 err = PTR_ERR(inst); crypto_nivaead_default()
448 if (IS_ERR(inst)) crypto_nivaead_default()
451 err = crypto_register_instance(tmpl, inst); crypto_nivaead_default()
453 tmpl->free(inst); crypto_nivaead_default()
520 err = crypto_init_spawn(&spawn->base, alg, spawn->base.inst, mask); crypto_grab_aead()
H A Dmcryptd.c222 struct crypto_instance *inst = crypto_tfm_alg_instance(tfm); mcryptd_get_queue() local
223 struct mcryptd_instance_ctx *ictx = crypto_instance_ctx(inst); mcryptd_get_queue()
232 struct crypto_instance *inst; mcryptd_alloc_instance() local
235 p = kzalloc(head + sizeof(*inst) + tail, GFP_KERNEL); mcryptd_alloc_instance()
239 inst = (void *)(p + head); mcryptd_alloc_instance()
242 if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, mcryptd_alloc_instance()
246 memcpy(inst->alg.cra_name, alg->cra_name, CRYPTO_MAX_ALG_NAME); mcryptd_alloc_instance()
248 inst->alg.cra_priority = alg->cra_priority + 50; mcryptd_alloc_instance()
249 inst->alg.cra_blocksize = alg->cra_blocksize; mcryptd_alloc_instance()
250 inst->alg.cra_alignmask = alg->cra_alignmask; mcryptd_alloc_instance()
277 struct crypto_instance *inst = crypto_tfm_alg_instance(tfm); mcryptd_hash_init_tfm() local
278 struct hashd_instance_ctx *ictx = crypto_instance_ctx(inst); mcryptd_hash_init_tfm()
494 struct ahash_instance *inst; mcryptd_create_hash() local
509 inst = mcryptd_alloc_instance(alg, ahash_instance_headroom(), mcryptd_create_hash()
511 err = PTR_ERR(inst); mcryptd_create_hash()
512 if (IS_ERR(inst)) mcryptd_create_hash()
515 ctx = ahash_instance_ctx(inst); mcryptd_create_hash()
519 ahash_crypto_instance(inst)); mcryptd_create_hash()
526 inst->alg.halg.base.cra_flags = type; mcryptd_create_hash()
528 inst->alg.halg.digestsize = salg->digestsize; mcryptd_create_hash()
529 inst->alg.halg.base.cra_ctxsize = sizeof(struct mcryptd_hash_ctx); mcryptd_create_hash()
531 inst->alg.halg.base.cra_init = mcryptd_hash_init_tfm; mcryptd_create_hash()
532 inst->alg.halg.base.cra_exit = mcryptd_hash_exit_tfm; mcryptd_create_hash()
534 inst->alg.init = mcryptd_hash_init_enqueue; mcryptd_create_hash()
535 inst->alg.update = mcryptd_hash_update_enqueue; mcryptd_create_hash()
536 inst->alg.final = mcryptd_hash_final_enqueue; mcryptd_create_hash()
537 inst->alg.finup = mcryptd_hash_finup_enqueue; mcryptd_create_hash()
538 inst->alg.export = mcryptd_hash_export; mcryptd_create_hash()
539 inst->alg.import = mcryptd_hash_import; mcryptd_create_hash()
540 inst->alg.setkey = mcryptd_hash_setkey; mcryptd_create_hash()
541 inst->alg.digest = mcryptd_hash_digest_enqueue; mcryptd_create_hash()
543 err = ahash_register_instance(tmpl, inst); mcryptd_create_hash()
547 kfree(inst); mcryptd_create_hash()
574 static void mcryptd_free(struct crypto_instance *inst) mcryptd_free() argument
576 struct mcryptd_instance_ctx *ctx = crypto_instance_ctx(inst); mcryptd_free()
577 struct hashd_instance_ctx *hctx = crypto_instance_ctx(inst); mcryptd_free()
579 switch (inst->alg.cra_flags & CRYPTO_ALG_TYPE_MASK) { mcryptd_free()
582 kfree(ahash_instance(inst)); mcryptd_free()
586 kfree(inst); mcryptd_free()
H A Dpcrypt.c276 struct crypto_instance *inst = crypto_tfm_alg_instance(tfm); pcrypt_aead_init_tfm() local
277 struct pcrypt_instance_ctx *ictx = crypto_instance_ctx(inst); pcrypt_aead_init_tfm()
289 cipher = crypto_spawn_aead(crypto_instance_ctx(inst)); pcrypt_aead_init_tfm()
311 struct crypto_instance *inst; pcrypt_alloc_instance() local
315 inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL); pcrypt_alloc_instance()
316 if (!inst) { pcrypt_alloc_instance()
317 inst = ERR_PTR(-ENOMEM); pcrypt_alloc_instance()
322 if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, pcrypt_alloc_instance()
326 memcpy(inst->alg.cra_name, alg->cra_name, CRYPTO_MAX_ALG_NAME); pcrypt_alloc_instance()
328 ctx = crypto_instance_ctx(inst); pcrypt_alloc_instance()
329 err = crypto_init_spawn(&ctx->spawn, alg, inst, pcrypt_alloc_instance()
334 inst->alg.cra_priority = alg->cra_priority + 100; pcrypt_alloc_instance()
335 inst->alg.cra_blocksize = alg->cra_blocksize; pcrypt_alloc_instance()
336 inst->alg.cra_alignmask = alg->cra_alignmask; pcrypt_alloc_instance()
339 return inst; pcrypt_alloc_instance()
342 kfree(inst); pcrypt_alloc_instance()
343 inst = ERR_PTR(err); pcrypt_alloc_instance()
350 struct crypto_instance *inst; pcrypt_alloc_aead() local
357 inst = pcrypt_alloc_instance(alg); pcrypt_alloc_aead()
358 if (IS_ERR(inst)) pcrypt_alloc_aead()
361 inst->alg.cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC; pcrypt_alloc_aead()
362 inst->alg.cra_type = &crypto_aead_type; pcrypt_alloc_aead()
364 inst->alg.cra_aead.ivsize = alg->cra_aead.ivsize; pcrypt_alloc_aead()
365 inst->alg.cra_aead.geniv = alg->cra_aead.geniv; pcrypt_alloc_aead()
366 inst->alg.cra_aead.maxauthsize = alg->cra_aead.maxauthsize; pcrypt_alloc_aead()
368 inst->alg.cra_ctxsize = sizeof(struct pcrypt_aead_ctx); pcrypt_alloc_aead()
370 inst->alg.cra_init = pcrypt_aead_init_tfm; pcrypt_alloc_aead()
371 inst->alg.cra_exit = pcrypt_aead_exit_tfm; pcrypt_alloc_aead()
373 inst->alg.cra_aead.setkey = pcrypt_aead_setkey; pcrypt_alloc_aead()
374 inst->alg.cra_aead.setauthsize = pcrypt_aead_setauthsize; pcrypt_alloc_aead()
375 inst->alg.cra_aead.encrypt = pcrypt_aead_encrypt; pcrypt_alloc_aead()
376 inst->alg.cra_aead.decrypt = pcrypt_aead_decrypt; pcrypt_alloc_aead()
377 inst->alg.cra_aead.givencrypt = pcrypt_aead_givencrypt; pcrypt_alloc_aead()
381 return inst; pcrypt_alloc_aead()
400 static void pcrypt_free(struct crypto_instance *inst) pcrypt_free() argument
402 struct pcrypt_instance_ctx *ctx = crypto_instance_ctx(inst); pcrypt_free()
405 kfree(inst); pcrypt_free()
H A Dcts.c255 struct crypto_instance *inst = (void *)tfm->__crt_alg; crypto_cts_init_tfm() local
256 struct crypto_spawn *spawn = crypto_instance_ctx(inst); crypto_cts_init_tfm()
276 struct crypto_instance *inst; crypto_cts_alloc() local
289 inst = ERR_PTR(-EINVAL); crypto_cts_alloc()
296 inst = crypto_alloc_instance("cts", alg); crypto_cts_alloc()
297 if (IS_ERR(inst)) crypto_cts_alloc()
300 inst->alg.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER; crypto_cts_alloc()
301 inst->alg.cra_priority = alg->cra_priority; crypto_cts_alloc()
302 inst->alg.cra_blocksize = alg->cra_blocksize; crypto_cts_alloc()
303 inst->alg.cra_alignmask = alg->cra_alignmask; crypto_cts_alloc()
304 inst->alg.cra_type = &crypto_blkcipher_type; crypto_cts_alloc()
307 inst->alg.cra_alignmask |= __alignof__(u32) - 1; crypto_cts_alloc()
309 inst->alg.cra_blkcipher.ivsize = alg->cra_blocksize; crypto_cts_alloc()
310 inst->alg.cra_blkcipher.min_keysize = alg->cra_blkcipher.min_keysize; crypto_cts_alloc()
311 inst->alg.cra_blkcipher.max_keysize = alg->cra_blkcipher.max_keysize; crypto_cts_alloc()
313 inst->alg.cra_ctxsize = sizeof(struct crypto_cts_ctx); crypto_cts_alloc()
315 inst->alg.cra_init = crypto_cts_init_tfm; crypto_cts_alloc()
316 inst->alg.cra_exit = crypto_cts_exit_tfm; crypto_cts_alloc()
318 inst->alg.cra_blkcipher.setkey = crypto_cts_setkey; crypto_cts_alloc()
319 inst->alg.cra_blkcipher.encrypt = crypto_cts_encrypt; crypto_cts_alloc()
320 inst->alg.cra_blkcipher.decrypt = crypto_cts_decrypt; crypto_cts_alloc()
324 return inst; crypto_cts_alloc()
327 static void crypto_cts_free(struct crypto_instance *inst) crypto_cts_free() argument
329 crypto_drop_spawn(crypto_instance_ctx(inst)); crypto_cts_free()
330 kfree(inst); crypto_cts_free()
H A Dchainiv.c290 struct crypto_instance *inst; chainiv_alloc() local
301 inst = skcipher_geniv_alloc(&chainiv_tmpl, tb, 0, 0); chainiv_alloc()
302 if (IS_ERR(inst)) chainiv_alloc()
305 inst->alg.cra_ablkcipher.givencrypt = chainiv_givencrypt_first; chainiv_alloc()
307 inst->alg.cra_init = chainiv_init; chainiv_alloc()
308 inst->alg.cra_exit = skcipher_geniv_exit; chainiv_alloc()
310 inst->alg.cra_ctxsize = sizeof(struct chainiv_ctx); chainiv_alloc()
313 inst->alg.cra_flags |= CRYPTO_ALG_ASYNC; chainiv_alloc()
315 inst->alg.cra_ablkcipher.givencrypt = chainiv_alloc()
318 inst->alg.cra_init = async_chainiv_init; chainiv_alloc()
319 inst->alg.cra_exit = async_chainiv_exit; chainiv_alloc()
321 inst->alg.cra_ctxsize = sizeof(struct async_chainiv_ctx); chainiv_alloc()
324 inst->alg.cra_ctxsize += inst->alg.cra_ablkcipher.ivsize; chainiv_alloc()
327 return inst; chainiv_alloc()
334 static void chainiv_free(struct crypto_instance *inst) chainiv_free() argument
336 skcipher_geniv_free(inst); chainiv_free()
H A Deseqiv.c208 struct crypto_instance *inst; eseqiv_alloc() local
215 inst = skcipher_geniv_alloc(&eseqiv_tmpl, tb, 0, 0); eseqiv_alloc()
216 if (IS_ERR(inst)) eseqiv_alloc()
220 if (inst->alg.cra_ablkcipher.ivsize != inst->alg.cra_blocksize) eseqiv_alloc()
223 inst->alg.cra_ablkcipher.givencrypt = eseqiv_givencrypt_first; eseqiv_alloc()
225 inst->alg.cra_init = eseqiv_init; eseqiv_alloc()
226 inst->alg.cra_exit = skcipher_geniv_exit; eseqiv_alloc()
228 inst->alg.cra_ctxsize = sizeof(struct eseqiv_ctx); eseqiv_alloc()
229 inst->alg.cra_ctxsize += inst->alg.cra_ablkcipher.ivsize; eseqiv_alloc()
232 return inst; eseqiv_alloc()
235 skcipher_geniv_free(inst); eseqiv_alloc()
236 inst = ERR_PTR(err); eseqiv_alloc()
242 static void eseqiv_free(struct crypto_instance *inst) eseqiv_free() argument
244 skcipher_geniv_free(inst); eseqiv_free()
H A Dauthenc.c549 struct crypto_instance *inst = crypto_tfm_alg_instance(tfm); crypto_authenc_init_tfm() local
550 struct authenc_instance_ctx *ictx = crypto_instance_ctx(inst); crypto_authenc_init_tfm()
599 struct crypto_instance *inst; crypto_authenc_alloc() local
626 inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL); crypto_authenc_alloc()
628 if (!inst) crypto_authenc_alloc()
631 ctx = crypto_instance_ctx(inst); crypto_authenc_alloc()
633 err = crypto_init_ahash_spawn(&ctx->auth, auth, inst); crypto_authenc_alloc()
637 crypto_set_skcipher_spawn(&ctx->enc, inst); crypto_authenc_alloc()
647 if (snprintf(inst->alg.cra_name, CRYPTO_MAX_ALG_NAME, crypto_authenc_alloc()
652 if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, crypto_authenc_alloc()
657 inst->alg.cra_flags = CRYPTO_ALG_TYPE_AEAD; crypto_authenc_alloc()
658 inst->alg.cra_flags |= enc->cra_flags & CRYPTO_ALG_ASYNC; crypto_authenc_alloc()
659 inst->alg.cra_priority = enc->cra_priority * crypto_authenc_alloc()
661 inst->alg.cra_blocksize = enc->cra_blocksize; crypto_authenc_alloc()
662 inst->alg.cra_alignmask = auth_base->cra_alignmask | enc->cra_alignmask; crypto_authenc_alloc()
663 inst->alg.cra_type = &crypto_aead_type; crypto_authenc_alloc()
665 inst->alg.cra_aead.ivsize = enc->cra_ablkcipher.ivsize; crypto_authenc_alloc()
666 inst->alg.cra_aead.maxauthsize = auth->digestsize; crypto_authenc_alloc()
668 inst->alg.cra_ctxsize = sizeof(struct crypto_authenc_ctx); crypto_authenc_alloc()
670 inst->alg.cra_init = crypto_authenc_init_tfm; crypto_authenc_alloc()
671 inst->alg.cra_exit = crypto_authenc_exit_tfm; crypto_authenc_alloc()
673 inst->alg.cra_aead.setkey = crypto_authenc_setkey; crypto_authenc_alloc()
674 inst->alg.cra_aead.encrypt = crypto_authenc_encrypt; crypto_authenc_alloc()
675 inst->alg.cra_aead.decrypt = crypto_authenc_decrypt; crypto_authenc_alloc()
676 inst->alg.cra_aead.givencrypt = crypto_authenc_givencrypt; crypto_authenc_alloc()
680 return inst; crypto_authenc_alloc()
687 kfree(inst); crypto_authenc_alloc()
689 inst = ERR_PTR(err); crypto_authenc_alloc()
693 static void crypto_authenc_free(struct crypto_instance *inst) crypto_authenc_free() argument
695 struct authenc_instance_ctx *ctx = crypto_instance_ctx(inst); crypto_authenc_free()
699 kfree(inst); crypto_authenc_free()
H A Dauthencesn.c641 struct crypto_instance *inst = crypto_tfm_alg_instance(tfm); crypto_authenc_esn_init_tfm() local
642 struct authenc_esn_instance_ctx *ictx = crypto_instance_ctx(inst); crypto_authenc_esn_init_tfm()
691 struct crypto_instance *inst; crypto_authenc_esn_alloc() local
718 inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL); crypto_authenc_esn_alloc()
720 if (!inst) crypto_authenc_esn_alloc()
723 ctx = crypto_instance_ctx(inst); crypto_authenc_esn_alloc()
725 err = crypto_init_ahash_spawn(&ctx->auth, auth, inst); crypto_authenc_esn_alloc()
729 crypto_set_skcipher_spawn(&ctx->enc, inst); crypto_authenc_esn_alloc()
739 if (snprintf(inst->alg.cra_name, CRYPTO_MAX_ALG_NAME, crypto_authenc_esn_alloc()
744 if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, crypto_authenc_esn_alloc()
749 inst->alg.cra_flags = CRYPTO_ALG_TYPE_AEAD; crypto_authenc_esn_alloc()
750 inst->alg.cra_flags |= enc->cra_flags & CRYPTO_ALG_ASYNC; crypto_authenc_esn_alloc()
751 inst->alg.cra_priority = enc->cra_priority * crypto_authenc_esn_alloc()
753 inst->alg.cra_blocksize = enc->cra_blocksize; crypto_authenc_esn_alloc()
754 inst->alg.cra_alignmask = auth_base->cra_alignmask | enc->cra_alignmask; crypto_authenc_esn_alloc()
755 inst->alg.cra_type = &crypto_aead_type; crypto_authenc_esn_alloc()
757 inst->alg.cra_aead.ivsize = enc->cra_ablkcipher.ivsize; crypto_authenc_esn_alloc()
758 inst->alg.cra_aead.maxauthsize = auth->digestsize; crypto_authenc_esn_alloc()
760 inst->alg.cra_ctxsize = sizeof(struct crypto_authenc_esn_ctx); crypto_authenc_esn_alloc()
762 inst->alg.cra_init = crypto_authenc_esn_init_tfm; crypto_authenc_esn_alloc()
763 inst->alg.cra_exit = crypto_authenc_esn_exit_tfm; crypto_authenc_esn_alloc()
765 inst->alg.cra_aead.setkey = crypto_authenc_esn_setkey; crypto_authenc_esn_alloc()
766 inst->alg.cra_aead.encrypt = crypto_authenc_esn_encrypt; crypto_authenc_esn_alloc()
767 inst->alg.cra_aead.decrypt = crypto_authenc_esn_decrypt; crypto_authenc_esn_alloc()
768 inst->alg.cra_aead.givencrypt = crypto_authenc_esn_givencrypt; crypto_authenc_esn_alloc()
772 return inst; crypto_authenc_esn_alloc()
779 kfree(inst); crypto_authenc_esn_alloc()
781 inst = ERR_PTR(err); crypto_authenc_esn_alloc()
785 static void crypto_authenc_esn_free(struct crypto_instance *inst) crypto_authenc_esn_free() argument
787 struct authenc_esn_instance_ctx *ctx = crypto_instance_ctx(inst); crypto_authenc_esn_free()
791 kfree(inst); crypto_authenc_esn_free()
H A Dblkcipher.c575 err = crypto_init_spawn(&spawn->base, alg, spawn->base.inst, mask); crypto_grab_nivcipher()
599 struct crypto_instance *inst; skcipher_geniv_alloc() local
615 inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL); skcipher_geniv_alloc()
616 if (!inst) skcipher_geniv_alloc()
619 spawn = crypto_instance_ctx(inst); skcipher_geniv_alloc()
624 crypto_set_skcipher_spawn(spawn, inst); skcipher_geniv_alloc()
670 memcpy(inst->alg.cra_name, alg->cra_name, CRYPTO_MAX_ALG_NAME); skcipher_geniv_alloc()
671 memcpy(inst->alg.cra_driver_name, alg->cra_driver_name, skcipher_geniv_alloc()
675 if (snprintf(inst->alg.cra_name, CRYPTO_MAX_ALG_NAME, skcipher_geniv_alloc()
679 if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, skcipher_geniv_alloc()
685 inst->alg.cra_flags = CRYPTO_ALG_TYPE_GIVCIPHER | CRYPTO_ALG_GENIV; skcipher_geniv_alloc()
686 inst->alg.cra_flags |= alg->cra_flags & CRYPTO_ALG_ASYNC; skcipher_geniv_alloc()
687 inst->alg.cra_priority = alg->cra_priority; skcipher_geniv_alloc()
688 inst->alg.cra_blocksize = alg->cra_blocksize; skcipher_geniv_alloc()
689 inst->alg.cra_alignmask = alg->cra_alignmask; skcipher_geniv_alloc()
690 inst->alg.cra_type = &crypto_givcipher_type; skcipher_geniv_alloc()
692 inst->alg.cra_ablkcipher.ivsize = balg.ivsize; skcipher_geniv_alloc()
693 inst->alg.cra_ablkcipher.min_keysize = balg.min_keysize; skcipher_geniv_alloc()
694 inst->alg.cra_ablkcipher.max_keysize = balg.max_keysize; skcipher_geniv_alloc()
695 inst->alg.cra_ablkcipher.geniv = balg.geniv; skcipher_geniv_alloc()
697 inst->alg.cra_ablkcipher.setkey = balg.setkey; skcipher_geniv_alloc()
698 inst->alg.cra_ablkcipher.encrypt = balg.encrypt; skcipher_geniv_alloc()
699 inst->alg.cra_ablkcipher.decrypt = balg.decrypt; skcipher_geniv_alloc()
702 return inst; skcipher_geniv_alloc()
707 kfree(inst); skcipher_geniv_alloc()
708 inst = ERR_PTR(err); skcipher_geniv_alloc()
713 void skcipher_geniv_free(struct crypto_instance *inst) skcipher_geniv_free() argument
715 crypto_drop_skcipher(crypto_instance_ctx(inst)); skcipher_geniv_free()
716 kfree(inst); skcipher_geniv_free()
722 struct crypto_instance *inst = (void *)tfm->__crt_alg; skcipher_geniv_init() local
725 cipher = crypto_spawn_skcipher(crypto_instance_ctx(inst)); skcipher_geniv_init()
H A Dvmac.c625 struct crypto_instance *inst = (void *)tfm->__crt_alg; vmac_init_tfm() local
626 struct crypto_spawn *spawn = crypto_instance_ctx(inst); vmac_init_tfm()
645 struct shash_instance *inst; vmac_create() local
658 inst = shash_alloc_instance("vmac", alg); vmac_create()
659 err = PTR_ERR(inst); vmac_create()
660 if (IS_ERR(inst)) vmac_create()
663 err = crypto_init_spawn(shash_instance_ctx(inst), alg, vmac_create()
664 shash_crypto_instance(inst), vmac_create()
669 inst->alg.base.cra_priority = alg->cra_priority; vmac_create()
670 inst->alg.base.cra_blocksize = alg->cra_blocksize; vmac_create()
671 inst->alg.base.cra_alignmask = alg->cra_alignmask; vmac_create()
673 inst->alg.digestsize = sizeof(vmac_t); vmac_create()
674 inst->alg.base.cra_ctxsize = sizeof(struct vmac_ctx_t); vmac_create()
675 inst->alg.base.cra_init = vmac_init_tfm; vmac_create()
676 inst->alg.base.cra_exit = vmac_exit_tfm; vmac_create()
678 inst->alg.init = vmac_init; vmac_create()
679 inst->alg.update = vmac_update; vmac_create()
680 inst->alg.final = vmac_final; vmac_create()
681 inst->alg.setkey = vmac_setkey; vmac_create()
683 err = shash_register_instance(tmpl, inst); vmac_create()
686 shash_free_instance(shash_crypto_instance(inst)); vmac_create()
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/iop/asm/
H A Diop_version_defs_asm.h6 * file: ../../inst/io_proc/rtl/guinness/iop_version.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_scrc_out_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_scrc_out.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_fifo_in_extra_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_fifo_out_extra_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_scrc_in_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_scrc_in.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_trigger_grp_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_trigger_grp.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_crc_par_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_crc_par.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_fifo_in_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_fifo_in.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_mpu_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_mpu.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_sap_in_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_sap_in.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_timer_grp_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_timer_grp.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_dmc_in_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_dmc_in.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_dmc_out_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_dmc_out.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_fifo_out_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_fifo_out.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Diop_sap_out_defs_asm.h6 * file: ../../inst/io_proc/rtl/iop_sap_out.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
/linux-4.1.27/drivers/crypto/qat/qat_common/
H A Dqat_crypto.c61 void qat_crypto_put_instance(struct qat_crypto_instance *inst) qat_crypto_put_instance() argument
63 if (atomic_sub_return(1, &inst->refctr) == 0) qat_crypto_put_instance()
64 adf_dev_put(inst->accel_dev); qat_crypto_put_instance()
69 struct qat_crypto_instance *inst; qat_crypto_free_instances() local
74 inst = list_entry(list_ptr, struct qat_crypto_instance, list); qat_crypto_free_instances()
76 for (i = 0; i < atomic_read(&inst->refctr); i++) qat_crypto_free_instances()
77 qat_crypto_put_instance(inst); qat_crypto_free_instances()
79 if (inst->sym_tx) qat_crypto_free_instances()
80 adf_remove_ring(inst->sym_tx); qat_crypto_free_instances()
82 if (inst->sym_rx) qat_crypto_free_instances()
83 adf_remove_ring(inst->sym_rx); qat_crypto_free_instances()
85 if (inst->pke_tx) qat_crypto_free_instances()
86 adf_remove_ring(inst->pke_tx); qat_crypto_free_instances()
88 if (inst->pke_rx) qat_crypto_free_instances()
89 adf_remove_ring(inst->pke_rx); qat_crypto_free_instances()
91 if (inst->rnd_tx) qat_crypto_free_instances()
92 adf_remove_ring(inst->rnd_tx); qat_crypto_free_instances()
94 if (inst->rnd_rx) qat_crypto_free_instances()
95 adf_remove_ring(inst->rnd_rx); qat_crypto_free_instances()
98 kfree(inst); qat_crypto_free_instances()
126 struct qat_crypto_instance *inst; local
129 inst = list_entry(itr, struct qat_crypto_instance, list);
130 cur = atomic_read(&inst->refctr);
132 inst_best = inst;
155 struct qat_crypto_instance *inst; qat_crypto_create_instances() local
169 inst = kzalloc_node(sizeof(*inst), GFP_KERNEL, qat_crypto_create_instances()
171 if (!inst) qat_crypto_create_instances()
174 list_add_tail(&inst->list, &accel_dev->crypto_list); qat_crypto_create_instances()
175 inst->id = i; qat_crypto_create_instances()
176 atomic_set(&inst->refctr, 0); qat_crypto_create_instances()
177 inst->accel_dev = accel_dev; qat_crypto_create_instances()
202 msg_size, key, NULL, 0, &inst->sym_tx)) qat_crypto_create_instances()
207 msg_size, key, NULL, 0, &inst->rnd_tx)) qat_crypto_create_instances()
213 msg_size, key, NULL, 0, &inst->pke_tx)) qat_crypto_create_instances()
220 &inst->sym_rx)) qat_crypto_create_instances()
226 &inst->rnd_rx)) qat_crypto_create_instances()
232 &inst->pke_rx)) qat_crypto_create_instances()
H A Dqat_algs.c115 struct qat_crypto_instance *inst; member in struct:qat_alg_aead_ctx
128 struct qat_crypto_instance *inst; member in struct:qat_alg_ablkcipher_ctx
573 dev = &GET_DEV(ctx->inst->accel_dev); qat_alg_aead_setkey()
581 struct qat_crypto_instance *inst = qat_alg_aead_setkey() local
583 if (!inst) { qat_alg_aead_setkey()
588 dev = &GET_DEV(inst->accel_dev); qat_alg_aead_setkey()
589 ctx->inst = inst; qat_alg_aead_setkey()
624 static void qat_alg_free_bufl(struct qat_crypto_instance *inst, qat_alg_free_bufl() argument
627 struct device *dev = &GET_DEV(inst->accel_dev); qat_alg_free_bufl()
656 static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, qat_alg_sgl_to_bufl() argument
663 struct device *dev = &GET_DEV(inst->accel_dev); qat_alg_sgl_to_bufl()
678 dev_to_node(&GET_DEV(inst->accel_dev))); qat_alg_sgl_to_bufl()
734 dev_to_node(&GET_DEV(inst->accel_dev)));
802 struct qat_crypto_instance *inst = ctx->inst; qat_aead_alg_callback() local
807 qat_alg_free_bufl(inst, qat_req); qat_aead_alg_callback()
817 struct qat_crypto_instance *inst = ctx->inst; qat_ablkcipher_alg_callback() local
822 qat_alg_free_bufl(inst, qat_req); qat_ablkcipher_alg_callback()
849 ret = qat_alg_sgl_to_bufl(ctx->inst, areq->assoc, areq->src, areq->dst, qat_alg_aead_dec()
871 ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg); qat_alg_aead_dec()
875 qat_alg_free_bufl(ctx->inst, qat_req); qat_alg_aead_dec()
893 ret = qat_alg_sgl_to_bufl(ctx->inst, areq->assoc, areq->src, areq->dst, qat_alg_aead_enc_internal()
921 ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg); qat_alg_aead_enc_internal()
925 qat_alg_free_bufl(ctx->inst, qat_req); qat_alg_aead_enc_internal()
960 dev = &GET_DEV(ctx->inst->accel_dev); qat_alg_ablkcipher_setkey()
968 struct qat_crypto_instance *inst = qat_alg_ablkcipher_setkey() local
970 if (!inst) { qat_alg_ablkcipher_setkey()
975 dev = &GET_DEV(inst->accel_dev); qat_alg_ablkcipher_setkey()
976 ctx->inst = inst; qat_alg_ablkcipher_setkey()
1021 ret = qat_alg_sgl_to_bufl(ctx->inst, NULL, req->src, req->dst, qat_alg_ablkcipher_encrypt()
1039 ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg); qat_alg_ablkcipher_encrypt()
1043 qat_alg_free_bufl(ctx->inst, qat_req); qat_alg_ablkcipher_encrypt()
1059 ret = qat_alg_sgl_to_bufl(ctx->inst, NULL, req->src, req->dst, qat_alg_ablkcipher_decrypt()
1077 ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg); qat_alg_ablkcipher_decrypt()
1081 qat_alg_free_bufl(ctx->inst, qat_req); qat_alg_ablkcipher_decrypt()
1122 struct qat_crypto_instance *inst = ctx->inst; qat_alg_aead_exit() local
1128 if (!inst) qat_alg_aead_exit()
1131 dev = &GET_DEV(inst->accel_dev); qat_alg_aead_exit()
1142 qat_crypto_put_instance(inst); qat_alg_aead_exit()
1159 struct qat_crypto_instance *inst = ctx->inst; qat_alg_ablkcipher_exit() local
1162 if (!inst) qat_alg_ablkcipher_exit()
1165 dev = &GET_DEV(inst->accel_dev); qat_alg_ablkcipher_exit()
1180 qat_crypto_put_instance(inst); qat_alg_ablkcipher_exit()
/linux-4.1.27/drivers/phy/
H A Dphy-exynos4x12-usb2.c168 static void exynos4x12_isol(struct samsung_usb2_phy_instance *inst, bool on) exynos4x12_isol() argument
170 struct samsung_usb2_phy_driver *drv = inst->drv; exynos4x12_isol()
174 switch (inst->cfg->id) { exynos4x12_isol()
195 static void exynos4x12_setup_clk(struct samsung_usb2_phy_instance *inst) exynos4x12_setup_clk() argument
197 struct samsung_usb2_phy_driver *drv = inst->drv; exynos4x12_setup_clk()
211 static void exynos4x12_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on) exynos4x12_phy_pwr() argument
213 struct samsung_usb2_phy_driver *drv = inst->drv; exynos4x12_phy_pwr()
219 switch (inst->cfg->id) { exynos4x12_phy_pwr()
263 static void exynos4x12_power_on_int(struct samsung_usb2_phy_instance *inst) exynos4x12_power_on_int() argument
265 if (inst->int_cnt++ > 0) exynos4x12_power_on_int()
268 exynos4x12_setup_clk(inst); exynos4x12_power_on_int()
269 exynos4x12_isol(inst, 0); exynos4x12_power_on_int()
270 exynos4x12_phy_pwr(inst, 1); exynos4x12_power_on_int()
273 static int exynos4x12_power_on(struct samsung_usb2_phy_instance *inst) exynos4x12_power_on() argument
275 struct samsung_usb2_phy_driver *drv = inst->drv; exynos4x12_power_on()
277 if (inst->ext_cnt++ > 0) exynos4x12_power_on()
280 if (inst->cfg->id == EXYNOS4x12_HOST) { exynos4x12_power_on()
287 if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch) exynos4x12_power_on()
292 if (inst->cfg->id == EXYNOS4x12_HSIC0 || exynos4x12_power_on()
293 inst->cfg->id == EXYNOS4x12_HSIC1) { exynos4x12_power_on()
298 exynos4x12_power_on_int(inst); exynos4x12_power_on()
303 static void exynos4x12_power_off_int(struct samsung_usb2_phy_instance *inst) exynos4x12_power_off_int() argument
305 if (inst->int_cnt-- > 1) exynos4x12_power_off_int()
308 exynos4x12_isol(inst, 1); exynos4x12_power_off_int()
309 exynos4x12_phy_pwr(inst, 0); exynos4x12_power_off_int()
312 static int exynos4x12_power_off(struct samsung_usb2_phy_instance *inst) exynos4x12_power_off() argument
314 struct samsung_usb2_phy_driver *drv = inst->drv; exynos4x12_power_off()
316 if (inst->ext_cnt-- > 1) exynos4x12_power_off()
319 if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch) exynos4x12_power_off()
324 if (inst->cfg->id == EXYNOS4x12_HOST) exynos4x12_power_off()
327 if (inst->cfg->id == EXYNOS4x12_HSIC0 || exynos4x12_power_off()
328 inst->cfg->id == EXYNOS4x12_HSIC1) { exynos4x12_power_off()
333 exynos4x12_power_off_int(inst); exynos4x12_power_off()
H A Dphy-s5pv210-usb2.c92 static void s5pv210_isol(struct samsung_usb2_phy_instance *inst, bool on) s5pv210_isol() argument
94 struct samsung_usb2_phy_driver *drv = inst->drv; s5pv210_isol()
97 switch (inst->cfg->id) { s5pv210_isol()
112 static void s5pv210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on) s5pv210_phy_pwr() argument
114 struct samsung_usb2_phy_driver *drv = inst->drv; s5pv210_phy_pwr()
120 switch (inst->cfg->id) { s5pv210_phy_pwr()
152 static int s5pv210_power_on(struct samsung_usb2_phy_instance *inst) s5pv210_power_on() argument
154 s5pv210_isol(inst, 0); s5pv210_power_on()
155 s5pv210_phy_pwr(inst, 1); s5pv210_power_on()
160 static int s5pv210_power_off(struct samsung_usb2_phy_instance *inst) s5pv210_power_off() argument
162 s5pv210_phy_pwr(inst, 0); s5pv210_power_off()
163 s5pv210_isol(inst, 1); s5pv210_power_off()
H A Dphy-exynos4210-usb2.c127 static void exynos4210_isol(struct samsung_usb2_phy_instance *inst, bool on) exynos4210_isol() argument
129 struct samsung_usb2_phy_driver *drv = inst->drv; exynos4210_isol()
133 switch (inst->cfg->id) { exynos4210_isol()
149 static void exynos4210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on) exynos4210_phy_pwr() argument
151 struct samsung_usb2_phy_driver *drv = inst->drv; exynos4210_phy_pwr()
158 switch (inst->cfg->id) { exynos4210_phy_pwr()
210 static int exynos4210_power_on(struct samsung_usb2_phy_instance *inst) exynos4210_power_on() argument
213 exynos4210_phy_pwr(inst, 1); exynos4210_power_on()
214 exynos4210_isol(inst, 0); exynos4210_power_on()
219 static int exynos4210_power_off(struct samsung_usb2_phy_instance *inst) exynos4210_power_off() argument
221 exynos4210_isol(inst, 1); exynos4210_power_off()
222 exynos4210_phy_pwr(inst, 0); exynos4210_power_off()
H A Dphy-samsung-usb2.c24 struct samsung_usb2_phy_instance *inst = phy_get_drvdata(phy); samsung_usb2_phy_power_on() local
25 struct samsung_usb2_phy_driver *drv = inst->drv; samsung_usb2_phy_power_on()
29 inst->cfg->label); samsung_usb2_phy_power_on()
36 if (inst->cfg->power_on) { samsung_usb2_phy_power_on()
38 ret = inst->cfg->power_on(inst); samsung_usb2_phy_power_on()
56 struct samsung_usb2_phy_instance *inst = phy_get_drvdata(phy); samsung_usb2_phy_power_off() local
57 struct samsung_usb2_phy_driver *drv = inst->drv; samsung_usb2_phy_power_off()
61 inst->cfg->label); samsung_usb2_phy_power_off()
62 if (inst->cfg->power_off) { samsung_usb2_phy_power_off()
64 ret = inst->cfg->power_off(inst); samsung_usb2_phy_power_off()
H A Dphy-exynos5250-usb2.c178 static void exynos5250_isol(struct samsung_usb2_phy_instance *inst, bool on) exynos5250_isol() argument
180 struct samsung_usb2_phy_driver *drv = inst->drv; exynos5250_isol()
184 switch (inst->cfg->id) { exynos5250_isol()
200 static int exynos5250_power_on(struct samsung_usb2_phy_instance *inst) exynos5250_power_on() argument
202 struct samsung_usb2_phy_driver *drv = inst->drv; exynos5250_power_on()
209 switch (inst->cfg->id) { exynos5250_power_on()
321 exynos5250_isol(inst, 0); exynos5250_power_on()
326 static int exynos5250_power_off(struct samsung_usb2_phy_instance *inst) exynos5250_power_off() argument
328 struct samsung_usb2_phy_driver *drv = inst->drv; exynos5250_power_off()
333 exynos5250_isol(inst, 1); exynos5250_power_off()
335 switch (inst->cfg->id) { exynos5250_power_off()
H A Dphy-exynos5-usbdrd.c135 void (*phy_isol)(struct phy_usb_instance *inst, u32 on);
137 unsigned int (*set_refclk)(struct phy_usb_instance *inst);
187 struct exynos5_usbdrd_phy *to_usbdrd_phy(struct phy_usb_instance *inst) to_usbdrd_phy() argument
189 return container_of((inst), struct exynos5_usbdrd_phy, to_usbdrd_phy()
190 phys[(inst)->index]); to_usbdrd_phy()
230 static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst, exynos5_usbdrd_phy_isol() argument
235 if (!inst->reg_pmu) exynos5_usbdrd_phy_isol()
240 regmap_update_bits(inst->reg_pmu, inst->pmu_offset, exynos5_usbdrd_phy_isol()
250 exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst) exynos5_usbdrd_pipe3_set_refclk() argument
253 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); exynos5_usbdrd_pipe3_set_refclk()
296 exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst) exynos5_usbdrd_utmi_set_refclk() argument
299 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); exynos5_usbdrd_utmi_set_refclk()
358 struct phy_usb_instance *inst = phy_get_drvdata(phy); exynos5_usbdrd_phy_init() local
359 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); exynos5_usbdrd_phy_init()
388 inst->phy_cfg->phy_init(phy_drd); exynos5_usbdrd_phy_init()
391 reg = inst->phy_cfg->set_refclk(inst); exynos5_usbdrd_phy_init()
420 struct phy_usb_instance *inst = phy_get_drvdata(phy); exynos5_usbdrd_phy_exit() local
421 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); exynos5_usbdrd_phy_exit()
453 struct phy_usb_instance *inst = phy_get_drvdata(phy); exynos5_usbdrd_phy_power_on() local
454 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); exynos5_usbdrd_phy_power_on()
484 inst->phy_cfg->phy_isol(inst, 0); exynos5_usbdrd_phy_power_on()
505 struct phy_usb_instance *inst = phy_get_drvdata(phy); exynos5_usbdrd_phy_power_off() local
506 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); exynos5_usbdrd_phy_power_off()
511 inst->phy_cfg->phy_isol(inst, 1); exynos5_usbdrd_phy_power_off()
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/asm/
H A Dirq_nmi_defs_asm.h44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dstrcop_defs_asm.h6 * file: ../../inst/strcop/rtl/strcop_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dstrmux_defs_asm.h6 * file: ../../inst/strmux/rtl/guinness/strmux_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dcris_defs_asm.h6 * file: ../../inst/crisp/doc/cris.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Drt_trace_defs_asm.h6 * file: ../../inst/rt_trace/rtl/rt_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dconfig_defs_asm.h44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Data_defs_asm.h6 * file: ../../inst/ata/rtl/ata_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dbif_slave_defs_asm.h6 * file: ../../inst/bif/rtl/bif_slave_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dmmu_defs_asm.h6 * file: ../../inst/mmu/doc/mmu_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dtimer_defs_asm.h6 * file: ../../inst/timer/rtl/timer_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Ddma_defs_asm.h6 * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dmarb_defs_asm.h6 * file: ../../inst/memarb/rtl/guinness/marb_top.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
313 * file: ../../inst/memarb/rtl/guinness/marb_top.r
317 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
351 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
352 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
356 #define REG_ADDR_VECT( scope, inst, reg, index ) \
357 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
359 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
360 ((inst) + offs + (index) * stride)
H A Dbif_core_defs_asm.h6 * file: ../../inst/bif/rtl/bif_core_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dgio_defs_asm.h6 * file: ../../inst/gio/rtl/gio_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dintr_vect_defs_asm.h6 * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dser_defs_asm.h6 * file: ../../inst/ser/rtl/ser_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dbif_dma_defs_asm.h6 * file: ../../inst/bif/rtl/bif_dma_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Deth_defs_asm.h6 * file: ../../inst/eth/rtl/eth_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dsser_defs_asm.h6 * file: ../../inst/syncser/rtl/sser_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dcpu_vect.h2 from ../../inst/crisp/doc/cpu_vect.r
H A Dintr_vect.h2 from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/
H A Diop_version_defs_asm.h41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46 #define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
49 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
H A Diop_sap_in_defs_asm.h41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46 #define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
49 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
H A Diop_sap_out_defs_asm.h41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46 #define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
49 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
/linux-4.1.27/include/crypto/internal/
H A Dhash.h83 struct ahash_instance *inst);
84 void ahash_free_instance(struct crypto_instance *inst);
88 struct crypto_instance *inst);
102 struct shash_instance *inst);
103 void shash_free_instance(struct crypto_instance *inst);
107 struct crypto_instance *inst);
149 struct ahash_instance *inst) ahash_crypto_instance()
151 return container_of(&inst->alg.halg.base, struct crypto_instance, alg); ahash_crypto_instance()
155 struct crypto_instance *inst) ahash_instance()
157 return container_of(&inst->alg, struct ahash_instance, alg.halg.base); ahash_instance()
160 static inline void *ahash_instance_ctx(struct ahash_instance *inst) ahash_instance_ctx() argument
162 return crypto_instance_ctx(ahash_crypto_instance(inst)); ahash_instance_ctx()
206 struct shash_instance *inst) shash_crypto_instance()
208 return container_of(&inst->alg.base, struct crypto_instance, alg); shash_crypto_instance()
212 struct crypto_instance *inst) shash_instance()
214 return container_of(__crypto_shash_alg(&inst->alg), shash_instance()
218 static inline void *shash_instance_ctx(struct shash_instance *inst) shash_instance_ctx() argument
220 return crypto_instance_ctx(shash_crypto_instance(inst)); shash_instance_ctx()
148 ahash_crypto_instance( struct ahash_instance *inst) ahash_crypto_instance() argument
154 ahash_instance( struct crypto_instance *inst) ahash_instance() argument
205 shash_crypto_instance( struct shash_instance *inst) shash_crypto_instance() argument
211 shash_instance( struct crypto_instance *inst) shash_instance() argument
H A Daead.h29 struct crypto_aead_spawn *spawn, struct crypto_instance *inst) crypto_set_aead_spawn()
31 crypto_set_spawn(&spawn->base, inst); crypto_set_aead_spawn()
61 void aead_geniv_free(struct crypto_instance *inst);
28 crypto_set_aead_spawn( struct crypto_aead_spawn *spawn, struct crypto_instance *inst) crypto_set_aead_spawn() argument
H A Dskcipher.h29 struct crypto_skcipher_spawn *spawn, struct crypto_instance *inst) crypto_set_skcipher_spawn()
31 crypto_set_spawn(&spawn->base, inst); crypto_set_skcipher_spawn()
65 void skcipher_geniv_free(struct crypto_instance *inst);
28 crypto_set_skcipher_spawn( struct crypto_skcipher_spawn *spawn, struct crypto_instance *inst) crypto_set_skcipher_spawn() argument
/linux-4.1.27/arch/mips/kvm/
H A Ddyntrans.c31 int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc, kvm_mips_trans_cache_index() argument
52 int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc, kvm_mips_trans_cache_va() argument
59 base = (inst >> 21) & 0x1f; kvm_mips_trans_cache_va()
60 offset = inst & 0xffff; kvm_mips_trans_cache_va()
73 int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc, struct kvm_vcpu *vcpu) kvm_mips_trans_mfc0() argument
79 rt = (inst >> 16) & 0x1f; kvm_mips_trans_mfc0()
80 rd = (inst >> 11) & 0x1f; kvm_mips_trans_mfc0()
81 sel = inst & 0x7; kvm_mips_trans_mfc0()
115 int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc, struct kvm_vcpu *vcpu) kvm_mips_trans_mtc0() argument
121 rt = (inst >> 16) & 0x1f; kvm_mips_trans_mtc0()
122 rd = (inst >> 11) & 0x1f; kvm_mips_trans_mtc0()
123 sel = inst & 0x7; kvm_mips_trans_mtc0()
/linux-4.1.27/drivers/soc/ti/
H A Dknav_qmss_queue.c63 #define for_each_handle_rcu(qh, inst) \
64 list_for_each_entry_rcu(qh, &inst->handles, list)
66 #define for_each_instance(idx, inst, kdev) \
67 for (idx = 0, inst = kdev->instances; \
69 idx++, inst = knav_queue_idx_to_inst(kdev, idx))
74 * @inst: qmss queue instance like accumulator
76 void knav_queue_notify(struct knav_queue_inst *inst) knav_queue_notify() argument
80 if (!inst) knav_queue_notify()
84 for_each_handle_rcu(qh, inst) { for_each_handle_rcu()
98 struct knav_queue_inst *inst = _instdata; knav_queue_int_handler() local
100 knav_queue_notify(inst); knav_queue_int_handler()
105 struct knav_queue_inst *inst) knav_queue_setup_irq()
107 unsigned queue = inst->id - range->queue_base; knav_queue_setup_irq()
115 inst->irq_name, inst); knav_queue_setup_irq()
131 static void knav_queue_free_irq(struct knav_queue_inst *inst) knav_queue_free_irq() argument
133 struct knav_range_info *range = inst->range; knav_queue_free_irq()
134 unsigned queue = inst->id - inst->range->queue_base; knav_queue_free_irq()
140 free_irq(irq, inst); knav_queue_free_irq()
144 static inline bool knav_queue_is_busy(struct knav_queue_inst *inst) knav_queue_is_busy() argument
146 return !list_empty(&inst->handles); knav_queue_is_busy()
149 static inline bool knav_queue_is_reserved(struct knav_queue_inst *inst) knav_queue_is_reserved() argument
151 return inst->range->flags & RANGE_RESERVED; knav_queue_is_reserved()
154 static inline bool knav_queue_is_shared(struct knav_queue_inst *inst) knav_queue_is_shared() argument
159 for_each_handle_rcu(tmp, inst) { for_each_handle_rcu()
169 static inline bool knav_queue_match_type(struct knav_queue_inst *inst, knav_queue_match_type() argument
173 (inst->range->flags & RANGE_HAS_IRQ)) { knav_queue_match_type()
176 (inst->range->flags & RANGE_HAS_ACCUMULATOR)) { knav_queue_match_type()
179 !(inst->range->flags & knav_queue_match_type()
189 struct knav_queue_inst *inst; knav_queue_match_id_to_inst() local
192 for_each_instance(idx, inst, kdev) { for_each_instance()
193 if (inst->id == id) for_each_instance()
194 return inst; for_each_instance()
209 static struct knav_queue *__knav_queue_open(struct knav_queue_inst *inst, __knav_queue_open() argument
216 qh = devm_kzalloc(inst->kdev->dev, sizeof(*qh), GFP_KERNEL); __knav_queue_open()
221 qh->inst = inst; __knav_queue_open()
222 id = inst->id - inst->qmgr->start_queue; __knav_queue_open()
223 qh->reg_push = &inst->qmgr->reg_push[id]; __knav_queue_open()
224 qh->reg_pop = &inst->qmgr->reg_pop[id]; __knav_queue_open()
225 qh->reg_peek = &inst->qmgr->reg_peek[id]; __knav_queue_open()
228 if (!knav_queue_is_busy(inst)) { __knav_queue_open()
229 struct knav_range_info *range = inst->range; __knav_queue_open()
231 inst->name = kstrndup(name, KNAV_NAME_SIZE, GFP_KERNEL); __knav_queue_open()
233 ret = range->ops->open_queue(range, inst, flags); __knav_queue_open()
236 devm_kfree(inst->kdev->dev, qh); __knav_queue_open()
240 list_add_tail_rcu(&qh->list, &inst->handles); __knav_queue_open()
247 struct knav_queue_inst *inst; knav_queue_open_by_id() local
253 inst = knav_queue_find_by_id(id); knav_queue_open_by_id()
254 if (!inst) knav_queue_open_by_id()
258 if (!(flags & KNAV_QUEUE_SHARED) && knav_queue_is_busy(inst)) knav_queue_open_by_id()
263 (knav_queue_is_busy(inst) && !knav_queue_is_shared(inst))) knav_queue_open_by_id()
266 qh = __knav_queue_open(inst, name, flags); knav_queue_open_by_id()
277 struct knav_queue_inst *inst; knav_queue_open_by_type() local
283 for_each_instance(idx, inst, kdev) { for_each_instance()
284 if (knav_queue_is_reserved(inst)) for_each_instance()
286 if (!knav_queue_match_type(inst, type)) for_each_instance()
288 if (knav_queue_is_busy(inst)) for_each_instance()
290 qh = __knav_queue_open(inst, name, flags); for_each_instance()
299 static void knav_queue_set_notify(struct knav_queue_inst *inst, bool enabled) knav_queue_set_notify() argument
301 struct knav_range_info *range = inst->range; knav_queue_set_notify()
304 range->ops->set_notify(range, inst, enabled); knav_queue_set_notify()
309 struct knav_queue_inst *inst = qh->inst; knav_queue_enable_notifier() local
321 first = (atomic_inc_return(&inst->num_notifiers) == 1); knav_queue_enable_notifier()
323 knav_queue_set_notify(inst, true); knav_queue_enable_notifier()
330 struct knav_queue_inst *inst = qh->inst; knav_queue_disable_notifier() local
337 last = (atomic_dec_return(&inst->num_notifiers) == 0); knav_queue_disable_notifier()
339 knav_queue_set_notify(inst, false); knav_queue_disable_notifier()
352 if (!(qh->inst->range->flags & (RANGE_HAS_ACCUMULATOR | RANGE_HAS_IRQ))) knav_queue_set_notifier()
368 struct knav_queue_inst *inst, knav_gp_set_notify()
374 queue = inst->id - range->queue_base; knav_gp_set_notify()
384 struct knav_queue_inst *inst, unsigned flags) knav_gp_open_queue()
386 return knav_queue_setup_irq(range, inst); knav_gp_open_queue()
390 struct knav_queue_inst *inst) knav_gp_close_queue()
392 knav_queue_free_irq(inst); knav_gp_close_queue()
406 struct knav_queue_inst *inst = qh->inst; knav_queue_get_count() local
409 atomic_read(&inst->desc_count); knav_queue_get_count()
413 struct knav_queue_inst *inst) knav_queue_debug_show_instance()
415 struct knav_device *kdev = inst->kdev; knav_queue_debug_show_instance()
418 if (!knav_queue_is_busy(inst)) knav_queue_debug_show_instance()
422 kdev->base_id + inst->id, inst->name); for_each_handle_rcu()
423 for_each_handle_rcu(qh, inst) { for_each_handle_rcu()
442 struct knav_queue_inst *inst; knav_queue_debug_show() local
449 for_each_instance(idx, inst, kdev) knav_queue_debug_show()
450 knav_queue_debug_show_instance(s, inst); knav_queue_debug_show()
489 struct knav_queue_inst *inst = qh->inst; knav_queue_flush() local
490 unsigned id = inst->id - inst->qmgr->start_queue; knav_queue_flush()
492 atomic_set(&inst->desc_count, 0); knav_queue_flush()
493 writel_relaxed(0, &inst->qmgr->reg_push[id].ptr_size_thresh); knav_queue_flush()
538 struct knav_queue_inst *inst = qh->inst; knav_queue_close() local
547 if (!knav_queue_is_busy(inst)) { knav_queue_close()
548 struct knav_range_info *range = inst->range; knav_queue_close()
551 range->ops->close_queue(range, inst); knav_queue_close()
553 devm_kfree(inst->kdev->dev, qh); knav_queue_close()
574 ret = qh->inst->kdev->base_id + qh->inst->id; knav_queue_device_control()
641 struct knav_queue_inst *inst = qh->inst; knav_queue_pop() local
646 if (inst->descs) { knav_queue_pop()
647 if (unlikely(atomic_dec_return(&inst->desc_count) < 0)) { knav_queue_pop()
648 atomic_inc(&inst->desc_count); knav_queue_pop()
651 idx = atomic_inc_return(&inst->desc_head); knav_queue_pop()
653 val = inst->descs[idx]; knav_queue_pop()
1614 struct knav_queue_inst *inst, knav_queue_init_queue()
1618 inst->qmgr = knav_find_qmgr(id); knav_queue_init_queue()
1619 if (!inst->qmgr) knav_queue_init_queue()
1622 INIT_LIST_HEAD(&inst->handles); knav_queue_init_queue()
1623 inst->kdev = kdev; knav_queue_init_queue()
1624 inst->range = range; knav_queue_init_queue()
1625 inst->irq_num = -1; knav_queue_init_queue()
1626 inst->id = id; knav_queue_init_queue()
1628 inst->irq_name = kstrndup(irq_name, sizeof(irq_name), GFP_KERNEL); knav_queue_init_queue()
1631 return range->ops->init_queue(range, inst); knav_queue_init_queue()
104 knav_queue_setup_irq(struct knav_range_info *range, struct knav_queue_inst *inst) knav_queue_setup_irq() argument
367 knav_gp_set_notify(struct knav_range_info *range, struct knav_queue_inst *inst, bool enabled) knav_gp_set_notify() argument
383 knav_gp_open_queue(struct knav_range_info *range, struct knav_queue_inst *inst, unsigned flags) knav_gp_open_queue() argument
389 knav_gp_close_queue(struct knav_range_info *range, struct knav_queue_inst *inst) knav_gp_close_queue() argument
412 knav_queue_debug_show_instance(struct seq_file *s, struct knav_queue_inst *inst) knav_queue_debug_show_instance() argument
1612 knav_queue_init_queue(struct knav_device *kdev, struct knav_range_info *range, struct knav_queue_inst *inst, unsigned id) knav_queue_init_queue() argument
H A Dknav_qmss.h274 * @inst: qmss queue instace properties
284 struct knav_queue_inst *inst; member in struct:knav_queue
313 struct knav_queue_inst *inst);
315 struct knav_queue_inst *inst, unsigned flags);
317 struct knav_queue_inst *inst);
319 struct knav_queue_inst *inst, bool enabled);
384 extern void knav_queue_notify(struct knav_queue_inst *inst);
/linux-4.1.27/arch/powerpc/kvm/
H A Dtrace.h15 TP_PROTO(unsigned int inst, unsigned long _pc, unsigned int emulate),
16 TP_ARGS(inst, _pc, emulate),
19 __field( unsigned int, inst )
25 __entry->inst = inst;
30 TP_printk("inst %u pc 0x%lx emulate %u\n",
31 __entry->inst, __entry->pc, __entry->emulate)
H A Demulate.c214 u32 inst; kvmppc_emulate_instruction() local
222 emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst); kvmppc_emulate_instruction()
226 pr_debug("Emulating opcode %d / %d\n", get_op(inst), get_xop(inst)); kvmppc_emulate_instruction()
228 rs = get_rs(inst); kvmppc_emulate_instruction()
229 rt = get_rt(inst); kvmppc_emulate_instruction()
230 sprn = get_sprn(inst); kvmppc_emulate_instruction()
232 switch (get_op(inst)) { kvmppc_emulate_instruction()
245 switch (get_xop(inst)) { kvmppc_emulate_instruction()
282 if (inst == KVMPPC_INST_SW_BREAKPOINT) { kvmppc_emulate_instruction()
297 emulated = vcpu->kvm->arch.kvm_ops->emulate_op(run, vcpu, inst, kvmppc_emulate_instruction()
304 "(op %d xop %d)\n", inst, get_op(inst), get_xop(inst)); kvmppc_emulate_instruction()
309 trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated); kvmppc_emulate_instruction()
H A Dbook3s_paired_singles.c347 * Cuts out inst bits with ordering according to spec.
350 static inline u32 inst_get_field(u32 inst, int msb, int lsb) inst_get_field() argument
352 return kvmppc_get_field(inst, msb + 32, lsb + 32); inst_get_field()
355 bool kvmppc_inst_is_paired_single(struct kvm_vcpu *vcpu, u32 inst) kvmppc_inst_is_paired_single() argument
360 switch (get_op(inst)) { kvmppc_inst_is_paired_single()
376 switch (inst_get_field(inst, 21, 30)) { kvmppc_inst_is_paired_single()
394 switch (inst_get_field(inst, 25, 30)) { kvmppc_inst_is_paired_single()
400 switch (inst_get_field(inst, 26, 30)) { kvmppc_inst_is_paired_single()
422 switch (inst_get_field(inst, 21, 30)) { kvmppc_inst_is_paired_single()
430 switch (inst_get_field(inst, 26, 30)) { kvmppc_inst_is_paired_single()
440 switch (inst_get_field(inst, 21, 30)) { kvmppc_inst_is_paired_single()
462 switch (inst_get_field(inst, 26, 30)) { kvmppc_inst_is_paired_single()
473 switch (inst_get_field(inst, 21, 30)) { kvmppc_inst_is_paired_single()
491 static int get_d_signext(u32 inst) get_d_signext() argument
493 int d = inst & 0x8ff; get_d_signext()
634 u32 inst; kvmppc_emulate_paired_single() local
646 emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst); kvmppc_emulate_paired_single()
650 ax_rd = inst_get_field(inst, 6, 10); kvmppc_emulate_paired_single()
651 ax_ra = inst_get_field(inst, 11, 15); kvmppc_emulate_paired_single()
652 ax_rb = inst_get_field(inst, 16, 20); kvmppc_emulate_paired_single()
653 ax_rc = inst_get_field(inst, 21, 25); kvmppc_emulate_paired_single()
654 full_d = inst_get_field(inst, 16, 31); kvmppc_emulate_paired_single()
661 rcomp = (inst & 1) ? true : false; kvmppc_emulate_paired_single()
664 if (!kvmppc_inst_is_paired_single(vcpu, inst)) kvmppc_emulate_paired_single()
686 switch (get_op(inst)) { kvmppc_emulate_paired_single()
690 bool w = inst_get_field(inst, 16, 16) ? true : false; kvmppc_emulate_paired_single()
691 int i = inst_get_field(inst, 17, 19); kvmppc_emulate_paired_single()
693 addr += get_d_signext(inst); kvmppc_emulate_paired_single()
700 bool w = inst_get_field(inst, 16, 16) ? true : false; kvmppc_emulate_paired_single()
701 int i = inst_get_field(inst, 17, 19); kvmppc_emulate_paired_single()
703 addr += get_d_signext(inst); kvmppc_emulate_paired_single()
713 bool w = inst_get_field(inst, 16, 16) ? true : false; kvmppc_emulate_paired_single()
714 int i = inst_get_field(inst, 17, 19); kvmppc_emulate_paired_single()
716 addr += get_d_signext(inst); kvmppc_emulate_paired_single()
723 bool w = inst_get_field(inst, 16, 16) ? true : false; kvmppc_emulate_paired_single()
724 int i = inst_get_field(inst, 17, 19); kvmppc_emulate_paired_single()
726 addr += get_d_signext(inst); kvmppc_emulate_paired_single()
735 switch (inst_get_field(inst, 21, 30)) { kvmppc_emulate_paired_single()
743 bool w = inst_get_field(inst, 21, 21) ? true : false; kvmppc_emulate_paired_single()
744 int i = inst_get_field(inst, 22, 24); kvmppc_emulate_paired_single()
757 bool w = inst_get_field(inst, 21, 21) ? true : false; kvmppc_emulate_paired_single()
758 int i = inst_get_field(inst, 22, 24); kvmppc_emulate_paired_single()
830 switch (inst_get_field(inst, 25, 30)) { kvmppc_emulate_paired_single()
834 bool w = inst_get_field(inst, 21, 21) ? true : false; kvmppc_emulate_paired_single()
835 int i = inst_get_field(inst, 22, 24); kvmppc_emulate_paired_single()
844 bool w = inst_get_field(inst, 21, 21) ? true : false; kvmppc_emulate_paired_single()
845 int i = inst_get_field(inst, 22, 24); kvmppc_emulate_paired_single()
856 switch (inst_get_field(inst, 26, 30)) { kvmppc_emulate_paired_single()
1009 switch (inst_get_field(inst, 21, 30)) { kvmppc_emulate_paired_single()
1108 switch (inst_get_field(inst, 21, 30)) { kvmppc_emulate_paired_single()
1130 switch (inst_get_field(inst, 26, 30)) { kvmppc_emulate_paired_single()
1154 switch (inst_get_field(inst, 21, 30)) { kvmppc_emulate_paired_single()
1174 u32 cr_shift = inst_get_field(inst, 6, 8) * 4; kvmppc_emulate_paired_single()
1185 u32 cr_shift = inst_get_field(inst, 6, 8) * 4; kvmppc_emulate_paired_single()
1234 switch (inst_get_field(inst, 26, 30)) { kvmppc_emulate_paired_single()
H A Dbook3s_emulate.c90 unsigned int inst, int *advance) kvmppc_core_emulate_op_pr()
93 int rt = get_rt(inst); kvmppc_core_emulate_op_pr()
94 int rs = get_rs(inst); kvmppc_core_emulate_op_pr()
95 int ra = get_ra(inst); kvmppc_core_emulate_op_pr()
96 int rb = get_rb(inst); kvmppc_core_emulate_op_pr()
99 switch (get_op(inst)) { kvmppc_core_emulate_op_pr()
103 (inst == swab32(inst_sc))) { kvmppc_core_emulate_op_pr()
117 switch (get_xop(inst)) { kvmppc_core_emulate_op_pr()
131 switch (get_xop(inst)) { kvmppc_core_emulate_op_pr()
138 if (inst & 0x10000) { kvmppc_core_emulate_op_pr()
154 srnum = kvmppc_get_field(inst, 12 + 32, 15 + 32); kvmppc_core_emulate_op_pr()
176 (inst >> 16) & 0xf, kvmppc_core_emulate_op_pr()
187 bool large = (inst & 0x00200000) ? true : false; kvmppc_core_emulate_op_pr()
658 u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst) kvmppc_alignment_dsisr() argument
660 return make_dsisr(inst); kvmppc_alignment_dsisr()
663 ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst) kvmppc_alignment_dar() argument
672 ulong ra = get_ra(inst); kvmppc_alignment_dar()
673 ulong rb = get_rb(inst); kvmppc_alignment_dar()
675 switch (get_op(inst)) { kvmppc_alignment_dar()
682 dar += (s32)((s16)inst); kvmppc_alignment_dar()
690 printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst); kvmppc_alignment_dar()
89 kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, unsigned int inst, int *advance) kvmppc_core_emulate_op_pr() argument
H A De500_emulate.c88 unsigned int inst, int *advance) kvmppc_e500_emul_ehpriv()
92 switch (get_oc(inst)) { kvmppc_e500_emul_ehpriv()
117 unsigned int inst, int *advance) kvmppc_core_emulate_op_e500()
120 int ra = get_ra(inst); kvmppc_core_emulate_op_e500()
121 int rb = get_rb(inst); kvmppc_core_emulate_op_e500()
122 int rt = get_rt(inst); kvmppc_core_emulate_op_e500()
125 switch (get_op(inst)) { kvmppc_core_emulate_op_e500()
127 switch (get_xop(inst)) { kvmppc_core_emulate_op_e500()
169 emulated = kvmppc_e500_emul_ehpriv(run, vcpu, inst, kvmppc_core_emulate_op_e500()
184 emulated = kvmppc_booke_emulate_op(run, vcpu, inst, advance); kvmppc_core_emulate_op_e500()
87 kvmppc_e500_emul_ehpriv(struct kvm_run *run, struct kvm_vcpu *vcpu, unsigned int inst, int *advance) kvmppc_e500_emul_ehpriv() argument
116 kvmppc_core_emulate_op_e500(struct kvm_run *run, struct kvm_vcpu *vcpu, unsigned int inst, int *advance) kvmppc_core_emulate_op_e500() argument
H A Demulate_loadstore.c53 u32 inst; kvmppc_emulate_loadstore() local
61 emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst); kvmppc_emulate_loadstore()
65 ra = get_ra(inst); kvmppc_emulate_loadstore()
66 rs = get_rs(inst); kvmppc_emulate_loadstore()
67 rt = get_rt(inst); kvmppc_emulate_loadstore()
69 switch (get_op(inst)) { kvmppc_emulate_loadstore()
71 switch (get_xop(inst)) { kvmppc_emulate_loadstore()
172 rt = get_rt(inst); kvmppc_emulate_loadstore()
198 rs = get_rs(inst); kvmppc_emulate_loadstore()
265 trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated); kvmppc_emulate_loadstore()
H A Dbooke.h85 unsigned int inst, int *advance);
111 unsigned int inst, int *advance);
119 unsigned int inst, int *advance);
/linux-4.1.27/arch/ia64/kernel/
H A Dparavirt_patch.c99 ia64_inst_t inst; paravirt_read_slot0() local
100 inst.l = bundle->quad0.slot0; paravirt_read_slot0()
101 return inst; paravirt_read_slot0()
107 ia64_inst_t inst; paravirt_read_slot1() local
108 inst.l = bundle->quad0.slot1_p0 | paravirt_read_slot1()
110 return inst; paravirt_read_slot1()
116 ia64_inst_t inst; paravirt_read_slot2() local
117 inst.l = bundle->quad1.slot2; paravirt_read_slot2()
118 return inst; paravirt_read_slot2()
141 paravirt_write_slot0(bundle_t *bundle, ia64_inst_t inst) paravirt_write_slot0() argument
143 bundle->quad0.slot0 = inst.l; paravirt_write_slot0()
147 paravirt_write_slot1(bundle_t *bundle, ia64_inst_t inst) paravirt_write_slot1() argument
149 bundle->quad0.slot1_p0 = inst.l; paravirt_write_slot1()
150 bundle->quad1.slot1_p1 = inst.l >> 18UL; paravirt_write_slot1()
154 paravirt_write_slot2(bundle_t *bundle, ia64_inst_t inst) paravirt_write_slot2() argument
156 bundle->quad1.slot2 = inst.l; paravirt_write_slot2()
160 paravirt_write_inst(unsigned long tag, ia64_inst_t inst) paravirt_write_inst() argument
167 paravirt_write_slot0(bundle, inst); paravirt_write_inst()
170 paravirt_write_slot1(bundle, inst); paravirt_write_inst()
173 paravirt_write_slot2(bundle, inst); paravirt_write_inst()
353 ia64_inst_t inst; member in union:inst_x3_op
369 ia64_inst_t inst; member in union:inst_x3_imm
412 ia64_inst_t inst; member in union:inst_b1
431 ia64_inst_t inst = paravirt_read_inst(tag); paravirt_patch_reloc_br() local
437 inst_b1.l = inst.l; paravirt_patch_reloc_br()
444 inst.l = inst_b1.l; paravirt_patch_reloc_br()
446 paravirt_write_inst(tag, inst); paravirt_patch_reloc_br()
/linux-4.1.27/drivers/net/ethernet/broadcom/
H A Dbnx2_fw.h21 .inst = BNX2_COM_CPU_INSTRUCTION,
37 .inst = BNX2_CP_CPU_INSTRUCTION,
53 .inst = BNX2_RXP_CPU_INSTRUCTION,
69 .inst = BNX2_TPAT_CPU_INSTRUCTION,
85 .inst = BNX2_TXP_CPU_INSTRUCTION,
/linux-4.1.27/sound/drivers/opl3/
H A Dopl3_synth.c200 struct sbi_patch inst; snd_opl3_write() local
202 while (count >= sizeof(inst)) { snd_opl3_write()
204 if (copy_from_user(&inst, buf, sizeof(inst))) snd_opl3_write()
206 if (!memcmp(inst.key, FM_KEY_SBI, 4) || snd_opl3_write()
207 !memcmp(inst.key, FM_KEY_2OP, 4)) snd_opl3_write()
209 else if (!memcmp(inst.key, FM_KEY_4OP, 4)) snd_opl3_write()
213 err = snd_opl3_load_patch(opl3, inst.prog, inst.bank, type, snd_opl3_write()
214 inst.name, inst.extension, snd_opl3_write()
215 inst.data); snd_opl3_write()
218 result += sizeof(inst); snd_opl3_write()
219 count -= sizeof(inst); snd_opl3_write()
267 patch->inst.op[i].am_vib = data[AM_VIB + i]; snd_opl3_load_patch()
268 patch->inst.op[i].ksl_level = data[KSL_LEVEL + i]; snd_opl3_load_patch()
269 patch->inst.op[i].attack_decay = data[ATTACK_DECAY + i]; snd_opl3_load_patch()
270 patch->inst.op[i].sustain_release = data[SUSTAIN_RELEASE + i]; snd_opl3_load_patch()
271 patch->inst.op[i].wave_select = data[WAVE_SELECT + i]; snd_opl3_load_patch()
273 patch->inst.feedback_connection[0] = data[CONNECTION]; snd_opl3_load_patch()
277 patch->inst.op[i+2].am_vib = snd_opl3_load_patch()
279 patch->inst.op[i+2].ksl_level = snd_opl3_load_patch()
281 patch->inst.op[i+2].attack_decay = snd_opl3_load_patch()
283 patch->inst.op[i+2].sustain_release = snd_opl3_load_patch()
285 patch->inst.op[i+2].wave_select = snd_opl3_load_patch()
288 patch->inst.feedback_connection[1] = snd_opl3_load_patch()
293 patch->inst.echo_delay = ext[0]; snd_opl3_load_patch()
294 patch->inst.echo_atten = ext[1]; snd_opl3_load_patch()
295 patch->inst.chorus_spread = ext[2]; snd_opl3_load_patch()
296 patch->inst.trnsps = ext[3]; snd_opl3_load_patch()
297 patch->inst.fix_dur = ext[4]; snd_opl3_load_patch()
298 patch->inst.modes = ext[5]; snd_opl3_load_patch()
299 patch->inst.fix_key = ext[6]; snd_opl3_load_patch()
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/
H A Dclkgen_defs_asm.h41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46 #define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
49 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
H A Dtimer_defs_asm.h41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46 #define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
49 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
H A Dddr2_defs_asm.h41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46 #define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
49 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
H A Dpio_defs_asm.h41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
42 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46 #define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
49 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
50 ((inst) + offs + (index) * stride)
/linux-4.1.27/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/
H A Dconfig_defs_asm.h44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dtimer_defs_asm.h6 * file: ../../inst/timer/rtl/timer_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dbif_core_defs_asm.h6 * file: ../../inst/bif/rtl/bif_core_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
H A Dgio_defs_asm.h6 * file: ../../inst/gio/rtl/gio_regs.r
10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
/linux-4.1.27/arch/arm64/include/asm/
H A Dsysreg.h34 .inst 0xd5300000|(\sreg)|(__reg_num_\rt)
38 .inst 0xd5100000|(\sreg)|(__reg_num_\rt)
50 " .inst 0xd5300000|(\\sreg)|(__reg_num_\\rt)\n"
54 " .inst 0xd5100000|(\\sreg)|(__reg_num_\\rt)\n"
/linux-4.1.27/net/netfilter/ipset/
H A Dip_set_core.c59 #define ip_set(inst, id) \
60 ip_set_dereference((inst)->ip_set_list)[id]
474 struct ip_set_net *inst = ip_set_pernet(net); ip_set_rcu_get() local
478 set = rcu_dereference(inst->ip_set_list)[index]; ip_set_rcu_get()
579 struct ip_set_net *inst = ip_set_pernet(net); ip_set_get_byname() local
582 for (i = 0; i < inst->ip_set_max; i++) { ip_set_get_byname()
583 s = rcu_dereference(inst->ip_set_list)[i]; ip_set_get_byname()
605 __ip_set_put_byindex(struct ip_set_net *inst, ip_set_id_t index) __ip_set_put_byindex() argument
610 set = rcu_dereference(inst->ip_set_list)[index]; __ip_set_put_byindex()
619 struct ip_set_net *inst = ip_set_pernet(net); ip_set_put_byindex() local
621 __ip_set_put_byindex(inst, index); ip_set_put_byindex()
660 struct ip_set_net *inst = ip_set_pernet(net); ip_set_nfnl_get_byindex() local
662 if (index >= inst->ip_set_max) ip_set_nfnl_get_byindex()
666 set = ip_set(inst, index); ip_set_nfnl_get_byindex()
688 struct ip_set_net *inst = ip_set_pernet(net); ip_set_nfnl_put() local
691 if (!inst->is_deleted) { /* already deleted from ip_set_net_exit() */ ip_set_nfnl_put()
692 set = ip_set(inst, index); ip_set_nfnl_put()
753 find_set_and_id(struct ip_set_net *inst, const char *name, ip_set_id_t *id) find_set_and_id() argument
759 for (i = 0; i < inst->ip_set_max; i++) { find_set_and_id()
760 set = ip_set(inst, i); find_set_and_id()
770 find_set(struct ip_set_net *inst, const char *name) find_set() argument
774 return find_set_and_id(inst, name, &id); find_set()
778 find_free_id(struct ip_set_net *inst, const char *name, ip_set_id_t *index, find_free_id() argument
785 for (i = 0; i < inst->ip_set_max; i++) { find_free_id()
786 s = ip_set(inst, i); find_free_id()
816 struct ip_set_net *inst = ip_set_pernet(net); ip_set_create() local
886 ret = find_free_id(inst, set->name, &index, &clash); ip_set_create()
899 ip_set_id_t i = inst->ip_set_max + IP_SET_INC; ip_set_create()
901 if (i < inst->ip_set_max || i == IPSET_INVALID_ID) ip_set_create()
909 tmp = ip_set_dereference(inst->ip_set_list); ip_set_create()
910 memcpy(list, tmp, sizeof(struct ip_set *) * inst->ip_set_max); ip_set_create()
911 rcu_assign_pointer(inst->ip_set_list, list); ip_set_create()
915 index = inst->ip_set_max; ip_set_create()
916 inst->ip_set_max = i; ip_set_create()
926 ip_set(inst, index) = set; ip_set_create()
949 ip_set_destroy_set(struct ip_set_net *inst, ip_set_id_t index) ip_set_destroy_set() argument
951 struct ip_set *set = ip_set(inst, index); ip_set_destroy_set()
954 ip_set(inst, index) = NULL; ip_set_destroy_set()
967 struct ip_set_net *inst = ip_set_pernet(sock_net(ctnl)); ip_set_destroy() local
987 for (i = 0; i < inst->ip_set_max; i++) { ip_set_destroy()
988 s = ip_set(inst, i); ip_set_destroy()
995 for (i = 0; i < inst->ip_set_max; i++) { ip_set_destroy()
996 s = ip_set(inst, i); ip_set_destroy()
998 ip_set_destroy_set(inst, i); ip_set_destroy()
1001 s = find_set_and_id(inst, nla_data(attr[IPSET_ATTR_SETNAME]), ip_set_destroy()
1012 ip_set_destroy_set(inst, i); ip_set_destroy()
1037 struct ip_set_net *inst = ip_set_pernet(sock_net(ctnl)); ip_set_flush() local
1045 for (i = 0; i < inst->ip_set_max; i++) { ip_set_flush()
1046 s = ip_set(inst, i); ip_set_flush()
1051 s = find_set(inst, nla_data(attr[IPSET_ATTR_SETNAME])); ip_set_flush()
1077 struct ip_set_net *inst = ip_set_pernet(sock_net(ctnl)); ip_set_rename() local
1088 set = find_set(inst, nla_data(attr[IPSET_ATTR_SETNAME])); ip_set_rename()
1099 for (i = 0; i < inst->ip_set_max; i++) { ip_set_rename()
1100 s = ip_set(inst, i); ip_set_rename()
1127 struct ip_set_net *inst = ip_set_pernet(sock_net(ctnl)); ip_set_swap() local
1137 from = find_set_and_id(inst, nla_data(attr[IPSET_ATTR_SETNAME]), ip_set_swap()
1142 to = find_set_and_id(inst, nla_data(attr[IPSET_ATTR_SETNAME2]), ip_set_swap()
1160 ip_set(inst, from_id) = to; ip_set_swap()
1161 ip_set(inst, to_id) = from; ip_set_swap()
1180 struct ip_set_net *inst = (struct ip_set_net *)cb->args[IPSET_CB_NET]; ip_set_dump_done() local
1183 ip_set(inst, cb->args[IPSET_CB_INDEX])->name); ip_set_dump_done()
1184 __ip_set_put_byindex(inst, ip_set_dump_done()
1203 dump_init(struct netlink_callback *cb, struct ip_set_net *inst) dump_init() argument
1225 set = find_set_and_id(inst, nla_data(cda[IPSET_ATTR_SETNAME]), dump_init()
1239 cb->args[IPSET_CB_NET] = (unsigned long)inst; dump_init()
1252 struct ip_set_net *inst = ip_set_pernet(sock_net(skb->sk)); ip_set_dump_start() local
1257 ret = dump_init(cb, inst); ip_set_dump_start()
1268 if (cb->args[IPSET_CB_INDEX] >= inst->ip_set_max) ip_set_dump_start()
1274 : inst->ip_set_max; ip_set_dump_start()
1280 set = ip_set(inst, index); ip_set_dump_start()
1358 pr_debug("release set %s\n", ip_set(inst, index)->name); ip_set_dump_start()
1359 __ip_set_put_byindex(inst, index); ip_set_dump_start()
1463 struct ip_set_net *inst = ip_set_pernet(sock_net(ctnl)); ip_set_uadd() local
1482 set = find_set(inst, nla_data(attr[IPSET_ATTR_SETNAME])); ip_set_uadd()
1518 struct ip_set_net *inst = ip_set_pernet(sock_net(ctnl)); ip_set_udel() local
1537 set = find_set(inst, nla_data(attr[IPSET_ATTR_SETNAME])); ip_set_udel()
1573 struct ip_set_net *inst = ip_set_pernet(sock_net(ctnl)); ip_set_utest() local
1584 set = find_set(inst, nla_data(attr[IPSET_ATTR_SETNAME])); ip_set_utest()
1609 struct ip_set_net *inst = ip_set_pernet(sock_net(ctnl)); ip_set_header() local
1619 set = find_set(inst, nla_data(attr[IPSET_ATTR_SETNAME])); ip_set_header()
1845 struct ip_set_net *inst = ip_set_pernet(net); ip_set_sockfn_get() local
1902 find_set_and_id(inst, req_get->set.name, &id); ip_set_sockfn_get()
1917 find_set_and_id(inst, req_get->set.name, &id); ip_set_sockfn_get()
1920 req_get->family = ip_set(inst, id)->family; ip_set_sockfn_get()
1929 req_get->set.index >= inst->ip_set_max) { ip_set_sockfn_get()
1934 set = ip_set(inst, req_get->set.index); ip_set_sockfn_get()
1966 struct ip_set_net *inst = ip_set_pernet(net); ip_set_net_init() local
1969 inst->ip_set_max = max_sets ? max_sets : CONFIG_IP_SET_MAX; ip_set_net_init()
1970 if (inst->ip_set_max >= IPSET_INVALID_ID) ip_set_net_init()
1971 inst->ip_set_max = IPSET_INVALID_ID - 1; ip_set_net_init()
1973 list = kzalloc(sizeof(struct ip_set *) * inst->ip_set_max, GFP_KERNEL); ip_set_net_init()
1976 inst->is_deleted = 0; ip_set_net_init()
1977 rcu_assign_pointer(inst->ip_set_list, list); ip_set_net_init()
1984 struct ip_set_net *inst = ip_set_pernet(net); ip_set_net_exit() local
1989 inst->is_deleted = 1; /* flag for ip_set_nfnl_put */ ip_set_net_exit()
1991 for (i = 0; i < inst->ip_set_max; i++) { ip_set_net_exit()
1992 set = ip_set(inst, i); ip_set_net_exit()
1994 ip_set_destroy_set(inst, i); ip_set_net_exit()
1996 kfree(rcu_dereference_protected(inst->ip_set_list, 1)); ip_set_net_exit()
/linux-4.1.27/arch/powerpc/platforms/powermac/
H A Dlow_i2c.c1235 struct pmac_i2c_pf_inst *inst; pmac_i2c_do_begin() local
1255 inst = kzalloc(sizeof(struct pmac_i2c_pf_inst), GFP_KERNEL); pmac_i2c_do_begin()
1256 if (inst == NULL) { pmac_i2c_do_begin()
1260 inst->bus = bus; pmac_i2c_do_begin()
1261 inst->addr = pmac_i2c_get_dev_addr(func->node); pmac_i2c_do_begin()
1262 inst->quirks = (int)(long)func->driver_data; pmac_i2c_do_begin()
1263 return inst; pmac_i2c_do_begin()
1268 struct pmac_i2c_pf_inst *inst = instdata; pmac_i2c_do_end() local
1270 if (inst == NULL) pmac_i2c_do_end()
1272 pmac_i2c_close(inst->bus); pmac_i2c_do_end()
1273 kfree(inst); pmac_i2c_do_end()
1278 struct pmac_i2c_pf_inst *inst = instdata; pmac_i2c_do_read() local
1280 inst->bytes = len; pmac_i2c_do_read()
1281 return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_read, 0, 0, pmac_i2c_do_read()
1282 inst->buffer, len); pmac_i2c_do_read()
1287 struct pmac_i2c_pf_inst *inst = instdata; pmac_i2c_do_write() local
1289 return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_write, 0, 0, pmac_i2c_do_write()
1299 static void pmac_i2c_do_apply_rmw(struct pmac_i2c_pf_inst *inst, pmac_i2c_do_apply_rmw() argument
1304 if (inst->quirks & pmac_i2c_quirk_invmask) { pmac_i2c_do_apply_rmw()
1306 inst->scratch[i] = (inst->buffer[i] & mask[i]) | val[i]; pmac_i2c_do_apply_rmw()
1309 inst->scratch[i] = (inst->buffer[i] & ~mask[i]) pmac_i2c_do_apply_rmw()
1318 struct pmac_i2c_pf_inst *inst = instdata; pmac_i2c_do_rmw() local
1320 if (masklen > inst->bytes || valuelen > inst->bytes || pmac_i2c_do_rmw()
1321 totallen > inst->bytes || valuelen > masklen) pmac_i2c_do_rmw()
1324 pmac_i2c_do_apply_rmw(inst, masklen, maskdata, valuedata); pmac_i2c_do_rmw()
1326 return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_write, 0, 0, pmac_i2c_do_rmw()
1327 inst->scratch, totallen); pmac_i2c_do_rmw()
1332 struct pmac_i2c_pf_inst *inst = instdata; pmac_i2c_do_read_sub() local
1334 inst->bytes = len; pmac_i2c_do_read_sub()
1335 return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_read, 1, subaddr, pmac_i2c_do_read_sub()
1336 inst->buffer, len); pmac_i2c_do_read_sub()
1342 struct pmac_i2c_pf_inst *inst = instdata; pmac_i2c_do_write_sub() local
1344 return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_write, 1, pmac_i2c_do_write_sub()
1350 struct pmac_i2c_pf_inst *inst = instdata; pmac_i2c_do_set_mode() local
1352 return pmac_i2c_setmode(inst->bus, mode); pmac_i2c_do_set_mode()
1359 struct pmac_i2c_pf_inst *inst = instdata; pmac_i2c_do_rmw_sub() local
1361 if (masklen > inst->bytes || valuelen > inst->bytes || pmac_i2c_do_rmw_sub()
1362 totallen > inst->bytes || valuelen > masklen) pmac_i2c_do_rmw_sub()
1365 pmac_i2c_do_apply_rmw(inst, masklen, maskdata, valuedata); pmac_i2c_do_rmw_sub()
1367 return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_write, 1, pmac_i2c_do_rmw_sub()
1368 subaddr, inst->scratch, totallen); pmac_i2c_do_rmw_sub()
1375 struct pmac_i2c_pf_inst *inst = instdata; pmac_i2c_do_mask_and_comp() local
1383 if (len > inst->bytes) pmac_i2c_do_mask_and_comp()
1387 if ((inst->buffer[i] & maskdata[i]) != valuedata[i]) pmac_i2c_do_mask_and_comp()
/linux-4.1.27/arch/mips/kernel/
H A Dmips-r2-to-r6-emul.c27 #include <asm/inst.h>
883 static inline int mipsr2_find_op_func(struct pt_regs *regs, u32 inst, mipsr2_find_op_func() argument
890 if ((inst & p->mask) == p->code) { mipsr2_find_op_func()
891 err = (p->func)(regs, inst); mipsr2_find_op_func()
901 * @inst: Instruction to decode and emulate
904 int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) mipsr2_decoder() argument
923 inst, epc, pass); mipsr2_decoder()
925 switch (MIPSInst_OPCODE(inst)) { mipsr2_decoder()
927 err = mipsr2_find_op_func(regs, inst, spec_op_table); mipsr2_decoder()
935 err = mipsr2_find_op_func(regs, inst, spec2_op_table); mipsr2_decoder()
938 rt = MIPSInst_RT(inst); mipsr2_decoder()
939 rs = MIPSInst_RS(inst); mipsr2_decoder()
942 if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst)) mipsr2_decoder()
949 if (regs->regs[rs] >= MIPSInst_UIMM(inst)) mipsr2_decoder()
956 if ((long)regs->regs[rs] < MIPSInst_SIMM(inst)) mipsr2_decoder()
963 if (regs->regs[rs] < MIPSInst_UIMM(inst)) mipsr2_decoder()
970 if (regs->regs[rs] == MIPSInst_SIMM(inst)) mipsr2_decoder()
977 if (regs->regs[rs] != MIPSInst_SIMM(inst)) mipsr2_decoder()
1125 switch (MIPSInst_OPCODE(inst)) { mipsr2_decoder()
1199 rt = regs->regs[MIPSInst_RT(inst)]; mipsr2_decoder()
1200 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); mipsr2_decoder()
1264 if (MIPSInst_RT(inst) && !err) mipsr2_decoder()
1265 regs->regs[MIPSInst_RT(inst)] = rt; mipsr2_decoder()
1272 rt = regs->regs[MIPSInst_RT(inst)]; mipsr2_decoder()
1273 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); mipsr2_decoder()
1338 if (MIPSInst_RT(inst) && !err) mipsr2_decoder()
1339 regs->regs[MIPSInst_RT(inst)] = rt; mipsr2_decoder()
1346 rt = regs->regs[MIPSInst_RT(inst)]; mipsr2_decoder()
1347 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); mipsr2_decoder()
1416 rt = regs->regs[MIPSInst_RT(inst)]; mipsr2_decoder()
1417 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); mipsr2_decoder()
1491 rt = regs->regs[MIPSInst_RT(inst)]; mipsr2_decoder()
1492 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); mipsr2_decoder()
1598 if (MIPSInst_RT(inst) && !err) mipsr2_decoder()
1599 regs->regs[MIPSInst_RT(inst)] = rt; mipsr2_decoder()
1610 rt = regs->regs[MIPSInst_RT(inst)]; mipsr2_decoder()
1611 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); mipsr2_decoder()
1717 if (MIPSInst_RT(inst) && !err) mipsr2_decoder()
1718 regs->regs[MIPSInst_RT(inst)] = rt; mipsr2_decoder()
1729 rt = regs->regs[MIPSInst_RT(inst)]; mipsr2_decoder()
1730 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); mipsr2_decoder()
1847 rt = regs->regs[MIPSInst_RT(inst)]; mipsr2_decoder()
1848 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); mipsr2_decoder()
1960 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); mipsr2_decoder()
2009 if (MIPSInst_RT(inst) && !err) mipsr2_decoder()
2010 regs->regs[MIPSInst_RT(inst)] = res; mipsr2_decoder()
2016 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); mipsr2_decoder()
2048 res = regs->regs[MIPSInst_RT(inst)]; mipsr2_decoder()
2066 if (MIPSInst_RT(inst) && !err) mipsr2_decoder()
2067 regs->regs[MIPSInst_RT(inst)] = res; mipsr2_decoder()
2079 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); mipsr2_decoder()
2127 if (MIPSInst_RT(inst) && !err) mipsr2_decoder()
2128 regs->regs[MIPSInst_RT(inst)] = res; mipsr2_decoder()
2140 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); mipsr2_decoder()
2172 res = regs->regs[MIPSInst_RT(inst)]; mipsr2_decoder()
2190 if (MIPSInst_RT(inst) && !err) mipsr2_decoder()
2191 regs->regs[MIPSInst_RT(inst)] = res; mipsr2_decoder()
2209 err = get_user(inst, (u32 __user *)regs->cp0_epc); mipsr2_decoder()
/linux-4.1.27/arch/sh/kernel/
H A Dtraps_32.c573 unsigned short inst = 0; is_dsp_inst() local
582 get_user(inst, ((unsigned short *) regs->pc)); is_dsp_inst()
584 inst &= 0xf000; is_dsp_inst()
587 if ((inst == 0xf000) || (inst == 0x4000)) is_dsp_inst()
621 unsigned short inst = 0; do_reserved_inst() local
624 get_user(inst, (unsigned short*)regs->pc); do_reserved_inst()
626 err = do_fpu_inst(inst, regs); do_reserved_inst()
628 regs->pc += instruction_size(inst); do_reserved_inst()
631 /* not a FPU inst. */ do_reserved_inst()
653 static int emulate_branch(unsigned short inst, struct pt_regs *regs) emulate_branch() argument
666 if (((inst & 0xf000) == 0xb000) || /* bsr */ emulate_branch()
667 ((inst & 0xf0ff) == 0x0003) || /* bsrf */ emulate_branch()
668 ((inst & 0xf0ff) == 0x400b)) /* jsr */ emulate_branch()
671 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */ emulate_branch()
672 regs->pc += SH_PC_8BIT_OFFSET(inst); emulate_branch()
676 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */ emulate_branch()
677 regs->pc += SH_PC_12BIT_OFFSET(inst); emulate_branch()
681 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */ emulate_branch()
682 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4; emulate_branch()
686 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */ emulate_branch()
687 regs->pc = regs->regs[(inst & 0x0f00) >> 8]; emulate_branch()
691 if ((inst & 0xffff) == 0x000b) { /* rts */ emulate_branch()
703 unsigned long inst; do_illegal_slot_inst() local
710 get_user(inst, (unsigned short *)regs->pc + 1); do_illegal_slot_inst()
711 if (!do_fpu_inst(inst, regs)) { do_illegal_slot_inst()
712 get_user(inst, (unsigned short *)regs->pc); do_illegal_slot_inst()
713 if (!emulate_branch(inst, regs)) do_illegal_slot_inst()
717 /* not a FPU inst. */ do_illegal_slot_inst()
720 inst = lookup_exception_vector(); do_illegal_slot_inst()
724 die_if_no_fixup("illegal slot instruction", regs, inst); do_illegal_slot_inst()
/linux-4.1.27/arch/x86/include/asm/
H A Dasm.h22 #define __ASM_SIZE(inst, ...) __ASM_SEL(inst##l##__VA_ARGS__, \
23 inst##q##__VA_ARGS__)
/linux-4.1.27/arch/mips/include/asm/
H A Dbranch.h14 #include <asm/inst.h>
89 union mips16e_instruction *inst) MIPS16e_compute_return_epc()
92 if (inst->ri.opcode == MIPS16e_extend_op) { MIPS16e_compute_return_epc()
88 MIPS16e_compute_return_epc(struct pt_regs *regs, union mips16e_instruction *inst) MIPS16e_compute_return_epc() argument
H A Dmips-r2-to-r6-emul.h78 int (*func)(struct pt_regs *regs, u32 inst);
87 static inline int mipsr2_decoder(struct pt_regs *regs, u32 inst, mipsr2_decoder() argument
95 extern int mipsr2_decoder(struct pt_regs *regs, u32 inst,
/linux-4.1.27/arch/powerpc/mm/
H A Dicswx.c175 u32 inst; acop_get_inst() local
182 if (__get_user(inst, p)) acop_get_inst()
185 return inst; acop_get_inst()
201 u32 inst = 0; acop_handle_fault() local
221 inst = acop_get_inst(regs); acop_handle_fault()
222 if (inst == 0) acop_handle_fault()
225 rs = (inst >> (31 - 10)) & 0x1f; acop_handle_fault()
256 /* get inst if we don't already have it */ acop_handle_fault()
257 if (inst == 0) { acop_handle_fault()
258 inst = acop_get_inst(regs); acop_handle_fault()
259 if (inst == 0) acop_handle_fault()
264 if (inst & 1) { acop_handle_fault()
/linux-4.1.27/arch/tile/lib/
H A Dmemcpy_user_64.c28 #define _ST(p, inst, v) \
30 asm("1: " #inst " %0, %1;" \
40 #define _LD(p, inst) \
43 asm("1: " #inst " %0, %1;" \
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
H A Dnv40.c37 u32 inst = *(u32 *)arg << 4; nv40_mpeg_mthd_dma() local
38 u32 dma0 = nv_ro32(imem, inst + 0); nv40_mpeg_mthd_dma()
39 u32 dma1 = nv_ro32(imem, inst + 4); nv40_mpeg_mthd_dma()
40 u32 dma2 = nv_ro32(imem, inst + 8); nv40_mpeg_mthd_dma()
H A Dnv44.c67 u32 inst = 0x80000000 | nv_gpuobj(chan)->addr >> 4; nv44_mpeg_context_fini() local
70 if (nv_rd32(priv, 0x00b318) == inst) nv44_mpeg_context_fini()
101 u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff; nv44_mpeg_intr() local
109 engctx = nvkm_engctx_get(engine, inst); nv44_mpeg_intr()
133 chid, inst << 4, nvkm_client_name(engctx), stat, nv44_mpeg_intr()
/linux-4.1.27/include/crypto/
H A Dalgapi.h54 void (*free)(struct crypto_instance *inst);
63 struct crypto_instance *inst; member in struct:crypto_spawn
139 struct crypto_instance *inst);
140 int crypto_unregister_instance(struct crypto_instance *inst);
143 struct crypto_instance *inst, u32 mask);
145 struct crypto_instance *inst,
154 struct crypto_instance *inst) crypto_set_spawn()
156 spawn->inst = inst; crypto_set_spawn()
221 static inline void *crypto_instance_ctx(struct crypto_instance *inst) crypto_instance_ctx() argument
223 return inst->__ctx; crypto_instance_ctx()
153 crypto_set_spawn(struct crypto_spawn *spawn, struct crypto_instance *inst) crypto_set_spawn() argument
/linux-4.1.27/drivers/edac/
H A Damd8131_edac.c71 .inst = NORTH_A,
76 .inst = NORTH_B,
81 .inst = SOUTH_A,
86 .inst = SOUTH_B,
90 {.inst = NO_BRIDGE,},
253 for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE; amd8131_probe()
258 if (dev_info->inst == NO_BRIDGE) /* should never happen */ amd8131_probe()
317 for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE; amd8131_remove()
322 if (dev_info->inst == NO_BRIDGE) /* should never happen */ amd8131_remove()
/linux-4.1.27/drivers/mcb/
H A Dmcb-internal.h59 * @inst: the instance number of the device, 0 is first instance
94 * @inst: the instance number of the device, 0 is first instance
107 unsigned int inst:6; member in struct:chameleon_bdd
/linux-4.1.27/arch/x86/lib/
H A Drwsem.S21 #define __ASM_HALF_SIZE(inst) __ASM_SEL(inst##w, inst##l)
/linux-4.1.27/arch/unicore32/kernel/
H A Dfpu-ucf64.c78 void ucf64_exchandler(u32 inst, u32 fpexc, struct pt_regs *regs) ucf64_exchandler() argument
84 inst, fpexc); ucf64_exchandler()
95 cff(FPSCR), inst); ucf64_exchandler()
/linux-4.1.27/arch/mips/include/asm/netlogic/xlp-hal/
H A Dpcibus.h101 #define nlm_get_pcie_base(node, inst) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
102 XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst))
H A Duart.h96 #define nlm_get_uart_pcibase(node, inst) \
98 XLP_IO_UART_OFFSET(node, inst))
99 #define nlm_get_uart_regbase(node, inst) \
100 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
/linux-4.1.27/arch/mips/netlogic/xlp/
H A Dusb-init.c65 #define nlm_get_usb_pcibase(node, inst) \
66 nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst))
67 #define nlm_get_usb_regbase(node, inst) \
68 (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)

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