1#ifndef __ddr2_defs_asm_h 2#define __ddr2_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: ddr2.r 7 * 8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r 9 * Any changes here will be lost. 10 * 11 * -*- buffer-read-only: t -*- 12 */ 13 14#ifndef REG_FIELD 15#define REG_FIELD( scope, reg, field, value ) \ 16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 17#define REG_FIELD_X_( value, shift ) ((value) << shift) 18#endif 19 20#ifndef REG_STATE 21#define REG_STATE( scope, reg, field, symbolic_value ) \ 22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 23#define REG_STATE_X_( k, shift ) (k << shift) 24#endif 25 26#ifndef REG_MASK 27#define REG_MASK( scope, reg, field ) \ 28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 30#endif 31 32#ifndef REG_LSB 33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 34#endif 35 36#ifndef REG_BIT 37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 38#endif 39 40#ifndef REG_ADDR 41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 42#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 43#endif 44 45#ifndef REG_ADDR_VECT 46#define REG_ADDR_VECT( scope, inst, reg, index ) \ 47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 48 STRIDE_##scope##_##reg ) 49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 50 ((inst) + offs + (index) * stride) 51#endif 52 53/* Register rw_cfg, scope ddr2, type rw */ 54#define reg_ddr2_rw_cfg___col_width___lsb 0 55#define reg_ddr2_rw_cfg___col_width___width 4 56#define reg_ddr2_rw_cfg___nr_banks___lsb 4 57#define reg_ddr2_rw_cfg___nr_banks___width 1 58#define reg_ddr2_rw_cfg___nr_banks___bit 4 59#define reg_ddr2_rw_cfg___bw___lsb 5 60#define reg_ddr2_rw_cfg___bw___width 1 61#define reg_ddr2_rw_cfg___bw___bit 5 62#define reg_ddr2_rw_cfg___nr_ref___lsb 6 63#define reg_ddr2_rw_cfg___nr_ref___width 4 64#define reg_ddr2_rw_cfg___ref_interval___lsb 10 65#define reg_ddr2_rw_cfg___ref_interval___width 11 66#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21 67#define reg_ddr2_rw_cfg___odt_ctrl___width 2 68#define reg_ddr2_rw_cfg___odt_mem___lsb 23 69#define reg_ddr2_rw_cfg___odt_mem___width 1 70#define reg_ddr2_rw_cfg___odt_mem___bit 23 71#define reg_ddr2_rw_cfg___imp_strength___lsb 24 72#define reg_ddr2_rw_cfg___imp_strength___width 1 73#define reg_ddr2_rw_cfg___imp_strength___bit 24 74#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25 75#define reg_ddr2_rw_cfg___auto_imp_cal___width 1 76#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25 77#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26 78#define reg_ddr2_rw_cfg___imp_cal_override___width 1 79#define reg_ddr2_rw_cfg___imp_cal_override___bit 26 80#define reg_ddr2_rw_cfg___dll_override___lsb 27 81#define reg_ddr2_rw_cfg___dll_override___width 1 82#define reg_ddr2_rw_cfg___dll_override___bit 27 83#define reg_ddr2_rw_cfg_offset 0 84 85/* Register rw_timing, scope ddr2, type rw */ 86#define reg_ddr2_rw_timing___wr___lsb 0 87#define reg_ddr2_rw_timing___wr___width 3 88#define reg_ddr2_rw_timing___rcd___lsb 3 89#define reg_ddr2_rw_timing___rcd___width 3 90#define reg_ddr2_rw_timing___rp___lsb 6 91#define reg_ddr2_rw_timing___rp___width 3 92#define reg_ddr2_rw_timing___ras___lsb 9 93#define reg_ddr2_rw_timing___ras___width 4 94#define reg_ddr2_rw_timing___rfc___lsb 13 95#define reg_ddr2_rw_timing___rfc___width 7 96#define reg_ddr2_rw_timing___rc___lsb 20 97#define reg_ddr2_rw_timing___rc___width 5 98#define reg_ddr2_rw_timing___rtp___lsb 25 99#define reg_ddr2_rw_timing___rtp___width 2 100#define reg_ddr2_rw_timing___rtw___lsb 27 101#define reg_ddr2_rw_timing___rtw___width 3 102#define reg_ddr2_rw_timing___wtr___lsb 30 103#define reg_ddr2_rw_timing___wtr___width 2 104#define reg_ddr2_rw_timing_offset 4 105 106/* Register rw_latency, scope ddr2, type rw */ 107#define reg_ddr2_rw_latency___cas___lsb 0 108#define reg_ddr2_rw_latency___cas___width 3 109#define reg_ddr2_rw_latency___additive___lsb 3 110#define reg_ddr2_rw_latency___additive___width 3 111#define reg_ddr2_rw_latency_offset 8 112 113/* Register rw_phy_cfg, scope ddr2, type rw */ 114#define reg_ddr2_rw_phy_cfg___en___lsb 0 115#define reg_ddr2_rw_phy_cfg___en___width 1 116#define reg_ddr2_rw_phy_cfg___en___bit 0 117#define reg_ddr2_rw_phy_cfg_offset 12 118 119/* Register rw_phy_ctrl, scope ddr2, type rw */ 120#define reg_ddr2_rw_phy_ctrl___rst___lsb 0 121#define reg_ddr2_rw_phy_ctrl___rst___width 1 122#define reg_ddr2_rw_phy_ctrl___rst___bit 0 123#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1 124#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1 125#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1 126#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2 127#define reg_ddr2_rw_phy_ctrl___cal_start___width 1 128#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2 129#define reg_ddr2_rw_phy_ctrl_offset 16 130 131/* Register rw_ctrl, scope ddr2, type rw */ 132#define reg_ddr2_rw_ctrl___mrs_data___lsb 0 133#define reg_ddr2_rw_ctrl___mrs_data___width 16 134#define reg_ddr2_rw_ctrl___cmd___lsb 16 135#define reg_ddr2_rw_ctrl___cmd___width 8 136#define reg_ddr2_rw_ctrl_offset 20 137 138/* Register rw_pwr_down, scope ddr2, type rw */ 139#define reg_ddr2_rw_pwr_down___self_ref___lsb 0 140#define reg_ddr2_rw_pwr_down___self_ref___width 2 141#define reg_ddr2_rw_pwr_down___phy_en___lsb 2 142#define reg_ddr2_rw_pwr_down___phy_en___width 1 143#define reg_ddr2_rw_pwr_down___phy_en___bit 2 144#define reg_ddr2_rw_pwr_down_offset 24 145 146/* Register r_stat, scope ddr2, type r */ 147#define reg_ddr2_r_stat___dll_lock___lsb 0 148#define reg_ddr2_r_stat___dll_lock___width 1 149#define reg_ddr2_r_stat___dll_lock___bit 0 150#define reg_ddr2_r_stat___dll_delay_code___lsb 1 151#define reg_ddr2_r_stat___dll_delay_code___width 7 152#define reg_ddr2_r_stat___imp_cal_done___lsb 8 153#define reg_ddr2_r_stat___imp_cal_done___width 1 154#define reg_ddr2_r_stat___imp_cal_done___bit 8 155#define reg_ddr2_r_stat___imp_cal_fault___lsb 9 156#define reg_ddr2_r_stat___imp_cal_fault___width 1 157#define reg_ddr2_r_stat___imp_cal_fault___bit 9 158#define reg_ddr2_r_stat___cal_imp_pu___lsb 10 159#define reg_ddr2_r_stat___cal_imp_pu___width 4 160#define reg_ddr2_r_stat___cal_imp_pd___lsb 14 161#define reg_ddr2_r_stat___cal_imp_pd___width 4 162#define reg_ddr2_r_stat_offset 28 163 164/* Register rw_imp_ctrl, scope ddr2, type rw */ 165#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0 166#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4 167#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4 168#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4 169#define reg_ddr2_rw_imp_ctrl_offset 32 170 171#define STRIDE_ddr2_rw_dll_ctrl 4 172/* Register rw_dll_ctrl, scope ddr2, type rw */ 173#define reg_ddr2_rw_dll_ctrl___mode___lsb 0 174#define reg_ddr2_rw_dll_ctrl___mode___width 1 175#define reg_ddr2_rw_dll_ctrl___mode___bit 0 176#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1 177#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7 178#define reg_ddr2_rw_dll_ctrl_offset 36 179 180#define STRIDE_ddr2_rw_dqs_dll_ctrl 4 181/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ 182#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0 183#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7 184#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7 185#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7 186#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14 187#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7 188#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21 189#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7 190#define reg_ddr2_rw_dqs_dll_ctrl_offset 52 191 192 193/* Constants */ 194#define regk_ddr2_al0 0x00000000 195#define regk_ddr2_al1 0x00000008 196#define regk_ddr2_al2 0x00000010 197#define regk_ddr2_al3 0x00000018 198#define regk_ddr2_al4 0x00000020 199#define regk_ddr2_auto 0x00000003 200#define regk_ddr2_bank4 0x00000000 201#define regk_ddr2_bank8 0x00000001 202#define regk_ddr2_bl4 0x00000002 203#define regk_ddr2_bl8 0x00000003 204#define regk_ddr2_bt_il 0x00000008 205#define regk_ddr2_bt_seq 0x00000000 206#define regk_ddr2_bw16 0x00000001 207#define regk_ddr2_bw32 0x00000000 208#define regk_ddr2_cas2 0x00000020 209#define regk_ddr2_cas3 0x00000030 210#define regk_ddr2_cas4 0x00000040 211#define regk_ddr2_cas5 0x00000050 212#define regk_ddr2_deselect 0x000000c0 213#define regk_ddr2_dic_weak 0x00000002 214#define regk_ddr2_direct 0x00000001 215#define regk_ddr2_dis 0x00000000 216#define regk_ddr2_dll_dis 0x00000001 217#define regk_ddr2_dll_en 0x00000000 218#define regk_ddr2_dll_rst 0x00000100 219#define regk_ddr2_emrs 0x00000081 220#define regk_ddr2_emrs2 0x00000082 221#define regk_ddr2_emrs3 0x00000083 222#define regk_ddr2_full 0x00000001 223#define regk_ddr2_hi_ref_rate 0x00000080 224#define regk_ddr2_mrs 0x00000080 225#define regk_ddr2_no 0x00000000 226#define regk_ddr2_nop 0x000000b8 227#define regk_ddr2_ocd_adj 0x00000200 228#define regk_ddr2_ocd_default 0x00000380 229#define regk_ddr2_ocd_drive0 0x00000100 230#define regk_ddr2_ocd_drive1 0x00000080 231#define regk_ddr2_ocd_exit 0x00000000 232#define regk_ddr2_odt_dis 0x00000000 233#define regk_ddr2_offs 0x00000000 234#define regk_ddr2_pre 0x00000090 235#define regk_ddr2_pre_all 0x00000400 236#define regk_ddr2_pwr_down_fast 0x00000000 237#define regk_ddr2_pwr_down_slow 0x00001000 238#define regk_ddr2_ref 0x00000088 239#define regk_ddr2_rtt150 0x00000040 240#define regk_ddr2_rtt50 0x00000044 241#define regk_ddr2_rtt75 0x00000004 242#define regk_ddr2_rw_cfg_default 0x00186000 243#define regk_ddr2_rw_dll_ctrl_default 0x00000000 244#define regk_ddr2_rw_dll_ctrl_size 0x00000004 245#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000 246#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004 247#define regk_ddr2_rw_latency_default 0x00000000 248#define regk_ddr2_rw_phy_cfg_default 0x00000000 249#define regk_ddr2_rw_pwr_down_default 0x00000000 250#define regk_ddr2_rw_timing_default 0x00000000 251#define regk_ddr2_s1Gb 0x0000001a 252#define regk_ddr2_s256Mb 0x0000000f 253#define regk_ddr2_s2Gb 0x00000027 254#define regk_ddr2_s4Gb 0x00000042 255#define regk_ddr2_s512Mb 0x00000015 256#define regk_ddr2_temp0_85 0x00000618 257#define regk_ddr2_temp85_95 0x0000030c 258#define regk_ddr2_term150 0x00000002 259#define regk_ddr2_term50 0x00000003 260#define regk_ddr2_term75 0x00000001 261#define regk_ddr2_test 0x00000080 262#define regk_ddr2_weak 0x00000000 263#define regk_ddr2_wr2 0x00000200 264#define regk_ddr2_wr3 0x00000400 265#define regk_ddr2_yes 0x00000001 266#endif /* __ddr2_defs_asm_h */ 267