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Searched refs:enable_mask (Results 1 – 110 of 110) sorted by relevance

/linux-4.1.27/drivers/clk/qcom/
Dgcc-msm8660.c53 .enable_mask = BIT(8),
130 .enable_mask = BIT(11),
146 .enable_mask = BIT(9),
181 .enable_mask = BIT(11),
197 .enable_mask = BIT(9),
232 .enable_mask = BIT(11),
248 .enable_mask = BIT(9),
283 .enable_mask = BIT(11),
299 .enable_mask = BIT(9),
334 .enable_mask = BIT(11),
[all …]
Dgcc-ipq806x.c53 .enable_mask = BIT(0),
80 .enable_mask = BIT(4),
107 .enable_mask = BIT(8),
134 .enable_mask = BIT(14),
240 .enable_mask = BIT(11),
256 .enable_mask = BIT(9),
291 .enable_mask = BIT(11),
307 .enable_mask = BIT(9),
342 .enable_mask = BIT(11),
358 .enable_mask = BIT(9),
[all …]
Dgcc-msm8960.c53 .enable_mask = BIT(4),
80 .enable_mask = BIT(8),
107 .enable_mask = BIT(14),
197 .enable_mask = BIT(11),
213 .enable_mask = BIT(9),
248 .enable_mask = BIT(11),
264 .enable_mask = BIT(9),
299 .enable_mask = BIT(11),
315 .enable_mask = BIT(9),
350 .enable_mask = BIT(11),
[all …]
Dmmcc-apq8084.c241 .enable_mask = BIT(0),
268 .enable_mask = BIT(1),
1127 .enable_mask = BIT(0),
1142 .enable_mask = BIT(0),
1159 .enable_mask = BIT(0),
1176 .enable_mask = BIT(0),
1193 .enable_mask = BIT(0),
1210 .enable_mask = BIT(0),
1227 .enable_mask = BIT(0),
1244 .enable_mask = BIT(0),
[all …]
Dmmcc-msm8960.c171 .enable_mask = BIT(2),
186 .enable_mask = BIT(0),
220 .enable_mask = BIT(2),
235 .enable_mask = BIT(0),
269 .enable_mask = BIT(2),
284 .enable_mask = BIT(0),
324 .enable_mask = BIT(2),
339 .enable_mask = BIT(0),
355 .enable_mask = BIT(8),
388 .enable_mask = BIT(2),
[all …]
Dmmcc-msm8974.c206 .enable_mask = BIT(0),
233 .enable_mask = BIT(1),
954 .enable_mask = BIT(0),
970 .enable_mask = BIT(0),
987 .enable_mask = BIT(0),
1003 .enable_mask = BIT(0),
1020 .enable_mask = BIT(0),
1037 .enable_mask = BIT(0),
1054 .enable_mask = BIT(0),
1071 .enable_mask = BIT(0),
[all …]
Dgcc-apq8084.c128 .enable_mask = BIT(0),
191 .enable_mask = BIT(1),
218 .enable_mask = BIT(4),
290 .enable_mask = BIT(0),
307 .enable_mask = BIT(0),
1333 .enable_mask = BIT(0),
1387 .enable_mask = BIT(12),
1404 .enable_mask = BIT(17),
1420 .enable_mask = BIT(0),
1437 .enable_mask = BIT(0),
[all …]
Dgcc-msm8974.c84 .enable_mask = BIT(0),
147 .enable_mask = BIT(1),
174 .enable_mask = BIT(4),
1049 .enable_mask = BIT(26),
1065 .enable_mask = BIT(12),
1082 .enable_mask = BIT(17),
1098 .enable_mask = BIT(0),
1115 .enable_mask = BIT(0),
1132 .enable_mask = BIT(0),
1149 .enable_mask = BIT(0),
[all …]
Dgcc-msm8916.c213 .enable_mask = BIT(0),
240 .enable_mask = BIT(1),
267 .enable_mask = BIT(2),
294 .enable_mask = BIT(3),
1141 .enable_mask = BIT(10),
1157 .enable_mask = BIT(0),
1174 .enable_mask = BIT(0),
1191 .enable_mask = BIT(0),
1208 .enable_mask = BIT(0),
1225 .enable_mask = BIT(0),
[all …]
Dclk-regmap.c41 return (val & rclk->enable_mask) == 0; in clk_is_enabled_regmap()
43 return (val & rclk->enable_mask) != 0; in clk_is_enabled_regmap()
64 val = rclk->enable_mask; in clk_enable_regmap()
67 rclk->enable_mask, val); in clk_enable_regmap()
86 val = rclk->enable_mask; in clk_disable_regmap()
90 regmap_update_bits(rclk->regmap, rclk->enable_reg, rclk->enable_mask, in clk_disable_regmap()
Dlcc-msm8960.c119 .enable_mask = BIT(9),
140 .enable_mask = BIT(17),
157 .enable_mask = BIT(15),
173 .enable_mask = BIT(15),
225 .enable_mask = BIT(9), \
246 .enable_mask = BIT(21), \
277 .enable_mask = BIT(19), \
369 .enable_mask = BIT(9),
386 .enable_mask = BIT(11),
437 .enable_mask = BIT(9),
[all …]
Dlcc-ipq806x.c138 .enable_mask = BIT(9),
159 .enable_mask = BIT(17),
190 .enable_mask = BIT(15),
252 .enable_mask = BIT(9),
269 .enable_mask = BIT(11),
332 .enable_mask = BIT(9),
353 .enable_mask = BIT(12),
391 .enable_mask = BIT(11),
Dclk-regmap.h34 unsigned int enable_mask; member
Dclk-pll.c160 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_set_rate() local
167 enabled = (mode & enable_mask) == enable_mask; in clk_pll_set_rate()
/linux-4.1.27/arch/arm/mach-ep93xx/
Dclock.c36 u32 enable_mask; member
57 .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
64 .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
71 .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
92 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
98 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
113 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
120 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
128 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
136 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
[all …]
/linux-4.1.27/arch/arm/mach-lpc32xx/
Dclock.c550 tmp &= ~clk->enable_mask; in local_onoff_enable()
552 tmp |= clk->enable_mask; in local_onoff_enable()
564 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
571 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
578 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
585 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
592 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN,
599 .enable_mask = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
606 .enable_mask = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
613 .enable_mask = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
[all …]
Dclock.h35 u32 enable_mask; member
/linux-4.1.27/drivers/regulator/
Drk808-regulator.c122 rdev->desc->enable_mask, in rk808_set_suspend_enable()
133 rdev->desc->enable_mask, in rk808_set_suspend_disable()
134 rdev->desc->enable_mask); in rk808_set_suspend_disable()
185 .enable_mask = BIT(0),
199 .enable_mask = BIT(1),
209 .enable_mask = BIT(2),
223 .enable_mask = BIT(3),
237 .enable_mask = BIT(0),
252 .enable_mask = BIT(1),
267 .enable_mask = BIT(2),
[all …]
Dlp8788-ldo.c203 .enable_mask = LP8788_EN_DLDO1_M,
216 .enable_mask = LP8788_EN_DLDO2_M,
229 .enable_mask = LP8788_EN_DLDO3_M,
242 .enable_mask = LP8788_EN_DLDO4_M,
255 .enable_mask = LP8788_EN_DLDO5_M,
268 .enable_mask = LP8788_EN_DLDO6_M,
281 .enable_mask = LP8788_EN_DLDO7_M,
294 .enable_mask = LP8788_EN_DLDO8_M,
307 .enable_mask = LP8788_EN_DLDO9_M,
320 .enable_mask = LP8788_EN_DLDO10_M,
[all …]
Dpbias-regulator.c32 u32 enable_mask; member
64 .enable_mask = BIT(1),
73 .enable_mask = BIT(9),
81 .enable_mask = BIT(26) | BIT(25) | BIT(22),
90 .enable_mask = BIT(27) | BIT(25) | BIT(26),
164 drvdata[data_idx].desc.enable_mask = info->enable_mask; in pbias_regulator_probe()
Dmax77686.c142 rdev->desc->enable_mask, val << shift); in max77686_set_suspend_disable()
176 rdev->desc->enable_mask, in max77686_set_suspend_mode()
210 rdev->desc->enable_mask, in max77686_ldo_set_suspend_mode()
231 rdev->desc->enable_mask, in max77686_enable()
283 desc->enable_mask, in max77686_of_parse_cb()
356 .enable_mask = MAX77686_OPMODE_MASK \
374 .enable_mask = MAX77686_OPMODE_MASK \
392 .enable_mask = MAX77686_OPMODE_MASK \
410 .enable_mask = MAX77686_OPMODE_MASK \
429 .enable_mask = MAX77686_OPMODE_MASK, \
[all …]
Ds2mps11.c273 .enable_mask = S2MPS11_ENABLE_MASK \
289 .enable_mask = S2MPS11_ENABLE_MASK \
305 .enable_mask = S2MPS11_ENABLE_MASK \
321 .enable_mask = S2MPS11_ENABLE_MASK \
337 .enable_mask = S2MPS11_ENABLE_MASK \
406 .enable_mask = S2MPS14_ENABLE_MASK \
423 .enable_mask = S2MPS14_ENABLE_MASK \
440 .enable_mask = S2MPS14_ENABLE_MASK \
457 .enable_mask = S2MPS14_ENABLE_MASK \
526 val = rdev->desc->enable_mask; in s2mps14_regulator_enable()
[all …]
Das3722-regulator.c68 u8 enable_mask; member
97 .enable_mask = AS3722_SDn_CTRL(0),
109 .enable_mask = AS3722_SDn_CTRL(1),
122 .enable_mask = AS3722_SDn_CTRL(2),
136 .enable_mask = AS3722_SDn_CTRL(3),
150 .enable_mask = AS3722_SDn_CTRL(4),
164 .enable_mask = AS3722_SDn_CTRL(5),
177 .enable_mask = AS3722_SDn_CTRL(6),
190 .enable_mask = AS3722_LDO0_CTRL,
202 .enable_mask = AS3722_LDO1_CTRL,
[all …]
Daat2870-regulator.c38 u8 enable_mask; member
74 return aat2870->update(aat2870, ri->enable_addr, ri->enable_mask, in aat2870_ldo_enable()
75 ri->enable_mask); in aat2870_ldo_enable()
83 return aat2870->update(aat2870, ri->enable_addr, ri->enable_mask, 0); in aat2870_ldo_disable()
97 return val & ri->enable_mask ? 1 : 0; in aat2870_ldo_is_enabled()
153 ri->enable_mask = 0x1 << ri->enable_shift; in aat2870_get_regulator()
Dmax77843.c48 return (reg & rdev->desc->enable_mask) == rdev->desc->enable_mask; in max77843_reg_is_enabled()
127 .enable_mask = MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT1,
142 .enable_mask = MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT2,
155 .enable_mask = MAX77843_CHG_MASK,
Dwm8400-regulator.c128 .enable_mask = WM8400_LDO1_ENA,
142 .enable_mask = WM8400_LDO2_ENA,
156 .enable_mask = WM8400_LDO3_ENA,
170 .enable_mask = WM8400_LDO4_ENA,
184 .enable_mask = WM8400_DC1_ENA_MASK,
198 .enable_mask = WM8400_DC1_ENA_MASK,
Dmax77802.c114 rdev->desc->enable_mask, val << shift); in max77802_set_suspend_disable()
144 rdev->desc->enable_mask, val << shift); in max77802_set_mode()
218 rdev->desc->enable_mask, val << shift); in max77802_set_suspend_mode()
231 rdev->desc->enable_mask, in max77802_enable()
380 .enable_mask = MAX77802_OPMODE_MASK << MAX77802_OPMODE_SHIFT_LDO, \
401 .enable_mask = MAX77802_OPMODE_MASK << MAX77802_OPMODE_SHIFT_LDO, \
422 .enable_mask = MAX77802_OPMODE_MASK, \
443 .enable_mask = MAX77802_OPMODE_MASK << \
465 .enable_mask = MAX77802_OPMODE_MASK, \
486 .enable_mask = MAX77802_OPMODE_MASK, \
Dmax77693.c49 return (val & rdev->desc->enable_mask) == rdev->desc->enable_mask; in max77693_chg_is_enabled()
141 .enable_mask = SAFEOUT_CTRL_ENSAFEOUT##_num##_MASK , \
156 .enable_mask = CHG_CNFG_00_CHG_MASK |
Disl9305.c84 .enable_mask = ISL9305_DCD1_EN,
98 .enable_mask = ISL9305_DCD2_EN,
112 .enable_mask = ISL9305_LDO1_EN,
126 .enable_mask = ISL9305_LDO2_EN,
Dlp872x.c532 .enable_mask = LP872X_EN_LDO1_M,
545 .enable_mask = LP872X_EN_LDO2_M,
558 .enable_mask = LP872X_EN_LDO3_M,
571 .enable_mask = LP872X_EN_LDO4_M,
584 .enable_mask = LP872X_EN_LDO5_M,
595 .enable_mask = LP8720_EN_BUCK_M,
611 .enable_mask = LP872X_EN_LDO1_M,
624 .enable_mask = LP872X_EN_LDO2_M,
637 .enable_mask = LP872X_EN_LDO3_M,
650 .enable_mask = LP872X_EN_LDO4_M,
[all …]
Dmax14577.c115 .enable_mask = CTRL2_SFOUTORD_MASK,
126 .enable_mask = CHGCTRL2_MBCHOSTEN_MASK,
153 .enable_mask = CTRL2_SFOUTORD_MASK,
164 .enable_mask = CHGCTRL2_MBCHOSTEN_MASK,
178 .enable_mask = MAX77836_CNFG1_LDO_PWRMD_MASK,
194 .enable_mask = MAX77836_CNFG1_LDO_PWRMD_MASK,
Drt5033-regulator.c49 .enable_mask = RT5033_CTRL_EN_BUCK_MASK,
65 .enable_mask = RT5033_CTRL_EN_LDO_MASK,
80 .enable_mask = RT5033_CTRL_EN_SAFE_LDO_MASK,
Dtps65217-regulator.c44 .enable_mask = _em, \
81 dev->desc->enable_mask, dev->desc->enable_mask, in tps65217_pmic_enable()
95 dev->desc->enable_mask, TPS65217_PROTECT_L1); in tps65217_pmic_disable()
Dtps65218-regulator.c44 .enable_mask = _em, \
138 dev->desc->enable_mask, dev->desc->enable_mask, in tps65218_pmic_enable()
152 dev->desc->enable_mask, TPS65218_PROTECT_L1); in tps65218_pmic_disable()
Dhelpers.c40 val &= rdev->desc->enable_mask; in regulator_is_enabled_regmap()
72 val = rdev->desc->enable_mask; in regulator_enable_regmap()
76 rdev->desc->enable_mask, val); in regulator_enable_regmap()
96 val = rdev->desc->enable_mask; in regulator_disable_regmap()
102 rdev->desc->enable_mask, val); in regulator_disable_regmap()
Dhi6421-regulator.c183 .enable_mask = emask, \
220 .enable_mask = emask, \
257 .enable_mask = emask, \
291 .enable_mask = emask, \
324 .enable_mask = emask, \
Ds2mpa01.c250 .enable_mask = S2MPA01_ENABLE_MASK \
266 .enable_mask = S2MPA01_ENABLE_MASK \
282 .enable_mask = S2MPA01_ENABLE_MASK \
298 .enable_mask = S2MPA01_ENABLE_MASK \
Dwm8350-regulator.c1005 .enable_mask = WM8350_DC1_ENA,
1015 .enable_mask = WM8350_DC2_ENA,
1030 .enable_mask = WM8350_DC3_ENA,
1045 .enable_mask = WM8350_DC4_ENA,
1055 .enable_mask = WM8350_DC5_ENA,
1070 .enable_mask = WM8350_DC6_ENA,
1085 .enable_mask = WM8350_LDO1_ENA,
1100 .enable_mask = WM8350_LDO2_ENA,
1115 .enable_mask = WM8350_LDO3_ENA,
1130 .enable_mask = WM8350_LDO4_ENA,
Daxp20x-regulator.c51 .enable_mask = (_emask), \
73 .enable_mask = (_emask), \
105 .enable_mask = (_emask), \
Das3711-regulator.c41 unsigned int fast_bit = rdev->desc->enable_mask, in as3711_set_mode_sd()
65 unsigned int fast_bit = rdev->desc->enable_mask, in as3711_get_mode_sd()
145 .enable_mask = BIT(_en_bit), \
D88pm8607.c247 .enable_mask = (ebit), \
266 .enable_mask = 1 << (ebit), \
285 .enable_mask = 1 << (ebit), \
Dmt6397-regulator.c59 .enable_mask = BIT(0), \
82 .enable_mask = BIT(enbit), \
98 .enable_mask = BIT(enbit), \
Dact8865-regulator.c189 .enable_mask = ACT8865_ENA, \
208 .enable_mask = ACT8865_ENA,
223 .enable_mask = ACT8865_ENA,
234 .enable_mask = ACT8600_LDO10_ENA,
Dtps65090-regulator.c104 rdev->desc->enable_mask, in tps65090_try_enable_fet()
105 rdev->desc->enable_mask); in tps65090_try_enable_fet()
161 rdev->desc->enable_mask, 0); in tps65090_fet_enable()
205 .enable_mask = _en_bits, \
Dtps65023-regulator.c255 tps->desc[i].enable_mask = 1 << 1; in tps_65023_probe()
260 tps->desc[i].enable_mask = 1 << 2; in tps_65023_probe()
263 tps->desc[i].enable_mask = in tps_65023_probe()
Dlp8788-buck.c383 .enable_mask = LP8788_EN_BUCK1_M,
394 .enable_mask = LP8788_EN_BUCK2_M,
407 .enable_mask = LP8788_EN_BUCK3_M,
420 .enable_mask = LP8788_EN_BUCK4_M,
Darizona-micsupp.c137 .enable_mask = ARIZONA_CPMIC_ENA,
164 .enable_mask = ARIZONA_CPMIC_ENA,
Dpfuze100-regulator.c173 .enable_mask = 0x10, \
208 .enable_mask = 0x48, \
226 .enable_mask = 0x10, \
245 .enable_mask = 0x10, \
Dsky81452-regulator.c65 .enable_mask = SKY81452_LEN,
Dstw481x-vmmc.c50 .enable_mask = STW_CONF1_PDN_VMMC,
Dpalmas-regulator.c904 desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE; in palmas_ldo_registration()
930 desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE; in palmas_ldo_registration()
1016 desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE; in tps65917_ldo_registration()
1031 desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE; in tps65917_ldo_registration()
1165 desc->enable_mask = SMPS10_SWITCH_EN; in palmas_smps_registration()
1167 desc->enable_mask = SMPS10_BOOST_EN; in palmas_smps_registration()
1213 desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; in palmas_smps_registration()
1320 desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; in tps65917_smps_registration()
Drn5t618-regulator.c44 .enable_mask = (emask), \
Dpcf50633-regulator.c41 .enable_mask = PCF50633_REGULATOR_ON, \
D88pm800.c109 .enable_mask = 1 << (ebit), \
135 .enable_mask = 1 << (ebit), \
Dmax8907-regulator.c63 .enable_mask = MAX8907_MASK_LDO_EN, \
89 .enable_mask = MAX8907_MASK_OUT5V_EN, \
Dwm831x-dcdc.c498 dcdc->desc.enable_mask = 1 << id; in wm831x_buckv_probe()
650 dcdc->desc.enable_mask = 1 << id; in wm831x_buckp_probe()
768 dcdc->desc.enable_mask = 1 << id; in wm831x_boostp_probe()
851 dcdc->desc.enable_mask = 1 << dcdc->desc.id; in wm831x_epe_probe()
Dwm831x-ldo.c266 ldo->desc.enable_mask = 1 << id; in wm831x_gp_ldo_probe()
477 ldo->desc.enable_mask = 1 << id; in wm831x_aldo_probe()
619 ldo->desc.enable_mask = 1 << id; in wm831x_alive_ldo_probe()
Dda9052-regulator.c305 .enable_mask = 1 << (ebits),\
325 .enable_mask = 1 << (ebits),\
Dbcm590xx-regulator.c419 pmu->desc[i].enable_mask = BCM590XX_VBUS_ENABLE; in bcm590xx_probe()
423 pmu->desc[i].enable_mask = BCM590XX_REG_ENABLE; in bcm590xx_probe()
Dda9210-regulator.c80 .enable_mask = DA9210_BUCK_EN,
Drc5t583-regulator.c94 .enable_mask = BIT(_en_bit), \
Dmax8649.c142 .enable_mask = MAX8649_EN_PD,
Dtps6586x-regulator.c124 .enable_mask = 1 << (ebit0), \
149 .enable_mask = 1 << (ebit0), \
Dda9055-regulator.c376 .enable_mask = 1, \
404 .enable_mask = 1,\
Dfan53555.c288 rdesc->enable_mask = VSEL_BUCK_EN; in fan53555_regulator_register()
Dda9063-regulator.c67 .desc.enable_mask = DA9063_LDO_EN, \
88 .desc.enable_mask = DA9063_BUCK_EN, \
Dmax8973-regulator.c405 max->desc.enable_mask = MAX8973_VOUT_ENABLE; in max8973_probe()
Dda9211-regulator.c230 .enable_mask = DA9211_BUCKA_EN,\
Dlp8755.c313 .enable_mask = LP8755_BUCK_EN_M,\
Dltc3589.c217 .enable_mask = (en_bit), \
Ds5m8767.c943 regulators[id].enable_mask = S5M8767_ENCTRL_MASK; in s5m8767_pmic_probe()
Dtps65910-regulator.c1191 pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED; in tps65910_probe()
/linux-4.1.27/drivers/acpi/acpica/
Dhwgpe.c58 acpi_hw_gpe_enable_write(u8 enable_mask,
102 u32 enable_mask; in acpi_hw_low_set_gpe() local
116 status = acpi_hw_read(&enable_mask, &gpe_register_info->enable_address); in acpi_hw_low_set_gpe()
129 if (!(register_bit & gpe_register_info->enable_mask)) { in acpi_hw_low_set_gpe()
137 ACPI_SET_BIT(enable_mask, register_bit); in acpi_hw_low_set_gpe()
142 ACPI_CLEAR_BIT(enable_mask, register_bit); in acpi_hw_low_set_gpe()
153 status = acpi_hw_write(enable_mask, &gpe_register_info->enable_address); in acpi_hw_low_set_gpe()
294 acpi_hw_gpe_enable_write(u8 enable_mask, in acpi_hw_gpe_enable_write() argument
299 gpe_register_info->enable_mask = enable_mask; in acpi_hw_gpe_enable_write()
300 status = acpi_hw_write(enable_mask, &gpe_register_info->enable_address); in acpi_hw_gpe_enable_write()
Devgpe.c95 gpe_register_info->enable_mask = gpe_register_info->enable_for_run; in acpi_ev_update_gpe_enable_mask()
Daclocal.h458 u8 enable_mask; /* Current mask of enabled GPEs */ member
/linux-4.1.27/drivers/clk/mmp/
Dclk-apmu.c26 u32 enable_mask; member
39 data = readl_relaxed(apmu->base) | apmu->enable_mask; in clk_apmu_enable()
57 data = readl_relaxed(apmu->base) & ~apmu->enable_mask; in clk_apmu_disable()
70 void __iomem *base, u32 enable_mask, spinlock_t *lock) in mmp_clk_register_apmu() argument
87 apmu->enable_mask = enable_mask; in mmp_clk_register_apmu()
Dclk.h133 const char *parent_name, void __iomem *base, u32 enable_mask,
/linux-4.1.27/drivers/tty/
Dsysrq.c97 .enable_mask = SYSRQ_ENABLE_LOG,
110 .enable_mask = SYSRQ_ENABLE_KEYBOARD,
126 .enable_mask = SYSRQ_ENABLE_KEYBOARD,
144 .enable_mask = SYSRQ_ENABLE_DUMP,
157 .enable_mask = SYSRQ_ENABLE_BOOT,
168 .enable_mask = SYSRQ_ENABLE_SYNC,
190 .enable_mask = SYSRQ_ENABLE_REMOUNT,
254 .enable_mask = SYSRQ_ENABLE_DUMP,
269 .enable_mask = SYSRQ_ENABLE_DUMP,
281 .enable_mask = SYSRQ_ENABLE_DUMP,
[all …]
/linux-4.1.27/drivers/clk/ti/
Dapll.c61 v &= ~ad->enable_mask; in dra7_apll_enable()
62 v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask); in dra7_apll_enable()
100 v &= ~ad->enable_mask; in dra7_apll_disable()
101 v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask); in dra7_apll_disable()
114 v &= ad->enable_mask; in dra7_apll_is_enabled()
116 v >>= __ffs(ad->enable_mask); in dra7_apll_is_enabled()
210 ad->enable_mask = 0x3; in of_dra7_apll_setup()
233 v &= ad->enable_mask; in omap2_apll_is_enabled()
235 v >>= __ffs(ad->enable_mask); in omap2_apll_is_enabled()
259 v &= ~ad->enable_mask; in omap2_apll_enable()
[all …]
Ddpll.c243 dd->enable_mask = dpll->enable_mask; in ti_clk_register_dpll()
454 .enable_mask = 0x7, in of_ti_omap3_dpll_setup()
474 .enable_mask = 0x7, in of_ti_omap3_core_dpll_setup()
493 .enable_mask = 0x7 << 16, in of_ti_omap3_per_dpll_setup()
513 .enable_mask = 0x7 << 16, in of_ti_omap3_per_jtype_dpll_setup()
536 .enable_mask = 0x7, in of_ti_omap4_dpll_setup()
555 .enable_mask = 0x7, in of_ti_omap5_mpu_dpll_setup()
576 .enable_mask = 0x7, in of_ti_omap4_core_dpll_setup()
597 .enable_mask = 0x7, in of_ti_omap4_m4xen_dpll_setup()
618 .enable_mask = 0x7, in of_ti_omap4_jtype_dpll_setup()
[all …]
Dclock.h143 u32 enable_mask; member
Dclk-3xxx-legacy.c142 .enable_mask = 0x7,
314 .enable_mask = 0x70000,
515 .enable_mask = 0x7,
1280 .enable_mask = 0x7,
2164 .enable_mask = 0x7,
2524 .enable_mask = 0x70000,
/linux-4.1.27/drivers/clocksource/
Dtime-armada-370-xp.c80 static u32 enable_mask; variable
120 local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask); in armada_370_xp_clkevt_next_event()
139 local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask); in armada_370_xp_clkevt_mode()
260 enable_mask = TIMER0_EN; in armada_370_xp_timer_common_init()
263 enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT); in armada_370_xp_timer_common_init()
284 TIMER0_RELOAD_EN | enable_mask, in armada_370_xp_timer_common_init()
285 TIMER0_RELOAD_EN | enable_mask); in armada_370_xp_timer_common_init()
/linux-4.1.27/drivers/clk/
Dclk-palmas.c37 unsigned int enable_mask; member
70 cinfo->clk_desc->enable_mask, in palmas_clks_prepare()
71 cinfo->clk_desc->enable_mask); in palmas_clks_prepare()
95 cinfo->clk_desc->enable_mask, 0); in palmas_clks_unprepare()
117 return !!(val & cinfo->clk_desc->enable_mask); in palmas_clks_is_prepared()
141 .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
157 .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
/linux-4.1.27/include/linux/
Dsysrq.h35 int enable_mask; member
51 int sysrq_toggle_support(int enable_mask);
/linux-4.1.27/arch/arm/mach-omap2/
Ddpll3xxx.c51 v &= ~dd->enable_mask; in _omap3_dpll_write_clken()
52 v |= clken_bits << __ffs(dd->enable_mask); in _omap3_dpll_write_clken()
754 WARN_ON(!dd->enable_mask); in omap3_clkoutx2_recalc()
756 v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask; in omap3_clkoutx2_recalc()
757 v >>= __ffs(dd->enable_mask); in omap3_clkoutx2_recalc()
794 WARN_ON(!dd->enable_mask); in omap3_clkoutx2_round_rate()
796 v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask; in omap3_clkoutx2_round_rate()
797 v >>= __ffs(dd->enable_mask); in omap3_clkoutx2_round_rate()
Dclkt_dpll.c215 v &= dd->enable_mask; in omap2_init_dpll_parent()
216 v >>= __ffs(dd->enable_mask); in omap2_init_dpll_parent()
251 v &= dd->enable_mask; in omap2_get_dpll_rate()
252 v >>= __ffs(dd->enable_mask); in omap2_get_dpll_rate()
Ddisplay.c115 u32 enable_mask, enable_shift; in omap4_dsi_mux_pads() local
120 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; in omap4_dsi_mux_pads()
125 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; in omap4_dsi_mux_pads()
135 reg &= ~enable_mask; in omap4_dsi_mux_pads()
138 reg |= (lanes << enable_shift) & enable_mask; in omap4_dsi_mux_pads()
/linux-4.1.27/drivers/gpu/drm/radeon/
Devergreen_hdmi.c39 u8 enable_mask) in dce4_audio_enable() argument
46 if (enable_mask) { in dce4_audio_enable()
48 if (enable_mask & 1) in dce4_audio_enable()
50 if (enable_mask & 2) in dce4_audio_enable()
52 if (enable_mask & 4) in dce4_audio_enable()
54 if (enable_mask & 8) in dce4_audio_enable()
Dr600_hdmi.c143 u8 enable_mask) in r600_audio_enable() argument
150 if (enable_mask) { in r600_audio_enable()
152 if (enable_mask & 1) in r600_audio_enable()
154 if (enable_mask & 2) in r600_audio_enable()
156 if (enable_mask & 4) in r600_audio_enable()
158 if (enable_mask & 8) in r600_audio_enable()
Dkv_smc.c54 int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask) in kv_dpm_get_enable_mask() argument
61 *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0); in kv_dpm_get_enable_mask()
Dkv_dpm.h66 u32 enable_mask; member
189 int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);
Dradeon_audio.c33 u8 enable_mask);
35 u8 enable_mask);
37 u8 enable_mask);
246 struct r600_audio_pin *pin, u8 enable_mask) in radeon_audio_enable() argument
266 if ((pin_count > 1) && (enable_mask == 0)) in radeon_audio_enable()
271 rdev->audio.funcs->enable(rdev, pin, enable_mask); in radeon_audio_enable()
Ddce6_afmt.c240 u8 enable_mask) in dce6_audio_enable() argument
246 enable_mask ? AUDIO_ENABLED : 0); in dce6_audio_enable()
Dradeon_audio.h41 struct r600_audio_pin *pin, u8 enable_mask);
Dkv_dpm.c274 local_cac_reg->enable_mask);
2042 u32 enable_mask, i; in kv_force_dpm_highest() local
2044 ret = kv_dpm_get_enable_mask(rdev, &enable_mask); in kv_force_dpm_highest()
2049 if (enable_mask & (1 << i)) in kv_force_dpm_highest()
2062 u32 enable_mask, i; in kv_force_dpm_lowest() local
2064 ret = kv_dpm_get_enable_mask(rdev, &enable_mask); in kv_force_dpm_lowest()
2069 if (enable_mask & (1 << i)) in kv_force_dpm_lowest()
Dradeon.h3048 u8 enable_mask);
3051 u8 enable_mask);
/linux-4.1.27/drivers/gpu/drm/i915/
Di915_irq.c367 u32 enable_mask, u32 status_mask) in __i915_enable_pipestat() argument
375 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || in __i915_enable_pipestat()
378 pipe_name(pipe), enable_mask, status_mask)) in __i915_enable_pipestat()
381 if ((pipestat & enable_mask) == enable_mask) in __i915_enable_pipestat()
387 pipestat |= enable_mask | status_mask; in __i915_enable_pipestat()
394 u32 enable_mask, u32 status_mask) in __i915_disable_pipestat() argument
402 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || in __i915_disable_pipestat()
405 pipe_name(pipe), enable_mask, status_mask)) in __i915_disable_pipestat()
408 if ((pipestat & enable_mask) == 0) in __i915_disable_pipestat()
413 pipestat &= ~enable_mask; in __i915_disable_pipestat()
[all …]
/linux-4.1.27/drivers/iio/imu/
Dadis16480.c440 unsigned int enable_mask, offset, reg; in adis16480_get_filter_freq() local
446 enable_mask = BIT(offset + 2); in adis16480_get_filter_freq()
452 if (!(val & enable_mask)) in adis16480_get_filter_freq()
464 unsigned int enable_mask, offset, reg; in adis16480_set_filter_freq() local
472 enable_mask = BIT(offset + 2); in adis16480_set_filter_freq()
479 val &= ~enable_mask; in adis16480_set_filter_freq()
495 val |= enable_mask; in adis16480_set_filter_freq()
/linux-4.1.27/kernel/power/
Dpoweroff.c37 .enable_mask = SYSRQ_ENABLE_BOOT,
/linux-4.1.27/arch/x86/kernel/cpu/
Dperf_event_amd_ibs.c49 u64 enable_mask; member
340 wrmsrl(hwc->config_base, hwc->config | config | perf_ibs->enable_mask); in perf_ibs_enable_event()
355 config &= ~perf_ibs->enable_mask; in perf_ibs_disable_event()
482 .enable_mask = IBS_FETCH_ENABLE,
506 .enable_mask = IBS_OP_ENABLE,
Dperf_event.h719 u64 enable_mask) in __x86_pmu_enable_event() argument
725 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); in __x86_pmu_enable_event()
/linux-4.1.27/drivers/clk/mvebu/
Dclk-corediv.c81 u32 enable_mask = BIT(desc->fieldbit) << soc_desc->enable_bit_offset; in clk_corediv_is_enabled() local
83 return !!(readl(corediv->reg) & enable_mask); in clk_corediv_is_enabled()
/linux-4.1.27/drivers/gpu/drm/via/
Dvia_irq.c288 cur_irq->enable_mask = dev_priv->irq_masks[i][0]; in via_driver_irq_preinstall()
291 dev_priv->irq_enable_mask |= cur_irq->enable_mask; in via_driver_irq_preinstall()
Dvia_drv.h58 uint32_t enable_mask; member
/linux-4.1.27/include/linux/regulator/
Ddriver.h294 unsigned int enable_mask; member
/linux-4.1.27/include/linux/clk/
Dti.h75 u32 enable_mask; member
/linux-4.1.27/drivers/net/ethernet/via/
Dvia-rhine.c830 u16 enable_mask = RHINE_EVENT & 0xffff; in rhine_napipoll() local
861 enable_mask &= ~RHINE_EVENT_SLOW; in rhine_napipoll()
867 iowrite16(enable_mask, ioaddr + IntrEnable); in rhine_napipoll()
/linux-4.1.27/drivers/net/ethernet/realtek/
Dr8169.c7470 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow; in rtl8169_poll() local
7484 enable_mask &= ~tp->event_slow; in rtl8169_poll()
7492 rtl_irq_enable(tp, enable_mask); in rtl8169_poll()
/linux-4.1.27/drivers/isdn/hardware/eicon/
Dmessage.c9590 static void dtmf_enable_receiver(PLCI *plci, byte enable_mask) in dtmf_enable_receiver() argument
9596 (char *)(FILE_), __LINE__, enable_mask)); in dtmf_enable_receiver()
9598 if (enable_mask != 0) in dtmf_enable_receiver()