Lines Matching refs:enable_mask
36 u32 enable_mask; member
57 .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
64 .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
71 .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
92 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
98 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
113 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
120 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
128 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
136 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
144 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
149 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
154 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
159 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
164 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
169 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
174 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
179 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
184 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
189 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
194 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
199 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
249 v |= clk->enable_mask; in __clk_enable()
280 v &= ~clk->enable_mask; in __clk_disable()
340 div_bit = clk->enable_mask >> 15; in set_keytchclk_rate()