Searched refs:divisor (Results 1 - 200 of 439) sorted by relevance

123

/linux-4.1.27/include/linux/
H A Dmath64.h13 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
18 static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder) div_u64_rem() argument
20 *remainder = dividend % divisor; div_u64_rem()
21 return dividend / divisor; div_u64_rem()
25 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
27 static inline s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder) div_s64_rem() argument
29 *remainder = dividend % divisor; div_s64_rem()
30 return dividend / divisor; div_s64_rem()
34 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
36 static inline u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder) div64_u64_rem() argument
38 *remainder = dividend % divisor; div64_u64_rem()
39 return dividend / divisor; div64_u64_rem()
43 * div64_u64 - unsigned 64bit divide with 64bit divisor
45 static inline u64 div64_u64(u64 dividend, u64 divisor) div64_u64() argument
47 return dividend / divisor; div64_u64()
51 * div64_s64 - signed 64bit divide with 64bit divisor
53 static inline s64 div64_s64(s64 dividend, s64 divisor) div64_s64() argument
55 return dividend / divisor; div64_s64()
64 static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder) div_u64_rem() argument
66 *remainder = do_div(dividend, divisor); div_u64_rem()
72 extern s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder);
76 extern u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder);
80 extern u64 div64_u64(u64 dividend, u64 divisor);
84 extern s64 div64_s64(s64 dividend, s64 divisor);
90 * div_u64 - unsigned 64bit divide with 32bit divisor
97 static inline u64 div_u64(u64 dividend, u32 divisor) div_u64() argument
100 return div_u64_rem(dividend, divisor, &remainder); div_u64()
105 * div_s64 - signed 64bit divide with 32bit divisor
108 static inline s64 div_s64(s64 dividend, s32 divisor) div_s64() argument
111 return div_s64_rem(dividend, divisor, &remainder); div_s64()
115 u32 iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder);
118 __iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder) __iter_div_u64_rem() argument
122 while (dividend >= divisor) { __iter_div_u64_rem()
127 dividend -= divisor; __iter_div_u64_rem()
H A Dmpi.h104 ulong mpi_fdiv_r_ui(MPI rem, MPI dividend, ulong divisor);
105 int mpi_fdiv_r(MPI rem, MPI dividend, MPI divisor);
106 int mpi_fdiv_q(MPI quot, MPI dividend, MPI divisor);
107 int mpi_fdiv_qr(MPI quot, MPI rem, MPI dividend, MPI divisor);
111 int mpi_divisible_ui(const MPI dividend, ulong divisor);
H A Dreciprocal_div.h15 * This optimization for A/B is helpful if the divisor B is mostly
H A Dvlynq.h57 enum vlynq_divisor divisor; member in struct:vlynq_device_id
66 enum vlynq_divisor divisor; member in struct:vlynq_device
H A Dkernel.h92 * Divide positive or negative dividend by positive divisor and round
94 * for negative dividends if the divisor variable type is unsigned.
96 #define DIV_ROUND_CLOSEST(x, divisor)( \
99 typeof(divisor) __d = divisor; \
101 ((typeof(divisor))-1) > 0 || (__x) > 0) ? \
107 * Same as above but for u64 dividends. divisor must be a 32-bit
110 #define DIV_ROUND_CLOSEST_ULL(x, divisor)( \
112 typeof(divisor) __d = divisor; \
H A Dclocksource.h56 * @shift: cycle to nanosecond divisor (power of two)
170 * @shift: cycle to nanosecond divisor (power of two)
H A Dtimecounter.h37 * @shift: cycle to nanosecond divisor (power of two)
/linux-4.1.27/lib/
H A Ddiv64.c62 s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder) div_s64_rem() argument
67 quotient = div_u64_rem(-dividend, abs(divisor), (u32 *)remainder); div_s64_rem()
69 if (divisor > 0) div_s64_rem()
72 quotient = div_u64_rem(dividend, abs(divisor), (u32 *)remainder); div_s64_rem()
73 if (divisor < 0) div_s64_rem()
82 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
84 * @divisor: 64bit divisor
93 u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder) div64_u64_rem() argument
95 u32 high = divisor >> 32; div64_u64_rem()
100 quot = div_u64_rem(dividend, divisor, &rem32); div64_u64_rem()
104 quot = div_u64(dividend >> n, divisor >> n); div64_u64_rem()
109 *remainder = dividend - quot * divisor; div64_u64_rem()
110 if (*remainder >= divisor) { div64_u64_rem()
112 *remainder -= divisor; div64_u64_rem()
122 * div64_u64 - unsigned 64bit divide with 64bit divisor
124 * @divisor: 64bit divisor
133 u64 div64_u64(u64 dividend, u64 divisor) div64_u64() argument
135 u32 high = divisor >> 32; div64_u64()
139 quot = div_u64(dividend, divisor); div64_u64()
142 quot = div_u64(dividend >> n, divisor >> n); div64_u64()
146 if ((dividend - quot * divisor) >= divisor) div64_u64()
156 * div64_s64 - signed 64bit divide with 64bit divisor
158 * @divisor: 64bit divisor
161 s64 div64_s64(s64 dividend, s64 divisor) div64_s64() argument
165 quot = div64_u64(abs64(dividend), abs64(divisor)); div64_s64()
166 t = (dividend ^ divisor) >> 63; div64_s64()
177 * bigger than divisor.
179 u32 iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder) iter_div_u64_rem() argument
181 return __iter_div_u64_rem(dividend, divisor, remainder); iter_div_u64_rem()
H A Dgcd.c5 /* Greatest common divisor */ gcd()
H A Dstring_helpers.c42 static const unsigned int divisor[] = { string_get_size() local
61 * coefficient * divisor[units]^i string_get_size()
71 do_div(blk_size, divisor[units]); string_get_size()
76 do_div(size, divisor[units]); string_get_size()
84 /* and logarithmically reduce it until it's just under the divisor */ string_get_size()
85 while (size >= divisor[units]) { string_get_size()
86 remainder = do_div(size, divisor[units]); string_get_size()
99 * divisor[units], which is 1 << 10 for STRING_UNITS_2 */ string_get_size()
/linux-4.1.27/arch/m68k/include/asm/
H A Dmcfpit.h24 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
25 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK128 0x0700 /* System clock divisor */
32 #define MCFPIT_PCSR_CLK256 0x0800 /* System clock divisor */
33 #define MCFPIT_PCSR_CLK512 0x0900 /* System clock divisor */
34 #define MCFPIT_PCSR_CLK1024 0x0a00 /* System clock divisor */
35 #define MCFPIT_PCSR_CLK2048 0x0b00 /* System clock divisor */
36 #define MCFPIT_PCSR_CLK4096 0x0c00 /* System clock divisor */
37 #define MCFPIT_PCSR_CLK8192 0x0d00 /* System clock divisor */
38 #define MCFPIT_PCSR_CLK16384 0x0e00 /* System clock divisor */
39 #define MCFPIT_PCSR_CLK32768 0x0f00 /* System clock divisor */
/linux-4.1.27/arch/arm/lib/
H A Dlib1funcs.S40 .macro ARM_DIV_BODY dividend, divisor, result, curbit
44 clz \curbit, \divisor
48 mov \divisor, \divisor, lsl \result
54 @ Initially shift the divisor left 3 bits if possible,
58 tst \divisor, #0xe0000000
59 moveq \divisor, \divisor, lsl #3
63 @ Unless the divisor is very big, shift it up in multiples of
65 @ division loop. Continue shifting until the divisor is
67 1: cmp \divisor, #0x10000000
68 cmplo \divisor, \dividend
69 movlo \divisor, \divisor, lsl #4
75 1: cmp \divisor, #0x80000000
76 cmplo \divisor, \dividend
77 movlo \divisor, \divisor, lsl #1
86 1: cmp \dividend, \divisor
87 subhs \dividend, \dividend, \divisor
89 cmp \dividend, \divisor, lsr #1
90 subhs \dividend, \dividend, \divisor, lsr #1
92 cmp \dividend, \divisor, lsr #2
93 subhs \dividend, \dividend, \divisor, lsr #2
95 cmp \dividend, \divisor, lsr #3
96 subhs \dividend, \dividend, \divisor, lsr #3
100 movne \divisor, \divisor, lsr #4
106 .macro ARM_DIV2_ORDER divisor, order
110 clz \order, \divisor
115 cmp \divisor, #(1 << 16)
116 movhs \divisor, \divisor, lsr #16
120 cmp \divisor, #(1 << 8)
121 movhs \divisor, \divisor, lsr #8
124 cmp \divisor, #(1 << 4)
125 movhs \divisor, \divisor, lsr #4
128 cmp \divisor, #(1 << 2)
130 addls \order, \order, \divisor, lsr #1
137 .macro ARM_MOD_BODY dividend, divisor, order, spare
141 clz \order, \divisor
144 mov \divisor, \divisor, lsl \order
150 @ Unless the divisor is very big, shift it up in multiples of
152 @ division loop. Continue shifting until the divisor is
154 1: cmp \divisor, #0x10000000
155 cmplo \divisor, \dividend
156 movlo \divisor, \divisor, lsl #4
162 1: cmp \divisor, #0x80000000
163 cmplo \divisor, \dividend
164 movlo \divisor, \divisor, lsl #1
175 1: cmp \dividend, \divisor
176 subhs \dividend, \dividend, \divisor
177 cmp \dividend, \divisor, lsr #1
178 subhs \dividend, \dividend, \divisor, lsr #1
179 cmp \dividend, \divisor, lsr #2
180 subhs \dividend, \dividend, \divisor, lsr #2
181 cmp \dividend, \divisor, lsr #3
182 subhs \dividend, \dividend, \divisor, lsr #3
184 mov \divisor, \divisor, lsr #4
196 cmp \dividend, \divisor
197 subhs \dividend, \dividend, \divisor
198 mov \divisor, \divisor, lsr #1
199 3: cmp \dividend, \divisor
200 subhs \dividend, \dividend, \divisor
201 mov \divisor, \divisor, lsr #1
202 4: cmp \dividend, \divisor
203 subhs \dividend, \dividend, \divisor
241 subs r2, r1, #1 @ compare divisor with 1
243 cmpne r0, r1 @ compare dividend with divisor
245 tsthi r1, r2 @ see if divisor is power of 2
270 tst r1, r2 @ divisor is power of 2 ?
307 subs r2, r1, #1 @ compare divisor with 1
308 cmpne r0, r1 @ compare dividend with divisor
310 tsthi r1, r2 @ see if divisor is power of 2
H A Ddiv64.S4 * Optimized computation of 64-bit dividend / 32-bit divisor
32 * __do_div64: perform a division with 64-bit dividend and 32-bit divisor.
39 * r4 = divisor (preserved)
53 bls 9f @ divisor is 0 or 1
55 beq 8f @ divisor is power of 2
62 @ Align divisor with upper part of dividend.
63 @ The aligned divisor is stored in yl preserving the original.
105 @ divisor for comparisons, considering the carry-out bit as well.
142 @ divisor at this point since divisor can not be smaller than 3 here.
150 8: @ Division by a power of 2: determine what that divisor order is
/linux-4.1.27/arch/metag/include/asm/
H A Ddiv64.h6 extern u64 div_u64(u64 dividend, u64 divisor);
7 extern s64 div_s64(s64 dividend, s64 divisor);
/linux-4.1.27/arch/x86/include/asm/
H A Ddiv64.h42 static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder) div_u64_rem() argument
52 if (upper >= divisor) { div_u64_rem()
53 d.v32[1] = upper / divisor; div_u64_rem()
54 upper %= divisor; div_u64_rem()
57 "rm" (divisor), "0" (d.v32[0]), "1" (upper)); div_u64_rem()
/linux-4.1.27/arch/alpha/lib/
H A Ddivide.S28 * the divisor is small is handled better by the DEC algorithm
37 * $1 - shifted divisor
42 * $25 - divisor
54 #define divisor $1 define
102 bis $25,$25,divisor
107 LONGIFY(divisor)
112 beq divisor, 9f /* div by zero */
116 * shift divisor left, using 3-bit shifts for
123 1: cmpult divisor,modulus,compare
124 s8addq divisor,$31,divisor
128 1: cmpult divisor,modulus,compare
129 blt divisor, 2f
130 addq divisor,divisor,divisor
139 cmpule divisor,modulus,compare
140 subq modulus,divisor,tmp1
142 srl divisor,1,divisor
H A Dev6-divide.S28 * the divisor is small is handled better by the DEC algorithm
37 * $1 - shifted divisor
42 * $25 - divisor
64 #define divisor $1 define
112 bis $25,$25,divisor # E :
118 LONGIFY(divisor) # E : U L L U
125 beq divisor, 9f /* div by zero */
135 * shift divisor left, using 3-bit shifts for
142 1: cmpult divisor,modulus,compare # E :
143 s8addq divisor,$31,divisor # E :
147 1: cmpult divisor,modulus,compare # E :
150 blt divisor, 2f # U : U L U L
152 addq divisor,divisor,divisor # E :
170 cmpule divisor,modulus,compare # E :
171 subq modulus,divisor,tmp1 # E :
176 srl divisor,1,divisor # U :
184 srl divisor,1,divisor # U :
/linux-4.1.27/drivers/acpi/acpica/
H A Dutmath.c77 * divisor - 32-bit divisor
91 u32 divisor, u64 *out_quotient, u32 *out_remainder) acpi_ut_short_divide()
99 /* Always check for a zero divisor */ acpi_ut_short_divide()
101 if (divisor == 0) { acpi_ut_short_divide()
112 ACPI_DIV_64_BY_32(0, dividend_ovl.part.hi, divisor, acpi_ut_short_divide()
114 ACPI_DIV_64_BY_32(remainder32, dividend_ovl.part.lo, divisor, acpi_ut_short_divide()
149 union uint64_overlay divisor; acpi_ut_divide() local
160 /* Always check for a zero divisor */ acpi_ut_divide()
167 divisor.full = in_divisor; acpi_ut_divide()
169 if (divisor.part.hi == 0) { acpi_ut_divide()
171 * 1) Simplest case is where the divisor is 32 bits, we can acpi_ut_divide()
180 ACPI_DIV_64_BY_32(0, dividend.part.hi, divisor.part.lo, acpi_ut_divide()
182 ACPI_DIV_64_BY_32(partial1, dividend.part.lo, divisor.part.lo, acpi_ut_divide()
188 * 2) The general case where the divisor is a full 64 bits acpi_ut_divide()
193 normalized_divisor = divisor; acpi_ut_divide()
195 /* Normalize the operands (shift until the divisor is < 32 bits) */ acpi_ut_divide()
216 partial1 = quotient.part.lo * divisor.part.hi; acpi_ut_divide()
217 partial2.full = (u64) quotient.part.lo * divisor.part.lo; acpi_ut_divide()
228 remainder.full -= divisor.full; acpi_ut_divide()
232 remainder.full -= divisor.full; acpi_ut_divide()
275 u32 divisor, u64 *out_quotient, u32 *out_remainder)
280 /* Always check for a zero divisor */
282 if (divisor == 0) {
290 *out_quotient = in_dividend / divisor;
293 *out_remainder = (u32) (in_dividend % divisor);
305 /* Always check for a zero divisor */
90 acpi_ut_short_divide(u64 dividend, u32 divisor, u64 *out_quotient, u32 *out_remainder) acpi_ut_short_divide() argument
/linux-4.1.27/arch/tile/lib/
H A Dexports.c67 uint32_t __udivsi3(uint32_t dividend, uint32_t divisor);
69 int32_t __divsi3(int32_t dividend, int32_t divisor);
71 uint64_t __udivdi3(uint64_t dividend, uint64_t divisor);
73 int64_t __divdi3(int64_t dividend, int64_t divisor);
75 uint32_t __umodsi3(uint32_t dividend, uint32_t divisor);
77 int32_t __modsi3(int32_t dividend, int32_t divisor);
79 uint64_t __umoddi3(uint64_t dividend, uint64_t divisor);
81 int64_t __moddi3(int64_t dividend, int64_t divisor);
/linux-4.1.27/arch/c6x/kernel/
H A Dc6x_ksyms.c19 extern int __c6xabi_divi(int dividend, int divisor);
22 extern unsigned __c6xabi_divu(unsigned dividend, unsigned divisor);
25 extern int __c6xabi_remi(int dividend, int divisor);
28 extern unsigned __c6xabi_remu(unsigned dividend, unsigned divisor);
31 extern int __c6xabi_divremi(int dividend, int divisor);
34 extern unsigned __c6xabi_divremu(unsigned dividend, unsigned divisor);
/linux-4.1.27/drivers/cpufreq/
H A Dsparc-us2e-cpufreq.c87 unsigned long old_divisor, unsigned long divisor) frob_mem_refresh()
92 refr_count /= (MCTRL0_REFR_CLKS_P_CNT * divisor * 1000000000UL); frob_mem_refresh()
119 unsigned long old_divisor, unsigned long divisor) us2e_transition()
128 if (old_divisor == 2 && divisor == 1) { us2e_transition()
131 frob_mem_refresh(0, clock_tick, old_divisor, divisor); us2e_transition()
132 } else if (old_divisor == 1 && divisor == 2) { us2e_transition()
133 frob_mem_refresh(1, clock_tick, old_divisor, divisor); us2e_transition()
136 } else if (old_divisor == 1 && divisor > 2) { us2e_transition()
140 2, divisor); us2e_transition()
141 } else if (old_divisor > 2 && divisor == 1) { us2e_transition()
145 2, divisor); us2e_transition()
146 } else if (old_divisor < divisor) { us2e_transition()
147 frob_mem_refresh(0, clock_tick, old_divisor, divisor); us2e_transition()
149 } else if (old_divisor > divisor) { us2e_transition()
151 frob_mem_refresh(1, clock_tick, old_divisor, divisor); us2e_transition()
252 unsigned long clock_tick, divisor, old_divisor, estar; us2e_freq_target() local
260 divisor = index_to_divisor(index); us2e_freq_target()
261 new_freq /= divisor; us2e_freq_target()
267 if (old_divisor != divisor) us2e_freq_target()
269 old_divisor, divisor); us2e_freq_target()
85 frob_mem_refresh(int cpu_slowing_down, unsigned long clock_tick, unsigned long old_divisor, unsigned long divisor) frob_mem_refresh() argument
117 us2e_transition(unsigned long estar, unsigned long new_bits, unsigned long clock_tick, unsigned long old_divisor, unsigned long divisor) us2e_transition() argument
/linux-4.1.27/arch/arm/common/
H A Dicst.c33 u32 divisor = (vco.r + 2) * p->s2div[vco.s]; icst_hz() local
35 do_div(dividend, divisor); icst_hz()
42 * Ascending divisor S values.
57 * First, find the PLL output divisor such icst_hz_to_vco()
74 * Now find the closest divisor combination icst_hz_to_vco()
/linux-4.1.27/sound/soc/codecs/
H A Dtlv320aic26.c69 int fsref, divisor, wlen, pval, jval, dval, qval; aic26_hw_params() local
78 case 8000: fsref = 48000; divisor = AIC26_DIV_6; break; aic26_hw_params()
79 case 11025: fsref = 44100; divisor = AIC26_DIV_4; break; aic26_hw_params()
80 case 12000: fsref = 48000; divisor = AIC26_DIV_4; break; aic26_hw_params()
81 case 16000: fsref = 48000; divisor = AIC26_DIV_3; break; aic26_hw_params()
82 case 22050: fsref = 44100; divisor = AIC26_DIV_2; break; aic26_hw_params()
83 case 24000: fsref = 48000; divisor = AIC26_DIV_2; break; aic26_hw_params()
84 case 32000: fsref = 48000; divisor = AIC26_DIV_1_5; break; aic26_hw_params()
85 case 44100: fsref = 44100; divisor = AIC26_DIV_1; break; aic26_hw_params()
86 case 48000: fsref = 48000; divisor = AIC26_DIV_1; break; aic26_hw_params()
126 /* Audio Control 1 (FSref divisor) */ aic26_hw_params()
127 reg = wlen | aic26->datfm | (divisor << 3) | divisor; aic26_hw_params()
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Dcomedi_8254.h68 * @divisor: divisor for single counter
69 * @divisor1: divisor loaded into first cascaded counter
70 * @divisor2: divisor loaded into second cascaded counter
71 * #next_div: next divisor for single counter
72 * @next_div1: next divisor to use for first cascaded counter
73 * @next_div2: next divisor to use for second cascaded counter
85 unsigned int divisor; member in struct:comedi_8254
H A Dcomedi_8254.c87 * Calculates the divisor value needed for a single counter to generate
91 * Calculates the two divisor values needed to the generate the pacer
95 * Transfers the intermediate divisor values to the current divisors.
99 * divisor values.
309 * @counter1: the counter number for the first divisor
310 * @counter2: the counter number for the second divisor
350 i8254->divisor = i8254->next_div & 0xffff; comedi_8254_update_divisors()
357 * comedi_8254_cascade_ns_to_timer - calculate the cascaded divisor values
442 * comedi_8254_ns_to_timer - calculate the divisor value for nanosec timing
450 unsigned int divisor; comedi_8254_ns_to_timer() local
455 divisor = DIV_ROUND_CLOSEST(*nanosec, i8254->osc_base); comedi_8254_ns_to_timer()
458 divisor = DIV_ROUND_UP(*nanosec, i8254->osc_base); comedi_8254_ns_to_timer()
461 divisor = *nanosec / i8254->osc_base; comedi_8254_ns_to_timer()
464 if (divisor < 2) comedi_8254_ns_to_timer()
465 divisor = 2; comedi_8254_ns_to_timer()
466 if (divisor > I8254_MAX_COUNT) comedi_8254_ns_to_timer()
467 divisor = I8254_MAX_COUNT; comedi_8254_ns_to_timer()
469 *nanosec = divisor * i8254->osc_base; comedi_8254_ns_to_timer()
470 i8254->next_div = divisor; comedi_8254_ns_to_timer()
H A Daddi_apci_3120.c283 unsigned int divisor; apci3120_ns_to_timer() local
287 divisor = DIV_ROUND_UP(ns, timer_base); apci3120_ns_to_timer()
290 divisor = ns / timer_base; apci3120_ns_to_timer()
294 divisor = DIV_ROUND_CLOSEST(ns, timer_base); apci3120_ns_to_timer()
300 if (divisor > 0x00ffffff) apci3120_ns_to_timer()
301 divisor = 0x00ffffff; apci3120_ns_to_timer()
304 if (divisor > 0xffff) apci3120_ns_to_timer()
305 divisor = 0xffff; apci3120_ns_to_timer()
307 /* the timers require a minimum divisor of 2 */ apci3120_ns_to_timer()
308 if (divisor < 2) apci3120_ns_to_timer()
309 divisor = 2; apci3120_ns_to_timer()
311 return divisor; apci3120_ns_to_timer()
553 unsigned int divisor; apci3120_ai_cmd() local
575 divisor = apci3120_ns_to_timer(dev, 1, cmd->scan_begin_arg, apci3120_ai_cmd()
578 apci3120_timer_write(dev, 1, divisor); apci3120_ai_cmd()
585 divisor = apci3120_ns_to_timer(dev, 0, cmd->convert_arg, cmd->flags); apci3120_ai_cmd()
587 apci3120_timer_write(dev, 0, divisor); apci3120_ai_cmd()
721 unsigned int divisor; apci3120_ai_insn_read() local
736 * when the divisor is written to the timer, The conversion is done apci3120_ai_insn_read()
743 divisor = apci3120_ns_to_timer(dev, 0, 10000, CMDF_ROUND_NEAREST); apci3120_ai_insn_read()
747 apci3120_timer_write(dev, 0, divisor); apci3120_ai_insn_read()
834 unsigned int divisor; apci3120_timer_insn_config() local
842 divisor = apci3120_ns_to_timer(dev, 2, data[1], apci3120_timer_insn_config()
844 apci3120_timer_write(dev, 2, divisor); apci3120_timer_insn_config()
H A Dcb_pcidas64.c62 * to configure the divisor to use for the external clock.
1113 /* master clock divisor to use for scans with external master clock */
1114 unsigned int divisor; member in struct:ext_clock_info
1911 unsigned int divisor = data[4]; ai_config_master_clock_4020() local
1914 if (divisor < 2) { ai_config_master_clock_4020()
1915 divisor = 2; ai_config_master_clock_4020()
1921 devpriv->ext_clock.divisor = divisor; ai_config_master_clock_4020()
1928 data[4] = divisor; ai_config_master_clock_4020()
1967 * take into account possible minimum/maximum divisor values. Used
1971 unsigned int divisor; get_divisor() local
1975 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE; get_divisor()
1978 divisor = ns / TIMER_BASE; get_divisor()
1982 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE; get_divisor()
1985 return divisor; get_divisor()
2249 /* supposed to load counter with desired divisor minus 3 */ ai_convert_counter_6xxx()
2278 unsigned int divisor; ai_convert_counter_4020() local
2282 divisor = cmd->scan_begin_arg / TIMER_BASE; ai_convert_counter_4020()
2285 divisor = devpriv->ext_clock.divisor; ai_convert_counter_4020()
2289 divisor = 1000; ai_convert_counter_4020()
2293 /* supposed to load counter with desired divisor minus 2 for 4020 */ ai_convert_counter_4020()
2294 return divisor - 2; ai_convert_counter_4020()
3168 unsigned int divisor; set_dac_interval_regs() local
3173 divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags); set_dac_interval_regs()
3174 if (divisor > max_counter_value) { set_dac_interval_regs()
3175 dev_err(dev->class_dev, "bug! ao divisor too big\n"); set_dac_interval_regs()
3176 divisor = max_counter_value; set_dac_interval_regs()
3178 writew(divisor & 0xffff, set_dac_interval_regs()
3180 writew((divisor >> 16) & 0xff, set_dac_interval_regs()
H A Ddt2811.c148 543 divisor freqency (kHz)
158 210 multiply divisor/divide frequency by
H A Dni_stc.h1191 static inline unsigned MSeries_PLL_Divisor_Bits(unsigned divisor) MSeries_PLL_Divisor_Bits() argument
1194 if (divisor < 1 || divisor > max_divisor) { MSeries_PLL_Divisor_Bits()
1195 pr_err("%s: bug, invalid divisor=%i\n", __func__, divisor); MSeries_PLL_Divisor_Bits()
1198 return (divisor & 0xf) << 8; MSeries_PLL_Divisor_Bits()
H A Ddt282x.c304 unsigned int divisor; member in struct:dt282x_private
708 devpriv->divisor = dt282x_ns_to_timer(&arg, cmd->flags); dt282x_ai_cmdtest()
726 outw(devpriv->divisor, dev->iobase + DT2821_TMRCTR_REG); dt282x_ai_cmd()
871 devpriv->divisor = dt282x_ns_to_timer(&arg, cmd->flags); dt282x_ao_cmdtest()
926 outw(devpriv->divisor, dev->iobase + DT2821_TMRCTR_REG); dt282x_ao_cmd()
/linux-4.1.27/arch/blackfin/lib/
H A Dumodsi3.S39 R0 *= R6; /* Quotient * divisor */
40 R0 = R7 - R0; /* Dividend - (quotient * divisor) */
H A Dudivsi3.S34 We know we have a 31-bit dividend, and 15-bit divisor so we can use the
89 R3 = R1 >> 1; /* Pre-scaled divisor for primitive case */
92 R2 = R3 - R2; /* shifted divisor < upper 16 bits of dividend */
155 /* If AQ==0, we'll sub divisor */
169 IF !CC R1 = P2; /* if 2, restore stored divisor */
172 R3 *= R1; /* Q * divisor */
173 R5 = R0 - R3; /* Z = (dividend - Q * divisor) */
174 CC = R1 <= R5 (IU); /* Check if divisor <= Z? */
225 divisor > 0x7FFFF.
228 Secondly we need to shift both the divisor and dividend 1 to the right so
255 To divide by a divisor > 0x7FFF,
257 2. multiply quotient by unscaled divisor (result M)
259 4. if E < divisor (Y) subtract 1, if E > divisor (Y) add 1, else return quotient (Q)
H A Dmodsi3.S46 R0 *= R6; /* Quotient * divisor */
47 R0 = R7 - R0; /* Dividend - (quotient * divisor) */
H A Ddivsi3.S128 /* we might be subtracting divisor (AQ==0) */
129 IF CC R5 = R1; /* or we might be adding divisor (AQ==1)*/
/linux-4.1.27/arch/powerpc/boot/
H A Dvirtex.c32 u16 divisor; virtex_ns16550_console_init() local
55 divisor = clk / (16 * spd); virtex_ns16550_console_init()
61 out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF); virtex_ns16550_console_init()
62 out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8); virtex_ns16550_console_init()
H A Ddiv64.S6 * the 64-bit quotient, and r4 contains the divisor.
26 divwu r7,r5,r4 # if dividend.hi >= divisor,
27 mullw r0,r7,r4 # quotient.hi = dividend.hi / divisor
28 subf. r5,r0,r5 # dividend.hi %= divisor
35 srw r10,r10,r0 # the divisor right the same amount,
45 mulhwu r9,r11,r4 # multiply the estimate by the divisor,
46 subfc r6,r10,r6 # take the product from the divisor,
H A Dcuboot-acadia.c49 unsigned long div; /* total divisor udiv * bdiv */ get_clocks()
130 div = plloutb / (16 * baud); /* total divisor */ get_clocks()
131 umin = (plloutb / freqOPB) << 1; /* 2 x OPB divisor */ get_clocks()
/linux-4.1.27/arch/arm/mach-orion5x/
H A Dtsx09-common.c30 /* 19200 baud divisor */ qnap_tsx09_power_off()
31 const unsigned divisor = ((orion5x_tclk + (8 * 19200)) / (16 * 19200)); qnap_tsx09_power_off() local
37 writel(divisor & 0xff, UART1_REG(DLL)); qnap_tsx09_power_off()
38 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); qnap_tsx09_power_off()
H A Dkurobox_pro-setup.c294 /* 38400 baud divisor */ kurobox_pro_power_off()
295 const unsigned divisor = ((orion5x_tclk + (8 * 38400)) / (16 * 38400)); kurobox_pro_power_off() local
301 writel(divisor & 0xff, UART1_REG(DLL)); kurobox_pro_power_off()
302 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); kurobox_pro_power_off()
H A Dterastation_pro2-setup.c273 /* 38400 baud divisor */ tsp2_power_off()
274 const unsigned divisor = ((orion5x_tclk + (8 * 38400)) / (16 * 38400)); tsp2_power_off() local
280 writel(divisor & 0xff, UART1_REG(DLL)); tsp2_power_off()
281 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); tsp2_power_off()
/linux-4.1.27/include/asm-generic/
H A Dcputime_nsecs.h28 #define cputime_div(__ct, divisor) div_u64((__force u64)__ct, divisor)
29 #define cputime_div_rem(__ct, divisor, remainder) \
30 div_u64_rem((__force u64)__ct, divisor, remainder);
H A Ddiv64.h35 extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
/linux-4.1.27/arch/x86/kernel/
H A Dearly_printk.c131 static __init void early_serial_hw_init(unsigned divisor) early_serial_hw_init() argument
142 serial_out(early_serial_base, DLL, divisor & 0xff); early_serial_hw_init()
143 serial_out(early_serial_base, DLH, (divisor >> 8) & 0xff); early_serial_hw_init()
151 unsigned divisor; early_serial_init() local
182 /* Convert from baud to divisor value */ early_serial_init()
183 divisor = 115200 / baud; early_serial_init()
190 early_serial_hw_init(divisor); early_serial_init()
217 unsigned divisor; early_pci_serial_init() local
302 /* Convert from baud to divisor value */ early_pci_serial_init()
303 divisor = 115200 / baud; early_pci_serial_init()
306 early_serial_hw_init(divisor); early_pci_serial_init()
/linux-4.1.27/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-jtag.c50 uint32_t divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000); cvmx_helper_qlm_jtag_init() local
51 divisor = (divisor - 1) >> 2; cvmx_helper_qlm_jtag_init()
52 /* Convert the divisor into a power of 2 shift */ cvmx_helper_qlm_jtag_init()
53 while (divisor) { cvmx_helper_qlm_jtag_init()
55 divisor = divisor >> 1; cvmx_helper_qlm_jtag_init()
/linux-4.1.27/drivers/clk/
H A Dclk-vt8500.c133 /* div == 0 is actually the highest divisor */ vt8500_dclk_recalc_rate()
144 u32 divisor; vt8500_dclk_round_rate() local
149 divisor = *prate / rate; vt8500_dclk_round_rate()
151 /* If prate / rate would be decimal, incr the divisor */ vt8500_dclk_round_rate()
152 if (rate * divisor < *prate) vt8500_dclk_round_rate()
153 divisor++; vt8500_dclk_round_rate()
156 * If this is a request for SDMMC we have to adjust the divisor vt8500_dclk_round_rate()
159 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { vt8500_dclk_round_rate()
160 divisor = 64 * ((divisor / 64) + 1); vt8500_dclk_round_rate()
163 return *prate / divisor; vt8500_dclk_round_rate()
170 u32 divisor; vt8500_dclk_set_rate() local
176 divisor = parent_rate / rate; vt8500_dclk_set_rate()
178 if (divisor == cdev->div_mask + 1) vt8500_dclk_set_rate()
179 divisor = 0; vt8500_dclk_set_rate()
182 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { vt8500_dclk_set_rate()
184 * Bit 5 is a fixed /64 predivisor. If the requested divisor vt8500_dclk_set_rate()
185 * is >31 then correct for the fixed divisor being required. vt8500_dclk_set_rate()
187 divisor = 0x20 + (divisor / 64); vt8500_dclk_set_rate()
190 if (divisor > cdev->div_mask) { vt8500_dclk_set_rate()
191 pr_err("%s: invalid divisor for clock\n", __func__); vt8500_dclk_set_rate()
198 writel(divisor, cdev->div_reg); vt8500_dclk_set_rate()
264 rc = of_property_read_u32(node, "divisor-reg", &div_reg); vtwm_device_clk_init()
273 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); vtwm_device_clk_init()
427 /* calculate frequency (MHz) after pre-divisor */ wm8750_get_filter()
/linux-4.1.27/arch/sh/lib/
H A Dudivsi3_i4i-Os.S33 udiv small divisor: 55 cycles
34 udiv large divisor: 52 cycles
35 sdiv small divisor, positive result: 59 cycles
36 sdiv large divisor, positive result: 56 cycles
37 sdiv small divisor, negative result: 65 cycles (*)
38 sdiv large divisor, negative result: 62 cycles (*)
/linux-4.1.27/arch/x86/boot/
H A Dearly_serial_console.c24 unsigned divisor; early_serial_init() local
31 divisor = 115200 / baud; early_serial_init()
34 outb(divisor & 0xff, port + DLL); early_serial_init()
35 outb((divisor >> 8) & 0xff, port + DLH); early_serial_init()
/linux-4.1.27/drivers/power/reset/
H A Dqnap-poweroff.c60 const unsigned divisor = ((tclk + (8 * cfg->baud)) / (16 * cfg->baud)); qnap_power_off() local
66 writel(divisor & 0xff, UART1_REG(DLL)); qnap_power_off()
67 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); qnap_power_off()
100 /* We need to know tclk in order to calculate the UART divisor */ qnap_power_off_probe()
/linux-4.1.27/arch/sh/kernel/cpu/sh4/
H A Dclock-sh4-202.c33 int divisor = clk->parent->rate / rate; frqcr3_lookup() local
37 if (frqcr3_divisors[i] == divisor) frqcr3_lookup()
82 int divisor = frqcr3_divisors[i]; shoc_clk_init() local
84 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) shoc_clk_init()
/linux-4.1.27/drivers/clk/sunxi/
H A Dclk-sun6i-apb0.c17 * The APB0 clk has a configurable divisor.
20 * divisor here, because the first 2 values divide the clock
H A Dclk-sun6i-ar100.c72 * - one power of 2 divisor ar100_determine_rate()
73 * - one regular divisor ar100_determine_rate()
85 * Then if the divisor is still bigger than what the HW ar100_determine_rate()
/linux-4.1.27/drivers/video/fbdev/via/
H A Dvia_clock.h42 u8 divisor; member in struct:via_pll_config
65 return ref_freq / pll.divisor * pll.multiplier; get_pll_internal_frequency()
H A Dvia_clock.c40 | pll.divisor; cle266_encode_pll()
45 return ((pll.divisor - 2) << 16) k800_encode_pll()
52 return (pll.divisor << 16) vx855_encode_pll()
/linux-4.1.27/arch/m68k/lib/
H A Dudivsi3.S91 movel sp@(12), d1 /* d1 = divisor */
94 cmpl IMM (0x10000), d1 /* divisor >= 2 ^ 16 ? */
107 L3: movel d1, d2 /* use d2 as divisor backup */
108 L4: lsrl IMM (1), d1 /* shift divisor */
110 cmpl IMM (0x10000), d1 /* still divisor >= 2 ^ 16 ? */
112 divu d1, d0 /* now we have 16 bit divisor */
113 andl IMM (0xffff), d0 /* mask out divisor, ignore remainder */
115 /* Multiply the 16 bit tentative quotient with the 32 bit divisor. Because of
H A Ddivsi3.S92 movel sp@(12), d1 /* d1 = divisor */
96 negb d2 /* change sign because divisor <0 */
98 negl d2 /* change sign because divisor <0 */
111 jbsr SYM (__udivsi3) /* divide abs(dividend) by abs(divisor) */
H A Dmodsi3.S89 movel sp@(8), d1 /* d1 = divisor */
95 movel sp@(8), d1 /* d1 = divisor */
H A Dumodsi3.S89 movel sp@(8), d1 /* d1 = divisor */
95 movel sp@(8), d1 /* d1 = divisor */
/linux-4.1.27/drivers/usb/serial/
H A Dftdi_sio.h130 * For the FT232BM, a 17th divisor bit was introduced to encode the multiples
134 * 000 - add .000 to divisor
135 * 001 - add .500 to divisor
136 * 010 - add .250 to divisor
137 * 011 - add .125 to divisor
138 * 100 - add .375 to divisor
139 * 101 - add .625 to divisor
140 * 110 - add .750 to divisor
141 * 111 - add .875 to divisor
142 * Bits 15 to 0 of the 17-bit divisor are placed in the urb value. Bit 16 is
146 * rates. If the calculated divisor value is 1, this needs to be replaced with
147 * 0. Additionally for the FT232BM, if the calculated divisor value is 0x4001
148 * (1.5), this needs to be replaced with 0x0001 (1) (but this divisor value is
178 * The ftdi_8U232AM_xxMHz_byyy constants have been removed. The encoded divisor
H A Doti6858.c79 __le16 divisor; /* baud rate = 96000000 / (16 * divisor), LE */ member in struct:oti6858_control_pkt
117 (((a)->divisor == (priv)->pending_setup.divisor) \
181 __le16 divisor; member in struct:oti6858_private::__anon10444
228 new_setup->divisor = priv->pending_setup.divisor; setup_line()
409 __le16 divisor; oti6858_set_termios() local
415 divisor = priv->pending_setup.divisor; oti6858_set_termios()
444 divisor = 0; oti6858_set_termios()
452 divisor = cpu_to_le16(new_divisor); oti6858_set_termios()
494 if (divisor != priv->pending_setup.divisor oti6858_set_termios()
497 priv->pending_setup.divisor = divisor; oti6858_set_termios()
527 buf->divisor = cpu_to_le16(0x009c); /* 38400 bps */ oti6858_open()
538 priv->pending_setup.divisor = buf->divisor; oti6858_open()
H A Dftdi_sio.c57 int baud_base; /* baud base clock for divisor setting */
1108 unsigned short int divisor; ftdi_232am_baud_base_to_divisor() local
1109 /* divisor shifted 3 bits to the left */ ftdi_232am_baud_base_to_divisor()
1113 divisor = divisor3 >> 3; ftdi_232am_baud_base_to_divisor()
1116 divisor |= 0xc000; ftdi_232am_baud_base_to_divisor()
1118 divisor |= 0x4000; ftdi_232am_baud_base_to_divisor()
1120 divisor |= 0x8000; ftdi_232am_baud_base_to_divisor()
1121 else if (divisor == 1) ftdi_232am_baud_base_to_divisor()
1122 divisor = 0; /* special case for maximum baud rate */ ftdi_232am_baud_base_to_divisor()
1123 return divisor; ftdi_232am_baud_base_to_divisor()
1134 __u32 divisor; ftdi_232bm_baud_base_to_divisor() local
1135 /* divisor shifted 3 bits to the left */ ftdi_232bm_baud_base_to_divisor()
1137 divisor = divisor3 >> 3; ftdi_232bm_baud_base_to_divisor()
1138 divisor |= (__u32)divfrac[divisor3 & 0x7] << 14; ftdi_232bm_baud_base_to_divisor()
1140 if (divisor == 1) ftdi_232bm_baud_base_to_divisor()
1141 divisor = 0; ftdi_232bm_baud_base_to_divisor()
1142 else if (divisor == 0x4001) ftdi_232bm_baud_base_to_divisor()
1143 divisor = 1; ftdi_232bm_baud_base_to_divisor()
1144 return divisor; ftdi_232bm_baud_base_to_divisor()
1155 __u32 divisor; ftdi_2232h_baud_base_to_divisor() local
1161 divisor = divisor3 >> 3; ftdi_2232h_baud_base_to_divisor()
1162 divisor |= (__u32)divfrac[divisor3 & 0x7] << 14; ftdi_2232h_baud_base_to_divisor()
1164 if (divisor == 1) ftdi_2232h_baud_base_to_divisor()
1165 divisor = 0; ftdi_2232h_baud_base_to_divisor()
1166 else if (divisor == 0x4001) ftdi_2232h_baud_base_to_divisor()
1167 divisor = 1; ftdi_2232h_baud_base_to_divisor()
1173 divisor |= 0x00020000; ftdi_2232h_baud_base_to_divisor()
1174 return divisor; ftdi_2232h_baud_base_to_divisor()
1255 * 3. You can also set baud rate by setting custom divisor as follows get_ftdi_divisor()
1280 dev_dbg(dev, "%s - custom divisor %d sets baud rate to %d\n", get_ftdi_divisor()
1284 /* 3. Convert baudrate to device-specific divisor */ get_ftdi_divisor()
1360 dev_dbg(dev, "%s - Baud rate set to %d (divisor 0x%lX) on chip %s\n", get_ftdi_divisor()
H A Dssu100.c206 u16 baud, divisor, remainder; ssu100_set_termios() local
241 divisor = MAX_BAUD_RATE / baud; ssu100_set_termios()
244 divisor++; ssu100_set_termios()
248 result = ssu100_control_msg(dev, QT_GET_SET_UART, divisor, urb_value); ssu100_set_termios()
H A Dch341.c128 short divisor; ch341_set_baudrate() local
133 divisor = CH341_BAUDBASE_DIVMAX; ch341_set_baudrate()
135 while ((factor > 0xfff0) && divisor) { ch341_set_baudrate()
137 divisor--; ch341_set_baudrate()
144 a = (factor & 0xff00) | divisor; ch341_set_baudrate()
H A Dquatech2.c152 int divisor, rem; calc_baud_divisor() local
154 divisor = MAX_BAUD_RATE / baudrate; calc_baud_divisor()
156 /* Round to nearest divisor */ calc_baud_divisor()
158 divisor++; calc_baud_divisor()
160 return divisor; calc_baud_divisor()
167 int divisor = calc_baud_divisor(baudrate); qt2_set_port_config() local
172 divisor, index, NULL, 0, QT2_USB_TIMEOUT); qt2_set_port_config()
H A Dmos7840.c62 #define LCR_DL_ENABLE 0x80 /* Enable access to divisor latch */
1552 * this function calculates the proper baud rate divisor for the specified
1556 int baudRate, int *divisor, mos7840_calc_baud_rate_divisor()
1562 *divisor = 115200 / baudRate; mos7840_calc_baud_rate_divisor()
1566 *divisor = 230400 / baudRate; mos7840_calc_baud_rate_divisor()
1569 *divisor = 403200 / baudRate; mos7840_calc_baud_rate_divisor()
1572 *divisor = 460800 / baudRate; mos7840_calc_baud_rate_divisor()
1575 *divisor = 806400 / baudRate; mos7840_calc_baud_rate_divisor()
1578 *divisor = 921600 / baudRate; mos7840_calc_baud_rate_divisor()
1581 *divisor = 1572864 / baudRate; mos7840_calc_baud_rate_divisor()
1584 *divisor = 3145728 / baudRate; mos7840_calc_baud_rate_divisor()
1599 int divisor = 0; mos7840_send_cmd_write_baud_rate() local
1652 status = mos7840_calc_baud_rate_divisor(port, baudRate, &divisor, mos7840_send_cmd_write_baud_rate()
1673 /* Enable access to divisor latch */ mos7840_send_cmd_write_baud_rate()
1678 /* Write the divisor */ mos7840_send_cmd_write_baud_rate()
1679 Data = (unsigned char)(divisor & 0xff); mos7840_send_cmd_write_baud_rate()
1683 Data = (unsigned char)((divisor & 0xff00) >> 8); mos7840_send_cmd_write_baud_rate()
1687 /* Disable access to divisor latch */ mos7840_send_cmd_write_baud_rate()
1829 /* Determine divisor based on baud rate */ mos7840_change_port_settings()
1555 mos7840_calc_baud_rate_divisor(struct usb_serial_port *port, int baudRate, int *divisor, __u16 *clk_sel_val) mos7840_calc_baud_rate_divisor() argument
H A Df81232.c352 int divisor; f81232_set_baudrate() local
355 divisor = calc_baud_divisor(baudrate); f81232_set_baudrate()
374 divisor & 0x00ff); /* low */ f81232_set_baudrate()
382 (divisor & 0xff00) >> 8); /* high */ f81232_set_baudrate()
H A Dmos7720.c1391 __u16 divisor; member in struct:divisor_table_entry
1418 * this function calculates the proper baud rate divisor for the specified
1421 static int calc_baud_rate_divisor(struct usb_serial_port *port, int baudrate, int *divisor) calc_baud_rate_divisor() argument
1433 *divisor = divisor_table[i].divisor; calc_baud_rate_divisor()
1439 * Try calculating the divisor for this baud rate */ calc_baud_rate_divisor()
1441 /* get the divisor */ calc_baud_rate_divisor()
1449 *divisor = custom; calc_baud_rate_divisor()
1469 int divisor; send_cmd_write_baud_rate() local
1483 status = calc_baud_rate_divisor(port, baudrate, &divisor); send_cmd_write_baud_rate()
1489 /* Enable access to divisor latch */ send_cmd_write_baud_rate()
1493 /* Write the divisor */ send_cmd_write_baud_rate()
1494 write_mos_reg(serial, number, DLL, (__u8)(divisor & 0xff)); send_cmd_write_baud_rate()
1495 write_mos_reg(serial, number, DLM, (__u8)((divisor & 0xff00) >> 8)); send_cmd_write_baud_rate()
1497 /* Disable access to divisor latch */ send_cmd_write_baud_rate()
1631 /* Determine divisor based on baud rate */ change_port_settings()
H A Dkeyspan_usa90msg.h58 baudLo, // host does baud divisor calculation
59 baudHi, // host does baud divisor calculation
H A Dmct_u232.c181 unsigned int divisor; mct_u232_set_baud_rate() local
191 divisor = mct_u232_calculate_baud_rate(serial, value, &speed); mct_u232_set_baud_rate()
192 put_unaligned_le32(cpu_to_le32(divisor), buf); mct_u232_set_baud_rate()
203 dev_dbg(&port->dev, "set_baud_rate: value: 0x%x, divisor: 0x%x\n", value, divisor); mct_u232_set_baud_rate()
H A Dmct_u232.h86 * Baud rate (divisor)
166 * Baud rate (divisor)
174 * Data: divisor = 115200 / baud_rate
181 * use a baud-rate code instead of a conventional RS-232 baud rate divisor.
343 * occurs immediately after a "Baud rate (divisor)" message. It was not
H A Dkeyspan.c167 /* FIXME - calculate exact rate from divisor ? */ keyspan_set_termios()
1368 div, /* divisor */ keyspan_usa19_calc_baud()
1369 cnt; /* inverse of divisor (programmed into 8051) */ keyspan_usa19_calc_baud()
1378 as we run out of divisor resolution. */ keyspan_usa19_calc_baud()
1382 /* calculate the divisor and the counter (its inverse) */ keyspan_usa19_calc_baud()
1409 div; /* divisor */ keyspan_usa19hs_calc_baud()
1418 /* calculate the divisor */ keyspan_usa19hs_calc_baud()
1446 div, /* divisor using 13/8 prescaler */ keyspan_usa19w_calc_baud()
1491 /* return the divisor and prescaler if non-null */ keyspan_usa19w_calc_baud()
1509 div, /* divisor */ keyspan_usa28_calc_baud()
1510 cnt; /* inverse of divisor (programmed into 8051) */ keyspan_usa28_calc_baud()
1519 /* calculate the divisor and the counter (its inverse) */ keyspan_usa28_calc_baud()
H A Dio_edgeport.c235 static int calc_baud_rate_divisor(struct device *dev, int baud_rate, int *divisor);
2239 int divisor; send_cmd_write_baud_rate() local
2252 status = calc_baud_rate_divisor(dev, baudRate, &divisor); send_cmd_write_baud_rate()
2265 /* Enable access to divisor latch */ send_cmd_write_baud_rate()
2268 /* Write the divisor itself */ send_cmd_write_baud_rate()
2269 MAKE_CMD_WRITE_REG(&currCmd, &cmdLen, number, DLL, LOW8(divisor)); send_cmd_write_baud_rate()
2270 MAKE_CMD_WRITE_REG(&currCmd, &cmdLen, number, DLM, HIGH8(divisor)); send_cmd_write_baud_rate()
2272 /* Restore original value to disable access to divisor latch */ send_cmd_write_baud_rate()
2288 * this function calculates the proper baud rate divisor for the specified
2291 static int calc_baud_rate_divisor(struct device *dev, int baudrate, int *divisor) calc_baud_rate_divisor() argument
2298 *divisor = divisor_table[i].Divisor; calc_baud_rate_divisor()
2304 * lets try to calculate the divisor for this baud rate calc_baud_rate_divisor()
2307 /* get divisor */ calc_baud_rate_divisor()
2310 *divisor = custom; calc_baud_rate_divisor()
2528 /* Determine divisor based on baud rate */ change_port_settings()
/linux-4.1.27/arch/powerpc/kernel/
H A Dudbg_16550.c130 unsigned int dll, dlm, divisor, prescaler, speed; udbg_probe_uart_speed() local
135 /* select divisor latch registers. */ udbg_probe_uart_speed()
138 /* now, read the divisor */ udbg_probe_uart_speed()
141 divisor = dlm << 8 | dll; udbg_probe_uart_speed()
153 speed = (clock / prescaler) / (divisor * 16); udbg_probe_uart_speed()
H A Dtime.c1074 * Divide a 128-bit dividend by a 32-bit divisor, leaving a 128 bit
1078 unsigned divisor, struct div_result *dr) div128_by_32()
1089 w = a / divisor; div128_by_32()
1090 ra = ((u64)(a - (w * divisor)) << 32) + b; div128_by_32()
1092 rb = ((u64) do_div(ra, divisor) << 32) + c; div128_by_32()
1095 rc = ((u64) do_div(rb, divisor) << 32) + d; div128_by_32()
1098 do_div(rc, divisor); div128_by_32()
1077 div128_by_32(u64 dividend_high, u64 dividend_low, unsigned divisor, struct div_result *dr) div128_by_32() argument
/linux-4.1.27/arch/arm/mach-omap2/
H A Dclkt_clksel.c114 * value to search for, find the corresponding clock divisor. The register
116 * before calling. Returns 0 on error or returns the actual integer divisor
151 * _divisor_to_clksel() - turn clksel integer divisor into a field value
153 * @div: integer divisor to search for
156 * divisor, find the corresponding register field value. Returns the
183 pr_err("clock: %s: could not find divisor %d for parent %s\n", _divisor_to_clksel()
193 * _read_divisor() - get current divisor applied to parent clock (from hdwr)
196 * Read the current divisor register value for @clk that is programmed
197 * into the hardware, convert it into the actual divisor value, and
217 * omap2_clksel_round_rate_div() - find divisor for the given clock and rate
220 * @new_div: ptr to where we should store the divisor
274 pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n", omap2_clksel_round_rate_div()
354 * and its current divisor setting in the hardware.
H A Dmsdi.c47 /* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
H A Dclock.h134 * @div: clock divisor corresponding to @val
140 * @div is the divisor that should be applied to the parent clock's rate
/linux-4.1.27/net/sched/
H A Dsch_sfq.c120 unsigned int divisor; /* number of slots in hash table */ member in struct:sfq_sched_data
129 sfq_index *ht; /* Hash table ('divisor' slots) */
182 return hash & (q->divisor - 1); sfq_hash()
195 TC_H_MIN(skb->priority) <= q->divisor) sfq_classify()
216 if (TC_H_MIN(res.classid) <= q->divisor) sfq_classify()
651 if (ctl->divisor && sfq_change()
652 (!is_power_of_2(ctl->divisor) || ctl->divisor > 65536)) sfq_change()
667 if (ctl->divisor) { sfq_change()
668 q->divisor = ctl->divisor; sfq_change()
669 q->maxflows = min_t(u32, q->maxflows, q->divisor); sfq_change()
750 q->divisor = SFQ_DEFAULT_HASH_DIVISOR; sfq_init()
763 q->ht = sfq_alloc(sizeof(q->ht[0]) * q->divisor); sfq_init()
769 for (i = 0; i < q->divisor; i++) sfq_init()
794 opt.v0.divisor = q->divisor; sfq_dump()
887 for (i = 0; i < q->divisor; i++) { sfq_walk()
H A Dcls_flow.c56 u32 divisor; member in struct:flow_filter
314 if (f->divisor) flow_classify()
315 classid %= f->divisor; flow_classify()
440 fnew->divisor = fold->divisor; flow_change()
513 fnew->divisor = nla_get_u32(tb[TCA_FLOW_DIVISOR]); flow_change()
620 if (f->divisor && flow_dump()
621 nla_put_u32(skb, TCA_FLOW_DIVISOR, f->divisor)) flow_dump()
H A Dcls_u32.c80 unsigned int divisor; member in struct:tc_u_hnode
200 if (ht->divisor) { u32_classify()
207 sel = ht->divisor & u32_hash_fold(*data, &n->sel, u32_classify()
273 if (sel > ht->divisor) u32_lookup_key()
331 root_ht->divisor = 0; u32_init()
432 for (h = 0; h <= ht->divisor; h++) { u32_clear_hnode()
470 for (h = 0; h <= ht->divisor; h++) ht_empty()
776 unsigned int divisor = nla_get_u32(tb[TCA_U32_DIVISOR]); u32_change() local
778 if (--divisor > 0x100) u32_change()
787 ht = kzalloc(sizeof(*ht) + divisor*sizeof(void *), GFP_KERNEL); u32_change()
792 ht->divisor = divisor; u32_change()
816 if (ht->divisor < TC_U32_HASH(htid)) u32_change()
919 for (h = 0; h <= ht->divisor; h++) { u32_walk()
955 u32 divisor = ht->divisor + 1; u32_dump() local
957 if (nla_put_u32(skb, TCA_U32_DIVISOR, divisor)) u32_dump()
/linux-4.1.27/arch/m68k/ifpsp060/src/
H A Dilsp.S74 # 0x4(sp) = divisor #
89 # codes before performing the final "rts". If the divisor was equal to #
134 mov.l 0x8(%a6),%d7 # fetch divisor
136 beq.w ldiv64eq0 # divisor is = 0!!!
145 # save the sign of the divisor
146 # make divisor unsigned if it's negative
147 tst.l %d7 # chk sign of divisor
148 slt NDIVISOR(%a6) # save sign of divisor
150 neg.l %d7 # complement negative divisor
165 # - is (hi(dividend) == 0 && (divisor <= lo(dividend))) ? (32-bit div)
173 cmp.l %d7,%d6 # is (divisor <= lo(dividend))
186 # - is hi(dividend) >= divisor ? if yes, then overflow
272 # where U,V are words of the quadword dividend and longword divisor, #
276 # in %d6. The divisor must be in the variable ddivisor, and the #
283 # if the divisor msw is 0, use simpler algorithm then the full blown
289 # Since the divisor is only a word (and larger than the mslw of the dividend),
292 # dividing the divisor word into each dividend word. In this case,
320 # In this algorithm, the divisor is treated as a 2 digit (word) number
323 # process repeated. Before beginning, the divisor and quotient are
332 bne.b lddnormalized # divisor (V1) must be >= 65536/2
334 lsl.l &0x1, %d7 # shift the divisor
342 mov.l %d7, %d3 # divisor
387 # now test the word by multiplying it by the divisor (V1V2) and comparing
394 mov.l %d5, %d2 # now %d2,%d3 are trial*divisor
402 # need to add back divisor longword to current ms 3 digits of dividend
404 # divisor, dividend selection.
408 clr.w %d3 # %d3 now ls word of divisor
412 clr.w %d3 # %d3 now ms word of divisor
H A Disp.S2069 # codes. Set idbyz_flg in SPCOND_FLG if divisor was zero. Store the #
2094 mov.l (EXC_DREGS,%a6,%d0.w*4), %d7 # fetch divisor from register
2097 beq.w div64eq0 # divisor is = 0!!!
2115 # save the sign of the divisor
2116 # make divisor unsigned if it's negative
2117 tst.l %d7 # chk sign of divisor
2118 slt NDIVISOR(%a6) # save sign of divisor
2120 neg.l %d7 # complement negative divisor
2135 # - is (hi(dividend) == 0 && (divisor <= lo(dividend))) ? (32-bit div)
2143 cmp.l %d7,%d6 # is (divisor <= lo(dividend))
2156 # - is hi(dividend) >= divisor ? if yes, then overflow
2222 # where U,V are words of the quadword dividend and longword divisor, #
2226 # in %d6. The divisor must be in the variable ddivisor, and the #
2233 # if the divisor msw is 0, use simpler algorithm then the full blown
2239 # Since the divisor is only a word (and larger than the mslw of the dividend),
2242 # dividing the divisor word into each dividend word. In this case,
2270 # In this algorithm, the divisor is treated as a 2 digit (word) number
2273 # process repeated. Before beginning, the divisor and quotient are
2282 bne.b ddnormalized # divisor (V1) must be >= 65536/2
2284 lsl.l &0x1, %d7 # shift the divisor
2292 mov.l %d7, %d3 # divisor
2337 # now test the word by multiplying it by the divisor (V1V2) and comparing
2344 mov.l %d5, %d2 # now %d2,%d3 are trial*divisor
2352 # need to add back divisor longword to current ms 3 digits of dividend
2354 # divisor, dividend selection.
2358 clr.w %d3 # %d3 now ls word of divisor
2362 clr.w %d3 # %d3 now ms word of divisor
2437 bsr.l _dmem_read_long # fetch divisor from <ea>
/linux-4.1.27/arch/mips/ralink/
H A Dtimer.c77 static int rt_timer_config(struct rt_timer *rt, unsigned long divisor) rt_timer_config() argument
79 if (rt->timer_freq < divisor) rt_timer_config()
82 rt->timer_div = divisor; rt_timer_config()
/linux-4.1.27/arch/arm/mach-rpc/include/mach/
H A Dacornfb.h87 /* Select pixel-clock divisor to keep PLL in range */ acornfb_vidc20_find_rates()
90 /* Limit divisor */ acornfb_vidc20_find_rates()
96 /* Encode divisor to VIDC20 setting */ acornfb_vidc20_find_rates()
/linux-4.1.27/drivers/input/serio/
H A Dambakmi.c35 unsigned int divisor; member in struct:amba_kmi_port
71 unsigned int divisor; amba_kmi_open() local
78 divisor = clk_get_rate(kmi->clk) / 8000000 - 1; amba_kmi_open()
79 writeb(divisor, KMICLKDIV); amba_kmi_open()
/linux-4.1.27/drivers/tty/serial/8250/
H A D8250_early.c116 unsigned int divisor; init_port() local
126 divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * device->baud); init_port()
129 serial8250_early_out(port, UART_DLL, divisor & 0xff); init_port()
130 serial8250_early_out(port, UART_DLM, (divisor >> 8) & 0xff); init_port()
H A D8250.h209 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ ns16550a_goto_highspeed()
/linux-4.1.27/arch/avr32/include/asm/
H A Dtimex.h21 * - a divisor of the actual rate
/linux-4.1.27/arch/arm/mach-w90x900/include/mach/
H A Dregs-serial.h37 unsigned int divisor; member in struct:w90x900_uart_clksrc
/linux-4.1.27/sound/aoa/soundbus/i2sbus/
H A Dinterface.h63 * - MClk divisor
64 * - SClk divisor
82 * It is derived by taking only every 'divisor' tick of the clock.
110 * derived from the MClk above by taking only every 'divisor' tick
/linux-4.1.27/drivers/iio/common/hid-sensors/
H A Dhid-sensor-attributes.c73 static void simple_div(int dividend, int divisor, int *whole, simple_div() argument
80 if (divisor == 0) { simple_div()
84 *whole = dividend/divisor; simple_div()
85 rem = dividend % divisor; simple_div()
87 while (rem <= divisor) { simple_div()
91 *micro_frac = (rem / divisor) * pow_10(6-exp); simple_div()
/linux-4.1.27/drivers/media/tuners/
H A Dmax2165.c164 static int fixpt_div32(u32 dividend, u32 divisor, u32 *quotient, u32 *fraction) fixpt_div32() argument
170 if (0 == divisor) fixpt_div32()
173 q = dividend / divisor; fixpt_div32()
174 remainder = dividend - q * divisor; fixpt_div32()
178 if (remainder >= divisor) { fixpt_div32()
180 remainder -= divisor; fixpt_div32()
H A Dtda18271-fe.c577 s32 divisor, dividend; tda18271_rf_tracking_filters_init() local
623 divisor = (s32)(rf_freq[RF2] - rf_freq[RF1]) / 1000; tda18271_rf_tracking_filters_init()
624 map[i].rf_a1 = (dividend / divisor); tda18271_rf_tracking_filters_init()
630 divisor = (s32)(rf_freq[RF3] - rf_freq[RF2]) / 1000; tda18271_rf_tracking_filters_init()
631 map[i].rf_a2 = (dividend / divisor); tda18271_rf_tracking_filters_init()
/linux-4.1.27/drivers/mfd/
H A Dmcp-core.c56 * mcp_set_telecom_divisor - set the telecom divisor
58 * @div: SIB clock divisor
60 * Set the telecom divisor on the MCP interface. The resulting
74 * mcp_set_audio_divisor - set the audio divisor
76 * @div: SIB clock divisor
78 * Set the audio divisor on the MCP interface.
H A Dmcp-sa11x0.c48 mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor) mcp_sa11x0_set_telecom_divisor() argument
52 divisor /= 32; mcp_sa11x0_set_telecom_divisor()
55 m->mccr0 |= divisor << 8; mcp_sa11x0_set_telecom_divisor()
60 mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor) mcp_sa11x0_set_audio_divisor() argument
64 divisor /= 32; mcp_sa11x0_set_audio_divisor()
67 m->mccr0 |= divisor; mcp_sa11x0_set_audio_divisor()
/linux-4.1.27/drivers/clk/shmobile/
H A Dclk-div6.c29 * @div: divisor value (1-64)
62 * DIV6 clocks require the divisor field to be non-zero when stopping cpg_div6_clock_disable()
64 * re-enabled later if the divisor field is changed when stopping the cpg_div6_clock_disable()
118 /* Only program the new divisor if the clock isn't stopped. */ cpg_div6_clock_set_rate()
204 /* Remap the clock register and read the divisor. Disabling the cpg_div6_clock_init()
205 * clock overwrites the divisor, so we need to cache its value for the cpg_div6_clock_init()
/linux-4.1.27/drivers/vlynq/
H A Dvlynq.c331 vdev->divisor = ids->divisor; vlynq_device_match()
415 "%s: using remote clock divisor %d\n", __vlynq_try_remote()
417 dev->divisor = i; __vlynq_try_remote()
452 "%s: using local clock divisor %d\n", __vlynq_try_local()
454 dev->divisor = i; __vlynq_try_local()
487 dev->divisor = vlynq_div_external; __vlynq_try_external()
503 switch (dev->divisor) { __vlynq_enable_device()
532 VLYNQ_CTRL_CLOCK_DIV(dev->divisor - __vlynq_enable_device()
537 "%s: using local clock divisor %d\n", __vlynq_enable_device()
539 dev->divisor - vlynq_ldiv1 + 1); __vlynq_enable_device()
553 VLYNQ_CTRL_CLOCK_DIV(dev->divisor - __vlynq_enable_device()
557 "%s: using remote clock divisor %d\n", __vlynq_enable_device()
559 dev->divisor - vlynq_rdiv1 + 1); __vlynq_enable_device()
739 dev->divisor = vlynq_div_auto; vlynq_probe()
/linux-4.1.27/drivers/staging/sm750fb/
H A Dddk750_chip.c136 unsigned int ulReg, divisor; setMemoryClock() local
148 /* Calculate the divisor */ setMemoryClock()
149 divisor = (unsigned int) roundedDiv(getChipClock(), frequency); setMemoryClock()
151 /* Set the corresponding divisor in the register. */ setMemoryClock()
153 switch (divisor) { setMemoryClock()
184 unsigned int ulReg, divisor; setMasterClock() local
196 /* Calculate the divisor */ setMasterClock()
197 divisor = (unsigned int) roundedDiv(getChipClock(), frequency); setMasterClock()
199 /* Set the corresponding divisor in the register. */ setMasterClock()
201 switch (divisor) { setMasterClock()
/linux-4.1.27/drivers/w1/masters/
H A Dds1wm.c36 #define DS1WM_CLKDIV 0x04 /* R/W 5 bits of divisor and pre-scale */
67 unsigned long divisor; member in struct:__anon10661
250 return freq[i].divisor; ds1wm_find_divisor()
257 int divisor; ds1wm_up() local
264 divisor = ds1wm_find_divisor(plat->clock_rate); ds1wm_up()
265 dev_dbg(dev, "found divisor 0x%x for clock %d\n", ds1wm_up()
266 divisor, plat->clock_rate); ds1wm_up()
267 if (divisor == 0) { ds1wm_up()
268 dev_err(dev, "no suitable divisor for %dHz clock\n", ds1wm_up()
272 ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor); ds1wm_up()
/linux-4.1.27/arch/nios2/kernel/
H A Dinsnemu.S229 * Divide an unsigned dividend by an unsigned divisor using
239 * remainder >= divisor? no 00000000 0101011:0
241 * remainder >= divisor? no 00000000 101011:00
243 * remainder >= divisor? no 00000001 01011:000
245 * remainder >= divisor? no 00000010 1011:0000
247 * remainder >= divisor? no 00000101 011:00000
249 * remainder >= divisor? yes 00001010 11:000001
250 * remainder -= divisor - 00000111
254 * remainder >= divisor? yes 00000111 1:0000011
255 * remainder -= divisor - 00000111
259 * remainder >= divisor? no 00000001 :00000110
297 * r5 = divisor
322 * if (remainder >= divisor)
325 * remainder -= divisor;
/linux-4.1.27/drivers/tty/serial/
H A Dmpc52xx_uart.c128 /* setting the prescaler and divisor reg is common for all chips */ mpc52xx_set_divisor()
130 u16 prescaler, unsigned int divisor) mpc52xx_set_divisor()
134 out_8(&psc->ctur, divisor >> 8); mpc52xx_set_divisor()
135 out_8(&psc->ctlr, divisor & 0xff); mpc52xx_set_divisor()
297 unsigned int divisor; mpc5200_psc_set_baudrate() local
303 divisor = (port->uartclk + 16 * baud) / (32 * baud); mpc5200_psc_set_baudrate()
305 /* enable the /32 prescaler and set the divisor */ mpc5200_psc_set_baudrate()
306 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); mpc5200_psc_set_baudrate() local
315 unsigned int divisor; mpc5200b_psc_set_baudrate() local
323 divisor = (port->uartclk + 2 * baud) / (4 * baud); mpc5200b_psc_set_baudrate()
325 /* select the proper prescaler and set the divisor mpc5200b_psc_set_baudrate()
327 if (divisor > 0xffff || baud <= 115200) { mpc5200b_psc_set_baudrate()
328 divisor = (divisor + 4) / 8; mpc5200b_psc_set_baudrate()
332 mpc52xx_set_divisor(PSC(port), prescaler, divisor); mpc5200b_psc_set_baudrate() local
543 unsigned int divisor; mpc512x_psc_set_baudrate() local
562 divisor = (port->uartclk + 8 * baud) / (16 * baud); mpc512x_psc_set_baudrate()
564 /* enable the /16 prescaler and set the divisor */ mpc512x_psc_set_baudrate()
565 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); mpc512x_psc_set_baudrate() local
880 u8 prescaler, unsigned int divisor) mpc5125_set_divisor()
884 out_8(&psc->ctur, divisor >> 8); mpc5125_set_divisor()
885 out_8(&psc->ctlr, divisor & 0xff); mpc5125_set_divisor()
893 unsigned int divisor; mpc5125_psc_set_baudrate() local
903 divisor = (port->uartclk + 8 * baud) / (16 * baud); mpc5125_psc_set_baudrate()
905 /* enable the /16 prescaler and set the divisor */ mpc5125_psc_set_baudrate()
906 mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor); mpc5125_psc_set_baudrate() local
129 mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc, u16 prescaler, unsigned int divisor) mpc52xx_set_divisor() argument
879 mpc5125_set_divisor(struct mpc5125_psc __iomem *psc, u8 prescaler, unsigned int divisor) mpc5125_set_divisor() argument
H A Dtilegx.c455 UART_DIVISOR_t divisor; tilegx_set_termios() local
475 divisor.word = gxio_uart_read(context, UART_DIVISOR); tilegx_set_termios()
480 divisor.divisor = uart_get_divisor(port, baud); tilegx_set_termios()
510 gxio_uart_write(context, UART_DIVISOR, divisor.word); tilegx_set_termios()
H A Dlantiq.c394 unsigned int divisor; lqasc_set_termios() local
458 divisor = uart_get_divisor(port, baud); lqasc_set_termios()
459 divisor = divisor / 2 - 1; lqasc_set_termios()
467 /* set up to use divisor of 2 */ lqasc_set_termios()
471 ltq_w32(divisor, port->membase + LTQ_ASC_BG); lqasc_set_termios()
H A D21285.c47 * The documented expression for selecting the divisor is:
50 * we want to select the divisor that gives us the minimum
227 * Ask the core to calculate the divisor for us. serial21285_set_termios()
H A Ddigicolor-usart.c296 unsigned int baud, divisor; digicolor_uart_set_termios() local
308 divisor = uart_get_divisor(port, baud) - 1; digicolor_uart_set_termios()
345 writeb_relaxed(divisor & 0xff, port->membase + UA_HBAUD_LO); digicolor_uart_set_termios()
346 writeb_relaxed(divisor >> 8, port->membase + UA_HBAUD_HI); digicolor_uart_set_termios()
H A D68328serial.c187 * This is used to figure out the divisor speeds and the timeouts
451 int divisor, prescale; member in struct:__anon10353
499 * This routine is called to set the UART divisor registers to match
522 uart->ubaud = PUT_FIELD(UBAUD_DIVIDE, hw_baud_table[i].divisor) | change_speed()
1247 UBAUD = PUT_FIELD(UBAUD_DIVIDE, hw_baud_table[i].divisor) | m68328_set_baud()
H A Dmsm_serial.c384 u16 divisor; member in struct:msm_baud_map
392 unsigned int i, divisor; msm_find_best_baud() local
413 divisor = uart_get_divisor(port, baud); msm_find_best_baud()
416 if (entry->divisor <= divisor) msm_find_best_baud()
H A Dserial-tegra.c273 unsigned int divisor; tegra_set_baudrate() local
288 divisor = 1; tegra_set_baudrate()
291 divisor = DIV_ROUND_CLOSEST(rate, baud * 16); tegra_set_baudrate()
298 tegra_uart_write(tup, divisor & 0xFF, UART_TX); tegra_set_baudrate()
299 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); tegra_set_baudrate()
/linux-4.1.27/arch/arm/mach-pxa/
H A Dviper.c155 * If force is not true then step from existing to new divisor. If
156 * force is true then jump straight to the new divisor. Stepping is
160 * force can be used to initialize the divisor to a know state by
168 unsigned int divisor = 0; viper_set_core_cpu_voltage() local
172 v = "1.0"; divisor = 0xfff; viper_set_core_cpu_voltage()
174 v = "1.1"; divisor = 0xde5; viper_set_core_cpu_voltage()
176 v = "1.3"; divisor = 0x325; viper_set_core_cpu_voltage()
187 step = divisor; viper_set_core_cpu_voltage()
188 else if (current_voltage_divisor < divisor - STEP) viper_set_core_cpu_voltage()
190 else if (current_voltage_divisor > divisor + STEP) viper_set_core_cpu_voltage()
193 step = divisor; viper_set_core_cpu_voltage()
218 } while (current_voltage_divisor != divisor); viper_set_core_cpu_voltage()
/linux-4.1.27/arch/mips/ar7/
H A Dclock.c181 int divisor = prediv * postdiv; tnetd7300_get_clock() local
200 return base_clock / divisor; tnetd7300_get_clock()
203 return (base_clock >> (mul / 16 + 1)) / divisor; tnetd7300_get_clock()
209 return product / divisor; tnetd7300_get_clock()
213 return base_clock / divisor; tnetd7300_get_clock()
215 return base_clock * mul / divisor; tnetd7300_get_clock()
/linux-4.1.27/drivers/ssb/
H A Ddriver_chipcommon.c154 int divisor = 1; chipco_pctl_clockfreqlimit() local
161 divisor = 64; chipco_pctl_clockfreqlimit()
164 divisor = 32; chipco_pctl_clockfreqlimit()
176 divisor = (tmp >> 16) + 1; chipco_pctl_clockfreqlimit()
177 divisor *= 4; chipco_pctl_clockfreqlimit()
182 divisor = (tmp >> 16) + 1; chipco_pctl_clockfreqlimit()
183 divisor *= 4; chipco_pctl_clockfreqlimit()
206 limit /= divisor; chipco_pctl_clockfreqlimit()
/linux-4.1.27/arch/powerpc/platforms/embedded6xx/
H A Dls_uart.c75 out_8(avr_addr + UART_DLL, quot & 0xff); /* LS of divisor */ avr_uart_configure()
76 out_8(avr_addr + UART_DLM, quot >> 8); /* MS of divisor */ avr_uart_configure()
/linux-4.1.27/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet_mdio.c166 printk(KERN_WARNING "Setting MDIO clock divisor to " axienet_mdio_setup()
175 printk(KERN_WARNING "Setting MDIO clock divisor to " axienet_mdio_setup()
186 * 1 to the clock divisor or we will surely be above 2.5 MHz */ axienet_mdio_setup()
190 printk(KERN_DEBUG "%s(): Setting MDIO clock divisor to %u based " axienet_mdio_setup()
H A Dll_temac_mdio.c67 /* Calculate a reasonable divisor for the clock rate */ temac_mdio_setup()
/linux-4.1.27/drivers/clk/st/
H A Dclk-flexgen.c22 /* Pre-divisor's gate */
24 /* Pre-divisor */
26 /* Final divisor's gate */
28 /* Final divisor */
/linux-4.1.27/arch/tile/include/asm/
H A Dvdso.h35 __u32 shift; /* Cycle to nanosecond divisor (power of two) */
/linux-4.1.27/drivers/media/dvb-frontends/
H A Dstv6110.h46 u8 clk_div; /* divisor value for the output clock */
H A Dstv6110x.h29 u8 clk_div; /* divisor value for the output clock */
H A Dtua6100.c115 * The N divisor ratio (note: c->frequency is in kHz, but we tua6100_set_params()
H A Dstv6110.c227 /* divisor value for the output clock */ stv6110_init()
420 /* divisor value for the output clock */ stv6110_attach()
/linux-4.1.27/arch/arm/mach-s3c24xx/
H A Diotiming-s3c2412.c64 * to_div - turn a cycle length into a divisor setting.
74 * calc_timing - calculate timing divisor value and check in range.
91 * s3c2412_calc_bank - calculate the bank divisor settings.
135 * s3c2412_iotiming_calc - calculate all the bank divisor settings.
H A Diotiming-s3c2410.c80 * to_div - convert cycle time to divisor
84 * Convert the given cycle time into the divisor to use to obtain it from
96 * calc_0124 - calculate divisor control for divisors that do /0, /1. /2 and /4
102 * Calculate the divisor, and turn it into the correct control bits to
143 * calc_tacc - calculate divisor control for tacc.
149 * Calculate the divisor control for tACC, taking into account whether
H A Dmach-at2440evb.c161 .pixclock = 33333, /* HCLK 60 MHz, divisor 2 */
H A Dmach-smdk2440.c118 .pixclock = 166667, /* HCLK 60 MHz, divisor 10 */
/linux-4.1.27/drivers/video/fbdev/
H A Dasiliantfb.c120 unsigned char divisor = 0; asiliant_calc_dclk2() local
128 divisor += 0x10; asiliant_calc_dclk2()
166 divisor |= 4; /* or set VCO loop divide to 1 */ asiliant_calc_dclk2()
169 *dclk2_div = divisor; asiliant_calc_dclk2()
234 /* First check the constraint that the maximum post-VCO divisor is 32, asiliantfb_check_var()
273 u8 dclk2_div; /* Holds divisor bitmask */ asiliantfb_set_par()
436 {0xce, 0x90}, /* MCLK divisor = 2 */
H A Dgxt4500.c150 int pll_m; /* ref clock divisor */
151 int pll_n; /* VCO divisor */
152 int pll_pd1; /* first post-divisor */
153 int pll_pd2; /* second post-divisor */
199 * whatever divisor is required by putting the appropriate value into
200 * the reload register. For a divisor of N, one puts the value from
/linux-4.1.27/drivers/cpuidle/governors/
H A Dmenu.c201 int i, divisor; get_typical_interval() local
212 divisor = 0; get_typical_interval()
217 divisor++; get_typical_interval()
222 if (divisor == INTERVALS) get_typical_interval()
225 do_div(avg, divisor); get_typical_interval()
236 if (divisor == INTERVALS) get_typical_interval()
239 do_div(stddev, divisor); get_typical_interval()
246 * greatest difference to an outlier exceeds ~65 ms * sqrt(divisor) get_typical_interval()
255 if (((avg > stddev * 6) && (divisor * 4 >= INTERVALS * 3)) get_typical_interval()
272 if ((divisor * 4) <= INTERVALS * 3) get_typical_interval()
/linux-4.1.27/drivers/clk/mmp/
H A Dclk-mix.c128 item->divisor = parent_rate / item->rate; _filter_clk_table()
235 mix_rate = parent_rate / item->divisor; mmp_clk_mix_determine_rate()
365 div_val = _get_div_val(mix, item->divisor); mmp_clk_set_parent()
399 && item->divisor == best_divisor) mmp_clk_set_rate()
405 _get_div_val(mix, item->divisor), mmp_clk_set_rate()
H A Dclk.h69 unsigned int divisor; member in struct:mmp_clk_mix_clk_table
/linux-4.1.27/drivers/watchdog/
H A Ds3c2410_wdt.c309 unsigned int divisor = 1; s3c2410wdt_set_heartbeat() local
327 divisor = DIV_ROUND_UP(count, 0xffff); s3c2410wdt_set_heartbeat()
329 if (divisor > 0x100) { s3c2410wdt_set_heartbeat()
335 DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n", s3c2410wdt_set_heartbeat()
336 __func__, timeout, divisor, count, DIV_ROUND_UP(count, divisor)); s3c2410wdt_set_heartbeat()
338 count = DIV_ROUND_UP(count, divisor); s3c2410wdt_set_heartbeat()
344 wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); s3c2410wdt_set_heartbeat()
349 wdd->timeout = (count * divisor) / freq; s3c2410wdt_set_heartbeat()
/linux-4.1.27/arch/powerpc/sysdev/qe_lib/
H A Dqe.c202 u32 divisor, tempval; qe_setbrg() local
208 divisor = qe_get_brg_clk() / (rate * multiplier); qe_setbrg()
210 if (divisor > QE_BRGC_DIVISOR_MAX + 1) { qe_setbrg()
212 divisor /= 16; qe_setbrg()
216 that the BRG divisor must be even if you're not using divide-by-16 qe_setbrg()
218 if (!div16 && (divisor & 1) && (divisor > 3)) qe_setbrg()
219 divisor++; qe_setbrg()
221 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | qe_setbrg()
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-axxia.c133 u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate; axxia_i2c_init() local
142 idev->bus_clk_rate, clk_mhz, divisor); axxia_i2c_init()
159 t_high = divisor * 1 / 2; axxia_i2c_init()
160 t_low = divisor * 1 / 2; axxia_i2c_init()
164 t_high = divisor * 1 / 3; axxia_i2c_init()
165 t_low = divisor * 2 / 3; axxia_i2c_init()
H A Di2c-tegra.c124 * @clk_divisor_hs_mode: Clock divisor in HS mode.
125 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
432 /* Make sure clock divisor programmed correctly */ tegra_i2c_init()
/linux-4.1.27/drivers/media/i2c/
H A Dsmiapp-pll.c150 * divisor. Begin with the operational timing and continue to video
153 * @mul is the PLL multiplier and @div is the common divisor
272 * should run at higher clock rate, so smaller divisor is used __smiapp_pll_calculate()
299 /* Find smallest and biggest allowed vt divisor. */ __smiapp_pll_calculate()
350 * divisor. __smiapp_pll_calculate()
482 dev_info(dev, "unable to compute pre_pll divisor\n"); smiapp_pll_calculate()
H A Daptina-pll.c54 /* Compute the multiplier M and combined N*P1 divisor. */ aptina_pll_calculate()
67 * - minimum/maximum combined N*P1 divisor aptina_pll_calculate()
80 dev_err(dev, "pll: no valid combined N*P1 divisor.\n"); aptina_pll_calculate()
/linux-4.1.27/drivers/staging/speakup/
H A Dserialio.c67 outb(quot & 0xff, ser->port + UART_DLL); /* LS of divisor */ spk_serial_init()
68 outb(quot >> 8, ser->port + UART_DLM); /* MS of divisor */ spk_serial_init()
/linux-4.1.27/arch/sh/lib64/
H A Dudivdi3.S55 /* small divisor: need a third divide step */
115 the full 64 bit shift result to multiply with the divisor would require
/linux-4.1.27/drivers/hsi/controllers/
H A Domap_ssi.h43 * @divisor: TX divider
54 u32 divisor; member in struct:omap_ssm_ctx::__anon4666::__anon4667
/linux-4.1.27/arch/blackfin/include/asm/
H A Dbfin_sport3.h59 #define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */
60 #define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */
/linux-4.1.27/arch/c6x/lib/
H A Ddivremu.S23 ;; out how many leading zero bits there are in the divisor. This
24 ;; gives us both a shift count for aligning (shifting) the divisor
H A Ddivu.S40 ;; out how many leading zero bits there are in the divisor. This
41 ;; gives us both a shift count for aligning (shifting) the divisor
/linux-4.1.27/arch/c6x/platforms/
H A Dtimer64.c66 * The divisor is in the EMUMGTCLKSPD register
225 * to get the divisor. timer64_init()
/linux-4.1.27/drivers/media/usb/gspca/
H A Dcpia1.c238 * indexed by [mains][sensorFps.baserate][sensorFps.divisor]*/
297 u8 divisor; member in struct:cam_params::__anon5826
671 params->sensorFps.divisor = 1; reset_camera_params()
679 [params->sensorFps.divisor]; reset_camera_params()
953 sd->params.sensorFps.divisor, command_setsensorfps()
1286 sd->params.sensorFps.divisor < 2) { monitor_exposure()
1289 ++sd->params.sensorFps.divisor; monitor_exposure()
1295 [sd->params.sensorFps.divisor]; monitor_exposure()
1311 sd->params.sensorFps.divisor > 0) { monitor_exposure()
1316 --sd->params.sensorFps.divisor; monitor_exposure()
1322 [sd->params.sensorFps.divisor]; monitor_exposure()
1342 sd->params.sensorFps.divisor < 2) { monitor_exposure()
1345 ++sd->params.sensorFps.divisor; monitor_exposure()
1358 sd->params.sensorFps.divisor > 0) { monitor_exposure()
1361 --sd->params.sensorFps.divisor; monitor_exposure()
1785 [sd->params.sensorFps.divisor]; sd_s_ctrl()
/linux-4.1.27/drivers/clocksource/
H A Dtcb_clksrc.c295 unsigned divisor = atmel_tc_divisors[i]; tcb_clksrc_init() local
299 if (!divisor) { tcb_clksrc_init()
304 tmp = rate / divisor; tcb_clksrc_init()
305 pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp); tcb_clksrc_init()
H A Dcs5535-clockevt.c51 #define MFGPT_SCALE 4 /* divisor = 2^(scale) */
H A Dtimer-integrator-ap.c139 /* Calculate and program a divisor */ integrator_clockevent_init()
H A Dsamsung_pwm_timer.c104 static void samsung_timer_set_divisor(unsigned int channel, u8 divisor) samsung_timer_set_divisor() argument
111 bits = (fls(divisor) - 1) - pwm.variant.div_base; samsung_timer_set_divisor()
/linux-4.1.27/arch/microblaze/lib/
H A Ddivsi3.S64 /* restore values of csrs and that of r3 and the divisor and the dividend */
H A Dmodsi3.S64 /* restore values of csrs and that of r3 and the divisor and the dividend */
H A Dudivsi3.S76 /* restore values of csrs and that of r3 and the divisor and the dividend */
H A Dumodsi3.S78 /* restore values of csrs and that of r3 and the divisor and the dividend */
/linux-4.1.27/arch/m68k/amiga/
H A Damisound.c59 /* setup divisor */ amiga_init_sound()
/linux-4.1.27/include/linux/amba/
H A Dkmi.h73 * KMI clock divisor: to generate 8MHz internal clock
H A Dserial.h47 #define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
48 #define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
/linux-4.1.27/drivers/media/pci/cx88/
H A Dcx88-dsp.c107 u32 divisor; int_goertzel() local
120 divisor = N * N; int_goertzel()
121 do_div(tmp, divisor); int_goertzel()
/linux-4.1.27/drivers/scsi/
H A Dscsicam.c239 temp = cylinders * sectors; /* Compute divisor for heads */ setsize()
243 temp = cylinders * heads; /* Compute divisor for sectors */ setsize()
248 temp = heads * sectors; /* Compute divisor for cylinders */ setsize()
H A Dqlogicfas408.h57 /* This is the sync transfer divisor, XTALFREQ/X will be the maximum
/linux-4.1.27/drivers/gpu/drm/i915/
H A Dintel_dsi_pll.c345 /* mask out other bits and extract the P1 divisor */ vlv_get_dsi_pclk()
349 /* mask out the other bits and extract the M1 divisor */ vlv_get_dsi_pclk()
360 DRM_ERROR("wrong P1 divisor\n"); vlv_get_dsi_pclk()
/linux-4.1.27/arch/tile/include/arch/
H A Duart.h37 * divisor = 68, baud rate = 125M/(68*16) = 115200 baud.
39 uint_reg_t divisor : 12; member in struct:__anon2785::__anon2786
44 uint_reg_t divisor : 12;
/linux-4.1.27/drivers/clk/pistachio/
H A Dclk-pll.c70 static inline u32 do_div_round_closest(u64 dividend, u32 divisor) do_div_round_closest() argument
72 dividend += divisor / 2; do_div_round_closest()
73 do_div(dividend, divisor); do_div_round_closest()
/linux-4.1.27/arch/arm/include/asm/
H A Ddiv64.h17 * In other words, a 64-bit dividend with a 32-bit divisor producing
66 * If the divisor happens to be constant, we determine the appropriate
78 /* non-constant divisor (or zero): slow path */ \
/linux-4.1.27/arch/alpha/kernel/
H A Dcore_lca.c488 printk("\tPrimary clock divisor\t0x%lx\n", LCA_GET_PRIMARY(pmr_reg)); lca_clock_print()
489 printk("\tOverride clock divisor\t0x%lx\n", LCA_GET_OVERRIDE(pmr_reg)); lca_clock_print()
508 lca_clock_fiddle(int divisor) lca_clock_fiddle()
513 LCA_SET_PRIMARY_CLOCK(pmr_reg, divisor); lca_clock_fiddle()
514 /* lca_norm_clock = divisor; */ lca_clock_fiddle()
506 lca_clock_fiddle(int divisor) lca_clock_fiddle() argument
/linux-4.1.27/drivers/media/rc/
H A Dite-cir.h148 /* baud rate divisor default */
227 #define IT87_BDLR 0x05 /* baud rate divisor low byte register */
228 #define IT87_BDHR 0x06 /* baud rate divisor high byte register */
309 #define IT85_C0BDLR 0x08 /* baud rate divisor low byte register */
310 #define IT85_C0BDHR 0x09 /* baud rate divisor high byte register */
418 #define IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */
419 #define IT8708_C0BDHR 0x02 /* baud rate divisor high byte register */
H A Dredrat3.c302 u32 divisor = (RR3_CLK_CONV_FACTOR) / 1000; redrat3_len_to_us() local
303 u32 result = (u32) (biglen / divisor); redrat3_len_to_us()
323 u32 divisor; redrat3_us_to_len() local
326 divisor = (RR3_CLK_CONV_FACTOR / 1000); redrat3_us_to_len()
327 result = (u32)(microsec * divisor) / 1000; redrat3_us_to_len()
/linux-4.1.27/drivers/staging/media/lirc/
H A Dlirc_sir.c581 /* Set divisor to 12 => 9600 Baud */ init_hardware()
620 /* Set divisor to 1 => 115200 Baud */ init_hardware()
784 /* Set divisor to 12 => 9600 Baud */ init_act200()
790 /* Set divisor to 12 => 9600 Baud */ init_act200()
826 /* Set divisor to 1 => 115200 Baud */ init_act200()
887 /* Set divisor to 1 => 115200 Baud */ init_act220()
/linux-4.1.27/drivers/pwm/
H A Dpwm-atmel-tcb.c288 * Find best clk divisor: atmel_tcb_pwm_config()
289 * the smallest divisor which can fulfill the period_ns requirements. atmel_tcb_pwm_config()
303 * If none of the divisor are small enough to represent period_ns atmel_tcb_pwm_config()
/linux-4.1.27/arch/x86/math-emu/
H A Dreg_u_div.S115 /* Check if the divisor can be treated as having just 32 bits */
120 movl SIGH(%ebx),%ecx /* The divisor */
214 /* At this point, we have a dividend < divisor, with a record of
/linux-4.1.27/drivers/clk/bcm/
H A Dclk-kona.c55 /* Convert a divider into the scaled divisor value it represents. */ scaled_div_value()
79 /* The scaled minimum divisor representable by a divider */
89 /* The scaled maximum divisor representable by a divider */ scaled_div_max()
103 * Convert a scaled divisor into its divider representation as
115 /* Return a rate scaled for use when dividing by a scaled divisor. */
561 /* Read a divider value and return the scaled divisor it represents. */ divider_read_scaled()
578 /* Return the scaled divisor value it represents */ divider_read_scaled()
583 * Convert a divider's scaled divisor value into its recorded form
613 /* Convert the scaled divisor to the value we need to record */ __div_commit()
727 * Get the scaled divisor value, and divide the scaled clk_recalc_rate()
743 * If scaled_div is non-null, it is used to return the scaled divisor
1148 * Get the scaled divisor value needed to achieve a clock kona_peri_clk_set_rate()
H A Dclk-kona.h251 * represents by referring to the latter as a "divisor".)
256 * a scaled value by a scaled divisor produces the desired quotient
298 /* A divider with an integral divisor */
308 /* A divider whose divisor has an integer and fractional part */
/linux-4.1.27/drivers/hwmon/
H A Dntc_thermistor.c300 static inline u64 div64_u64_safe(u64 dividend, u64 divisor) div64_u64_safe() argument
302 if (divisor == 0 && dividend == 0) div64_u64_safe()
304 if (divisor == 0) div64_u64_safe()
306 return div64_u64(dividend, divisor); div64_u64_safe()
H A Dw83l786ng.c193 /* Update the fan divisor */ w83l786ng_update_device()
337 * determined in part by the fan divisor. This follows the principle of
339 * because the divisor changed.
746 /* Update the fan divisor */ w83l786ng_probe()
/linux-4.1.27/drivers/bluetooth/
H A Dbtuart_cs.c350 int divisor; btuart_change_speed() local
364 divisor = SPEED_MAX / speed; btuart_change_speed()
383 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */ btuart_change_speed()
384 outb(divisor >> 8, iobase + UART_DLM); btuart_change_speed()
/linux-4.1.27/include/uapi/linux/dvb/
H A Ddmx.h138 unsigned int base; /* output: divisor for stc to get 90 kHz clock */
/linux-4.1.27/include/uapi/linux/
H A Dtty_flags.h32 #define ASYNCB_MAGIC_MULTIPLIER 16 /* Use special CLK or divisor */
/linux-4.1.27/arch/mn10300/kernel/
H A Dmn10300-serial.h79 u8 div_timer; /* timer used as divisor */
/linux-4.1.27/arch/c6x/include/asm/
H A Dclock.h103 #define FIXED_DIV_PLL BIT(4) /* fixed divisor from PLL */
/linux-4.1.27/drivers/media/platform/omap3isp/
H A Dispccp2.c241 * @vpclk_div: Video port divisor
243 * Configure the CCP2 video port with the given clock divisor. The valid divisor
249 * The exact divisor value used might differ from the requested value, as ISP
250 * revision 15.0 represent the divisor by 65536 divided by an integer.
395 /* Compute the minimum clock divisor, based on the pipeline maximum ccp2_adjust_bandwidth()
402 /* Compute the maximum clock divisor, based on the requested frame rate. ccp2_adjust_bandwidth()
416 dev_dbg(isp->dev, "%s: minimum clock divisor = %u\n", __func__, ccp2_adjust_bandwidth()
/linux-4.1.27/drivers/net/irda/
H A Dw83977af_ir.h101 #define ABLL 0x00 /* Advanced baud rate divisor latch (low byte) */
102 #define ABHL 0x01 /* Advanced baud rate divisor latch (high byte) */
H A Dpxaficp_ir.c194 unsigned int divisor; pxa_irda_set_speed() local
202 divisor = 14745600 / (16 * speed); pxa_irda_set_speed()
225 STDLL = divisor & 0xff; pxa_irda_set_speed()
226 STDLH = divisor >> 8; pxa_irda_set_speed()
/linux-4.1.27/sound/drivers/
H A Dserial-u16550.c94 MODULE_PARM_DESC(base, "Base for divisor in bauds.");
136 unsigned char divisor; member in struct:snd_uart16550
395 if (uart->divisor != 0) { snd_uart16550_do_open()
402 outb(uart->divisor snd_uart16550_do_open()
501 /* Restore old divisor */ snd_uart16550_do_close()
502 if (uart->divisor != 0) { snd_uart16550_do_close()
824 uart->divisor = base / speed; snd_uart16550_create()
825 uart->speed = base / (unsigned int)uart->divisor; snd_uart16550_create()
/linux-4.1.27/include/linux/mfd/
H A Ducb1x00.h232 * @div: SIB clock divisor
242 * @div: SIB clock divisor
H A Dmax8997.h134 * @pwm_divisor: divisor for external PWM device
/linux-4.1.27/drivers/spi/
H A Dspi-cadence.c64 * These are the values used in the calculation of baud rate divisor and
68 #define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
69 #define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
70 #define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
144 * divisor is set to 4, threshold value for TX FIFO not full interrupt is set
/linux-4.1.27/drivers/scsi/megaraid/
H A Dmegaraid_sas_fp.c86 u32 mega_mod64(u64 dividend, u32 divisor) mega_mod64() argument
91 if (!divisor) mega_mod64()
94 remainder = do_div(d, divisor); mega_mod64()
100 * @param divisor : Divisor
104 u64 mega_div64_32(uint64_t dividend, uint32_t divisor) mega_div64_32() argument
109 if (!divisor) mega_div64_32()
113 remainder = do_div(d, divisor); mega_div64_32()
/linux-4.1.27/drivers/isdn/hisax/
H A Delsa_ser.c105 * This routine is called to set the UART divisor registers to match
116 /* Determine divisor based on baud rate */ change_speed()
136 serial_outp(cs, UART_DLL, quot & 0xff); /* LS of divisor */ change_speed()
137 serial_outp(cs, UART_DLM, quot >> 8); /* MS of divisor */ change_speed()
/linux-4.1.27/drivers/md/
H A Ddm-stats.c773 unsigned divisor; message_stats_create() local
797 if (sscanf(argv[2], "/%u%c", &divisor, &dummy) == 1) { message_stats_create()
798 if (!divisor) message_stats_create()
801 if (do_div(step, divisor)) message_stats_create()
/linux-4.1.27/arch/mips/include/asm/netlogic/xlp-hal/
H A Duart.h109 /* enable divisor register, and write baud values */ nlm_uart_set_baudrate()
/linux-4.1.27/drivers/video/fbdev/geode/
H A Ddisplay_gx.c86 /* Setup DCLK and its divisor. */ gx_set_mode()
/linux-4.1.27/arch/powerpc/platforms/powermac/
H A Dudbg_scc.c60 13, 0, /* set baud rate divisor */
/linux-4.1.27/arch/powerpc/include/asm/
H A Dtime.h200 unsigned divisor, struct div_result *dr);
/linux-4.1.27/arch/frv/kernel/
H A Ddebug-stub.c206 /* work out the divisor to give us the nearest higher baud rate */ console_set_baud()
H A Dgdb-io.c86 /* work out the divisor to give us the nearest higher baud rate */ gdbstub_set_baud()
/linux-4.1.27/arch/arm/plat-samsung/include/plat/
H A Dcpu-freq.h73 * struct s3c_clkdivs - clock divisor information
/linux-4.1.27/drivers/media/radio/
H A Dradio-gemtek.c84 * value 10.7 MHz), reference divisor 6.39 kHz (nominal 6.25 kHz).
176 * Calculate divisor from FM-frequency for BU2614FS (3.125 KHz STDF expected).
/linux-4.1.27/drivers/sh/clk/
H A Dcpg.c185 * div6 clocks require the divisor field to be non-zero or the sh_clk_div_disable()
186 * above CKSTP toggle silently fails. Ensure that the divisor sh_clk_div_disable()
/linux-4.1.27/drivers/staging/lustre/lustre/lov/
H A Dlov_internal.h45 * order to reduce the divisor to a 32-bit number. If the divisor is
/linux-4.1.27/arch/alpha/include/asm/
H A Dcore_lca.h133 #define LCA_PMR_PDIV 0x7 /* Primary clock divisor */
134 #define LCA_PMR_ODIV 0x38 /* Override clock divisor */
/linux-4.1.27/tools/vm/
H A Dslabinfo.c224 unsigned long divisor = 1; store_size() local
229 divisor = 100000000UL; store_size()
232 divisor = 100000UL; store_size()
235 divisor = 100; store_size()
239 value /= divisor; store_size()
246 if (divisor != 1) { store_size()
/linux-4.1.27/scripts/
H A Dget_maintainer.pl1844 my ($role, $divisor, @lines) = @_;
1851 if ($divisor <= 0) {
1852 warn("Bad divisor in " . (caller(0))[3] . ": $divisor\n");
1853 $divisor = 1;
1868 my $percent = $sign_offs * 100 / $divisor;
1878 add_role($line, "$role:$sign_offs/$divisor=$fmt_percent%");
/linux-4.1.27/sound/isa/cs423x/
H A Dcs4236_lib.c163 static unsigned char divisor_to_rate_register(unsigned int divisor) divisor_to_rate_register() argument
165 switch (divisor) { divisor_to_rate_register()
174 if (divisor < 21 || divisor > 192) { divisor_to_rate_register()
178 return divisor; divisor_to_rate_register()
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb3/
H A Dxgmac.c347 int hwm, lwm, divisor; t3_mac_set_mtu() local
419 divisor = (adap->params.rev == T3_REV_C) ? 64 : 8; t3_mac_set_mtu()
421 (hwm - lwm) * 4 / divisor); t3_mac_set_mtu()

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