1/* 2 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published 6 * by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 16 * 17 * Copyright (C) 2004 Infineon IFAP DC COM CPE 18 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> 19 * Copyright (C) 2007 John Crispin <blogic@openwrt.org> 20 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com> 21 */ 22 23#include <linux/slab.h> 24#include <linux/module.h> 25#include <linux/ioport.h> 26#include <linux/init.h> 27#include <linux/console.h> 28#include <linux/sysrq.h> 29#include <linux/device.h> 30#include <linux/tty.h> 31#include <linux/tty_flip.h> 32#include <linux/serial_core.h> 33#include <linux/serial.h> 34#include <linux/of_platform.h> 35#include <linux/of_address.h> 36#include <linux/of_irq.h> 37#include <linux/io.h> 38#include <linux/clk.h> 39#include <linux/gpio.h> 40 41#include <lantiq_soc.h> 42 43#define PORT_LTQ_ASC 111 44#define MAXPORTS 2 45#define UART_DUMMY_UER_RX 1 46#define DRVNAME "lantiq,asc" 47#ifdef __BIG_ENDIAN 48#define LTQ_ASC_TBUF (0x0020 + 3) 49#define LTQ_ASC_RBUF (0x0024 + 3) 50#else 51#define LTQ_ASC_TBUF 0x0020 52#define LTQ_ASC_RBUF 0x0024 53#endif 54#define LTQ_ASC_FSTAT 0x0048 55#define LTQ_ASC_WHBSTATE 0x0018 56#define LTQ_ASC_STATE 0x0014 57#define LTQ_ASC_IRNCR 0x00F8 58#define LTQ_ASC_CLC 0x0000 59#define LTQ_ASC_ID 0x0008 60#define LTQ_ASC_PISEL 0x0004 61#define LTQ_ASC_TXFCON 0x0044 62#define LTQ_ASC_RXFCON 0x0040 63#define LTQ_ASC_CON 0x0010 64#define LTQ_ASC_BG 0x0050 65#define LTQ_ASC_IRNREN 0x00F4 66 67#define ASC_IRNREN_TX 0x1 68#define ASC_IRNREN_RX 0x2 69#define ASC_IRNREN_ERR 0x4 70#define ASC_IRNREN_TX_BUF 0x8 71#define ASC_IRNCR_TIR 0x1 72#define ASC_IRNCR_RIR 0x2 73#define ASC_IRNCR_EIR 0x4 74 75#define ASCOPT_CSIZE 0x3 76#define TXFIFO_FL 1 77#define RXFIFO_FL 1 78#define ASCCLC_DISS 0x2 79#define ASCCLC_RMCMASK 0x0000FF00 80#define ASCCLC_RMCOFFSET 8 81#define ASCCON_M_8ASYNC 0x0 82#define ASCCON_M_7ASYNC 0x2 83#define ASCCON_ODD 0x00000020 84#define ASCCON_STP 0x00000080 85#define ASCCON_BRS 0x00000100 86#define ASCCON_FDE 0x00000200 87#define ASCCON_R 0x00008000 88#define ASCCON_FEN 0x00020000 89#define ASCCON_ROEN 0x00080000 90#define ASCCON_TOEN 0x00100000 91#define ASCSTATE_PE 0x00010000 92#define ASCSTATE_FE 0x00020000 93#define ASCSTATE_ROE 0x00080000 94#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) 95#define ASCWHBSTATE_CLRREN 0x00000001 96#define ASCWHBSTATE_SETREN 0x00000002 97#define ASCWHBSTATE_CLRPE 0x00000004 98#define ASCWHBSTATE_CLRFE 0x00000008 99#define ASCWHBSTATE_CLRROE 0x00000020 100#define ASCTXFCON_TXFEN 0x0001 101#define ASCTXFCON_TXFFLU 0x0002 102#define ASCTXFCON_TXFITLMASK 0x3F00 103#define ASCTXFCON_TXFITLOFF 8 104#define ASCRXFCON_RXFEN 0x0001 105#define ASCRXFCON_RXFFLU 0x0002 106#define ASCRXFCON_RXFITLMASK 0x3F00 107#define ASCRXFCON_RXFITLOFF 8 108#define ASCFSTAT_RXFFLMASK 0x003F 109#define ASCFSTAT_TXFFLMASK 0x3F00 110#define ASCFSTAT_TXFREEMASK 0x3F000000 111#define ASCFSTAT_TXFREEOFF 24 112 113static void lqasc_tx_chars(struct uart_port *port); 114static struct ltq_uart_port *lqasc_port[MAXPORTS]; 115static struct uart_driver lqasc_reg; 116static DEFINE_SPINLOCK(ltq_asc_lock); 117 118struct ltq_uart_port { 119 struct uart_port port; 120 /* clock used to derive divider */ 121 struct clk *fpiclk; 122 /* clock gating of the ASC core */ 123 struct clk *clk; 124 unsigned int tx_irq; 125 unsigned int rx_irq; 126 unsigned int err_irq; 127}; 128 129static inline struct 130ltq_uart_port *to_ltq_uart_port(struct uart_port *port) 131{ 132 return container_of(port, struct ltq_uart_port, port); 133} 134 135static void 136lqasc_stop_tx(struct uart_port *port) 137{ 138 return; 139} 140 141static void 142lqasc_start_tx(struct uart_port *port) 143{ 144 unsigned long flags; 145 spin_lock_irqsave(<q_asc_lock, flags); 146 lqasc_tx_chars(port); 147 spin_unlock_irqrestore(<q_asc_lock, flags); 148 return; 149} 150 151static void 152lqasc_stop_rx(struct uart_port *port) 153{ 154 ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); 155} 156 157static int 158lqasc_rx_chars(struct uart_port *port) 159{ 160 struct tty_port *tport = &port->state->port; 161 unsigned int ch = 0, rsr = 0, fifocnt; 162 163 fifocnt = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; 164 while (fifocnt--) { 165 u8 flag = TTY_NORMAL; 166 ch = ltq_r8(port->membase + LTQ_ASC_RBUF); 167 rsr = (ltq_r32(port->membase + LTQ_ASC_STATE) 168 & ASCSTATE_ANY) | UART_DUMMY_UER_RX; 169 tty_flip_buffer_push(tport); 170 port->icount.rx++; 171 172 /* 173 * Note that the error handling code is 174 * out of the main execution path 175 */ 176 if (rsr & ASCSTATE_ANY) { 177 if (rsr & ASCSTATE_PE) { 178 port->icount.parity++; 179 ltq_w32_mask(0, ASCWHBSTATE_CLRPE, 180 port->membase + LTQ_ASC_WHBSTATE); 181 } else if (rsr & ASCSTATE_FE) { 182 port->icount.frame++; 183 ltq_w32_mask(0, ASCWHBSTATE_CLRFE, 184 port->membase + LTQ_ASC_WHBSTATE); 185 } 186 if (rsr & ASCSTATE_ROE) { 187 port->icount.overrun++; 188 ltq_w32_mask(0, ASCWHBSTATE_CLRROE, 189 port->membase + LTQ_ASC_WHBSTATE); 190 } 191 192 rsr &= port->read_status_mask; 193 194 if (rsr & ASCSTATE_PE) 195 flag = TTY_PARITY; 196 else if (rsr & ASCSTATE_FE) 197 flag = TTY_FRAME; 198 } 199 200 if ((rsr & port->ignore_status_mask) == 0) 201 tty_insert_flip_char(tport, ch, flag); 202 203 if (rsr & ASCSTATE_ROE) 204 /* 205 * Overrun is special, since it's reported 206 * immediately, and doesn't affect the current 207 * character 208 */ 209 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 210 } 211 212 if (ch != 0) 213 tty_flip_buffer_push(tport); 214 215 return 0; 216} 217 218static void 219lqasc_tx_chars(struct uart_port *port) 220{ 221 struct circ_buf *xmit = &port->state->xmit; 222 if (uart_tx_stopped(port)) { 223 lqasc_stop_tx(port); 224 return; 225 } 226 227 while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) & 228 ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) { 229 if (port->x_char) { 230 ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF); 231 port->icount.tx++; 232 port->x_char = 0; 233 continue; 234 } 235 236 if (uart_circ_empty(xmit)) 237 break; 238 239 ltq_w8(port->state->xmit.buf[port->state->xmit.tail], 240 port->membase + LTQ_ASC_TBUF); 241 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 242 port->icount.tx++; 243 } 244 245 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 246 uart_write_wakeup(port); 247} 248 249static irqreturn_t 250lqasc_tx_int(int irq, void *_port) 251{ 252 unsigned long flags; 253 struct uart_port *port = (struct uart_port *)_port; 254 spin_lock_irqsave(<q_asc_lock, flags); 255 ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); 256 spin_unlock_irqrestore(<q_asc_lock, flags); 257 lqasc_start_tx(port); 258 return IRQ_HANDLED; 259} 260 261static irqreturn_t 262lqasc_err_int(int irq, void *_port) 263{ 264 unsigned long flags; 265 struct uart_port *port = (struct uart_port *)_port; 266 spin_lock_irqsave(<q_asc_lock, flags); 267 /* clear any pending interrupts */ 268 ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | 269 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); 270 spin_unlock_irqrestore(<q_asc_lock, flags); 271 return IRQ_HANDLED; 272} 273 274static irqreturn_t 275lqasc_rx_int(int irq, void *_port) 276{ 277 unsigned long flags; 278 struct uart_port *port = (struct uart_port *)_port; 279 spin_lock_irqsave(<q_asc_lock, flags); 280 ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); 281 lqasc_rx_chars(port); 282 spin_unlock_irqrestore(<q_asc_lock, flags); 283 return IRQ_HANDLED; 284} 285 286static unsigned int 287lqasc_tx_empty(struct uart_port *port) 288{ 289 int status; 290 status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; 291 return status ? 0 : TIOCSER_TEMT; 292} 293 294static unsigned int 295lqasc_get_mctrl(struct uart_port *port) 296{ 297 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; 298} 299 300static void 301lqasc_set_mctrl(struct uart_port *port, u_int mctrl) 302{ 303} 304 305static void 306lqasc_break_ctl(struct uart_port *port, int break_state) 307{ 308} 309 310static int 311lqasc_startup(struct uart_port *port) 312{ 313 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 314 int retval; 315 316 if (!IS_ERR(ltq_port->clk)) 317 clk_enable(ltq_port->clk); 318 port->uartclk = clk_get_rate(ltq_port->fpiclk); 319 320 ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), 321 port->membase + LTQ_ASC_CLC); 322 323 ltq_w32(0, port->membase + LTQ_ASC_PISEL); 324 ltq_w32( 325 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | 326 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, 327 port->membase + LTQ_ASC_TXFCON); 328 ltq_w32( 329 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) 330 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, 331 port->membase + LTQ_ASC_RXFCON); 332 /* make sure other settings are written to hardware before 333 * setting enable bits 334 */ 335 wmb(); 336 ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | 337 ASCCON_ROEN, port->membase + LTQ_ASC_CON); 338 339 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, 340 0, "asc_tx", port); 341 if (retval) { 342 pr_err("failed to request lqasc_tx_int\n"); 343 return retval; 344 } 345 346 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int, 347 0, "asc_rx", port); 348 if (retval) { 349 pr_err("failed to request lqasc_rx_int\n"); 350 goto err1; 351 } 352 353 retval = request_irq(ltq_port->err_irq, lqasc_err_int, 354 0, "asc_err", port); 355 if (retval) { 356 pr_err("failed to request lqasc_err_int\n"); 357 goto err2; 358 } 359 360 ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, 361 port->membase + LTQ_ASC_IRNREN); 362 return 0; 363 364err2: 365 free_irq(ltq_port->rx_irq, port); 366err1: 367 free_irq(ltq_port->tx_irq, port); 368 return retval; 369} 370 371static void 372lqasc_shutdown(struct uart_port *port) 373{ 374 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 375 free_irq(ltq_port->tx_irq, port); 376 free_irq(ltq_port->rx_irq, port); 377 free_irq(ltq_port->err_irq, port); 378 379 ltq_w32(0, port->membase + LTQ_ASC_CON); 380 ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, 381 port->membase + LTQ_ASC_RXFCON); 382 ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, 383 port->membase + LTQ_ASC_TXFCON); 384 if (!IS_ERR(ltq_port->clk)) 385 clk_disable(ltq_port->clk); 386} 387 388static void 389lqasc_set_termios(struct uart_port *port, 390 struct ktermios *new, struct ktermios *old) 391{ 392 unsigned int cflag; 393 unsigned int iflag; 394 unsigned int divisor; 395 unsigned int baud; 396 unsigned int con = 0; 397 unsigned long flags; 398 399 cflag = new->c_cflag; 400 iflag = new->c_iflag; 401 402 switch (cflag & CSIZE) { 403 case CS7: 404 con = ASCCON_M_7ASYNC; 405 break; 406 407 case CS5: 408 case CS6: 409 default: 410 new->c_cflag &= ~ CSIZE; 411 new->c_cflag |= CS8; 412 con = ASCCON_M_8ASYNC; 413 break; 414 } 415 416 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 417 418 if (cflag & CSTOPB) 419 con |= ASCCON_STP; 420 421 if (cflag & PARENB) { 422 if (!(cflag & PARODD)) 423 con &= ~ASCCON_ODD; 424 else 425 con |= ASCCON_ODD; 426 } 427 428 port->read_status_mask = ASCSTATE_ROE; 429 if (iflag & INPCK) 430 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 431 432 port->ignore_status_mask = 0; 433 if (iflag & IGNPAR) 434 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 435 436 if (iflag & IGNBRK) { 437 /* 438 * If we're ignoring parity and break indicators, 439 * ignore overruns too (for real raw support). 440 */ 441 if (iflag & IGNPAR) 442 port->ignore_status_mask |= ASCSTATE_ROE; 443 } 444 445 if ((cflag & CREAD) == 0) 446 port->ignore_status_mask |= UART_DUMMY_UER_RX; 447 448 /* set error signals - framing, parity and overrun, enable receiver */ 449 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; 450 451 spin_lock_irqsave(<q_asc_lock, flags); 452 453 /* set up CON */ 454 ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON); 455 456 /* Set baud rate - take a divider of 2 into account */ 457 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 458 divisor = uart_get_divisor(port, baud); 459 divisor = divisor / 2 - 1; 460 461 /* disable the baudrate generator */ 462 ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON); 463 464 /* make sure the fractional divider is off */ 465 ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); 466 467 /* set up to use divisor of 2 */ 468 ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); 469 470 /* now we can write the new baudrate into the register */ 471 ltq_w32(divisor, port->membase + LTQ_ASC_BG); 472 473 /* turn the baudrate generator back on */ 474 ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON); 475 476 /* enable rx */ 477 ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); 478 479 spin_unlock_irqrestore(<q_asc_lock, flags); 480 481 /* Don't rewrite B0 */ 482 if (tty_termios_baud_rate(new)) 483 tty_termios_encode_baud_rate(new, baud, baud); 484 485 uart_update_timeout(port, cflag, baud); 486} 487 488static const char* 489lqasc_type(struct uart_port *port) 490{ 491 if (port->type == PORT_LTQ_ASC) 492 return DRVNAME; 493 else 494 return NULL; 495} 496 497static void 498lqasc_release_port(struct uart_port *port) 499{ 500 struct platform_device *pdev = to_platform_device(port->dev); 501 502 if (port->flags & UPF_IOREMAP) { 503 devm_iounmap(&pdev->dev, port->membase); 504 port->membase = NULL; 505 } 506} 507 508static int 509lqasc_request_port(struct uart_port *port) 510{ 511 struct platform_device *pdev = to_platform_device(port->dev); 512 struct resource *res; 513 int size; 514 515 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 516 if (!res) { 517 dev_err(&pdev->dev, "cannot obtain I/O memory region"); 518 return -ENODEV; 519 } 520 size = resource_size(res); 521 522 res = devm_request_mem_region(&pdev->dev, res->start, 523 size, dev_name(&pdev->dev)); 524 if (!res) { 525 dev_err(&pdev->dev, "cannot request I/O memory region"); 526 return -EBUSY; 527 } 528 529 if (port->flags & UPF_IOREMAP) { 530 port->membase = devm_ioremap_nocache(&pdev->dev, 531 port->mapbase, size); 532 if (port->membase == NULL) 533 return -ENOMEM; 534 } 535 return 0; 536} 537 538static void 539lqasc_config_port(struct uart_port *port, int flags) 540{ 541 if (flags & UART_CONFIG_TYPE) { 542 port->type = PORT_LTQ_ASC; 543 lqasc_request_port(port); 544 } 545} 546 547static int 548lqasc_verify_port(struct uart_port *port, 549 struct serial_struct *ser) 550{ 551 int ret = 0; 552 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC) 553 ret = -EINVAL; 554 if (ser->irq < 0 || ser->irq >= NR_IRQS) 555 ret = -EINVAL; 556 if (ser->baud_base < 9600) 557 ret = -EINVAL; 558 return ret; 559} 560 561static struct uart_ops lqasc_pops = { 562 .tx_empty = lqasc_tx_empty, 563 .set_mctrl = lqasc_set_mctrl, 564 .get_mctrl = lqasc_get_mctrl, 565 .stop_tx = lqasc_stop_tx, 566 .start_tx = lqasc_start_tx, 567 .stop_rx = lqasc_stop_rx, 568 .break_ctl = lqasc_break_ctl, 569 .startup = lqasc_startup, 570 .shutdown = lqasc_shutdown, 571 .set_termios = lqasc_set_termios, 572 .type = lqasc_type, 573 .release_port = lqasc_release_port, 574 .request_port = lqasc_request_port, 575 .config_port = lqasc_config_port, 576 .verify_port = lqasc_verify_port, 577}; 578 579static void 580lqasc_console_putchar(struct uart_port *port, int ch) 581{ 582 int fifofree; 583 584 if (!port->membase) 585 return; 586 587 do { 588 fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT) 589 & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF; 590 } while (fifofree == 0); 591 ltq_w8(ch, port->membase + LTQ_ASC_TBUF); 592} 593 594 595static void 596lqasc_console_write(struct console *co, const char *s, u_int count) 597{ 598 struct ltq_uart_port *ltq_port; 599 struct uart_port *port; 600 unsigned long flags; 601 602 if (co->index >= MAXPORTS) 603 return; 604 605 ltq_port = lqasc_port[co->index]; 606 if (!ltq_port) 607 return; 608 609 port = <q_port->port; 610 611 spin_lock_irqsave(<q_asc_lock, flags); 612 uart_console_write(port, s, count, lqasc_console_putchar); 613 spin_unlock_irqrestore(<q_asc_lock, flags); 614} 615 616static int __init 617lqasc_console_setup(struct console *co, char *options) 618{ 619 struct ltq_uart_port *ltq_port; 620 struct uart_port *port; 621 int baud = 115200; 622 int bits = 8; 623 int parity = 'n'; 624 int flow = 'n'; 625 626 if (co->index >= MAXPORTS) 627 return -ENODEV; 628 629 ltq_port = lqasc_port[co->index]; 630 if (!ltq_port) 631 return -ENODEV; 632 633 port = <q_port->port; 634 635 if (!IS_ERR(ltq_port->clk)) 636 clk_enable(ltq_port->clk); 637 638 port->uartclk = clk_get_rate(ltq_port->fpiclk); 639 640 if (options) 641 uart_parse_options(options, &baud, &parity, &bits, &flow); 642 return uart_set_options(port, co, baud, parity, bits, flow); 643} 644 645static struct console lqasc_console = { 646 .name = "ttyLTQ", 647 .write = lqasc_console_write, 648 .device = uart_console_device, 649 .setup = lqasc_console_setup, 650 .flags = CON_PRINTBUFFER, 651 .index = -1, 652 .data = &lqasc_reg, 653}; 654 655static int __init 656lqasc_console_init(void) 657{ 658 register_console(&lqasc_console); 659 return 0; 660} 661console_initcall(lqasc_console_init); 662 663static struct uart_driver lqasc_reg = { 664 .owner = THIS_MODULE, 665 .driver_name = DRVNAME, 666 .dev_name = "ttyLTQ", 667 .major = 0, 668 .minor = 0, 669 .nr = MAXPORTS, 670 .cons = &lqasc_console, 671}; 672 673static int __init 674lqasc_probe(struct platform_device *pdev) 675{ 676 struct device_node *node = pdev->dev.of_node; 677 struct ltq_uart_port *ltq_port; 678 struct uart_port *port; 679 struct resource *mmres, irqres[3]; 680 int line = 0; 681 int ret; 682 683 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 684 ret = of_irq_to_resource_table(node, irqres, 3); 685 if (!mmres || (ret != 3)) { 686 dev_err(&pdev->dev, 687 "failed to get memory/irq for serial port\n"); 688 return -ENODEV; 689 } 690 691 /* check if this is the console port */ 692 if (mmres->start != CPHYSADDR(LTQ_EARLY_ASC)) 693 line = 1; 694 695 if (lqasc_port[line]) { 696 dev_err(&pdev->dev, "port %d already allocated\n", line); 697 return -EBUSY; 698 } 699 700 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port), 701 GFP_KERNEL); 702 if (!ltq_port) 703 return -ENOMEM; 704 705 port = <q_port->port; 706 707 port->iotype = SERIAL_IO_MEM; 708 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 709 port->ops = &lqasc_pops; 710 port->fifosize = 16; 711 port->type = PORT_LTQ_ASC, 712 port->line = line; 713 port->dev = &pdev->dev; 714 /* unused, just to be backward-compatible */ 715 port->irq = irqres[0].start; 716 port->mapbase = mmres->start; 717 718 ltq_port->fpiclk = clk_get_fpi(); 719 if (IS_ERR(ltq_port->fpiclk)) { 720 pr_err("failed to get fpi clk\n"); 721 return -ENOENT; 722 } 723 724 /* not all asc ports have clock gates, lets ignore the return code */ 725 ltq_port->clk = clk_get(&pdev->dev, NULL); 726 727 ltq_port->tx_irq = irqres[0].start; 728 ltq_port->rx_irq = irqres[1].start; 729 ltq_port->err_irq = irqres[2].start; 730 731 lqasc_port[line] = ltq_port; 732 platform_set_drvdata(pdev, ltq_port); 733 734 ret = uart_add_one_port(&lqasc_reg, port); 735 736 return ret; 737} 738 739static const struct of_device_id ltq_asc_match[] = { 740 { .compatible = DRVNAME }, 741 {}, 742}; 743MODULE_DEVICE_TABLE(of, ltq_asc_match); 744 745static struct platform_driver lqasc_driver = { 746 .driver = { 747 .name = DRVNAME, 748 .of_match_table = ltq_asc_match, 749 }, 750}; 751 752int __init 753init_lqasc(void) 754{ 755 int ret; 756 757 ret = uart_register_driver(&lqasc_reg); 758 if (ret != 0) 759 return ret; 760 761 ret = platform_driver_probe(&lqasc_driver, lqasc_probe); 762 if (ret != 0) 763 uart_unregister_driver(&lqasc_reg); 764 765 return ret; 766} 767 768module_init(init_lqasc); 769 770MODULE_DESCRIPTION("Lantiq serial port driver"); 771MODULE_LICENSE("GPL"); 772