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Searched refs:dividers (Results 1 – 51 of 51) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Drv740_dpm.c125 struct atom_clock_dividers dividers; in rv740_populate_sclk_value() local
138 engine_clock, false, &dividers); in rv740_populate_sclk_value()
142 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
144 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
149 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
150 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
161 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
200 struct atom_clock_dividers dividers; in rv740_populate_mclk_value() local
206 memory_clock, false, &dividers); in rv740_populate_mclk_value()
210 ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in rv740_populate_mclk_value()
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Drv730_dpm.c45 struct atom_clock_dividers dividers; in rv730_populate_sclk_value() local
58 engine_clock, false, &dividers); in rv730_populate_sclk_value()
62 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
64 if (dividers.enable_post_div) in rv730_populate_sclk_value()
65 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
66 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
75 if (dividers.enable_post_div) in rv730_populate_sclk_value()
80 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
81 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
82 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
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Drv6xx_dpm.c143 struct atom_clock_dividers dividers; in rv6xx_convert_clock_to_stepping() local
146 clock, false, &dividers); in rv6xx_convert_clock_to_stepping()
150 if (dividers.enable_post_div) in rv6xx_convert_clock_to_stepping()
151 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
527 struct atom_clock_dividers *dividers, in rv6xx_calculate_vco_frequency() argument
530 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
531 (dividers->ref_div + 1); in rv6xx_calculate_vco_frequency()
554 struct atom_clock_dividers dividers; in rv6xx_program_engine_spread_spectrum() local
561 …if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers) == 0) { in rv6xx_program_engine_spread_spectrum()
562 vco_freq = rv6xx_calculate_vco_frequency(ref_clk, &dividers, in rv6xx_program_engine_spread_spectrum()
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Drv770_dpm.c321 struct atom_clock_dividers *dividers, in rv770_calculate_fractional_mpll_feedback_divider() argument
333 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
334 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
403 struct atom_clock_dividers dividers; in rv770_populate_mclk_value() local
411 memory_clock, false, &dividers); in rv770_populate_mclk_value()
415 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) in rv770_populate_mclk_value()
420 &dividers, &clkf, &clkfrac); in rv770_populate_mclk_value()
422 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
433 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
439 if (dividers.vco_mode) in rv770_populate_mclk_value()
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Dcypress_dpm.c494 struct atom_clock_dividers dividers; in cypress_populate_mclk_value() local
501 memory_clock, strobe_mode, &dividers); in cypress_populate_mclk_value()
509 dividers.post_div = 1; in cypress_populate_mclk_value()
512 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in cypress_populate_mclk_value()
519 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
520 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in cypress_populate_mclk_value()
521 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); in cypress_populate_mclk_value()
522 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); in cypress_populate_mclk_value()
525 if (dividers.vco_mode) in cypress_populate_mclk_value()
536 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
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Drs780_dpm.c77 struct atom_clock_dividers dividers; in rs780_initialize_dpm_power_state() local
82 default_state->sclk_low, false, &dividers); in rs780_initialize_dpm_power_state()
86 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); in rs780_initialize_dpm_power_state()
87 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
88 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
90 if (dividers.enable_post_div) in rs780_initialize_dpm_power_state()
1032 struct atom_clock_dividers dividers; in rs780_dpm_force_performance_level() local
1043 ps->sclk_high, false, &dividers); in rs780_dpm_force_performance_level()
1047 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1050 ps->sclk_low, false, &dividers); in rs780_dpm_force_performance_level()
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Dradeon_atombios.c2828 struct atom_clock_dividers *dividers) in radeon_atom_get_clock_dividers() argument
2835 memset(dividers, 0, sizeof(struct atom_clock_dividers)); in radeon_atom_get_clock_dividers()
2848 dividers->post_div = args.v1.ucPostDiv; in radeon_atom_get_clock_dividers()
2849 dividers->fb_div = args.v1.ucFbDiv; in radeon_atom_get_clock_dividers()
2850 dividers->enable_post_div = true; in radeon_atom_get_clock_dividers()
2862 dividers->post_div = args.v2.ucPostDiv; in radeon_atom_get_clock_dividers()
2863 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); in radeon_atom_get_clock_dividers()
2864 dividers->ref_div = args.v2.ucAction; in radeon_atom_get_clock_dividers()
2866 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? in radeon_atom_get_clock_dividers()
2868 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; in radeon_atom_get_clock_dividers()
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Dni_dpm.c2004 struct atom_clock_dividers dividers; in ni_calculate_sclk_params() local
2018 engine_clock, false, &dividers); in ni_calculate_sclk_params()
2022 reference_divider = 1 + dividers.ref_div; in ni_calculate_sclk_params()
2025 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()
2030 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in ni_calculate_sclk_params()
2031 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in ni_calculate_sclk_params()
2042 u32 vco_freq = engine_clock * dividers.post_div; in ni_calculate_sclk_params()
2177 struct atom_clock_dividers dividers; in ni_populate_mclk_value() local
2184 memory_clock, strobe_mode, &dividers); in ni_populate_mclk_value()
2192 dividers.post_div = 1; in ni_populate_mclk_value()
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Dkv_dpm.c537 struct atom_clock_dividers dividers; in kv_set_divider_value() local
541 sclk, false, &dividers); in kv_set_divider_value()
545 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
822 struct atom_clock_dividers dividers; in kv_populate_uvd_table() local
845 table->entries[i].vclk, false, &dividers); in kv_populate_uvd_table()
848 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
851 table->entries[i].dclk, false, &dividers); in kv_populate_uvd_table()
854 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
895 struct atom_clock_dividers dividers; in kv_populate_vce_table() local
913 table->entries[i].evclk, false, &dividers); in kv_populate_vce_table()
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Dtrinity_dpm.c365 struct atom_clock_dividers dividers; in trinity_gfx_powergating_initialize() local
372 25000, false, &dividers); in trinity_gfx_powergating_initialize()
380 value |= PDS_DIV(dividers.post_div); in trinity_gfx_powergating_initialize()
584 struct atom_clock_dividers dividers; in trinity_set_divider_value() local
590 sclk, false, &dividers); in trinity_set_divider_value()
596 value |= CLK_DIVIDER(dividers.post_div); in trinity_set_divider_value()
600 sclk/2, false, &dividers); in trinity_set_divider_value()
606 value |= PD_SCLK_DIVIDER(dividers.post_div); in trinity_set_divider_value()
Dci_dpm.c2622 struct atom_clock_dividers dividers; in ci_populate_smc_uvd_level() local
2639 table->UvdLevel[count].VclkFrequency, false, &dividers); in ci_populate_smc_uvd_level()
2643 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2647 table->UvdLevel[count].DclkFrequency, false, &dividers); in ci_populate_smc_uvd_level()
2651 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2665 struct atom_clock_dividers dividers; in ci_populate_smc_vce_level() local
2680 table->VceLevel[count].Frequency, false, &dividers); in ci_populate_smc_vce_level()
2684 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2698 struct atom_clock_dividers dividers; in ci_populate_smc_acp_level() local
2713 table->AcpLevel[count].Frequency, false, &dividers); in ci_populate_smc_acp_level()
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Dsumo_dpm.c552 struct atom_clock_dividers dividers; in sumo_program_power_level() local
556 pl->sclk, false, &dividers); in sumo_program_power_level()
560 sumo_set_divider_value(rdev, index, dividers.post_div); in sumo_program_power_level()
787 struct atom_clock_dividers dividers; in sumo_program_acpi_power_level() local
792 false, &dividers); in sumo_program_acpi_power_level()
796 WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK); in sumo_program_acpi_power_level()
Dsi_dpm.c4726 struct atom_clock_dividers dividers; in si_calculate_sclk_params() local
4740 engine_clock, false, &dividers); in si_calculate_sclk_params()
4744 reference_divider = 1 + dividers.ref_div; in si_calculate_sclk_params()
4746 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()
4751 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in si_calculate_sclk_params()
4752 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in si_calculate_sclk_params()
4763 u32 vco_freq = engine_clock * dividers.post_div; in si_calculate_sclk_params()
6810 struct atom_clock_dividers dividers; in si_dpm_init() local
6874 0, false, &dividers); in si_dpm_init()
6876 pi->ref_div = dividers.ref_div + 1; in si_dpm_init()
Dbtc_dpm.c2556 struct atom_clock_dividers dividers; in btc_dpm_init() local
2606 0, false, &dividers); in btc_dpm_init()
2608 pi->ref_div = dividers.ref_div + 1; in btc_dpm_init()
Dcik.c9690 struct atom_clock_dividers dividers; in cik_set_uvd_clock() local
9694 clock, false, &dividers); in cik_set_uvd_clock()
9700 tmp |= dividers.post_divider; in cik_set_uvd_clock()
9729 struct atom_clock_dividers dividers; in cik_set_vce_clocks() local
9733 ecclk, false, &dividers); in cik_set_vce_clocks()
9747 tmp |= dividers.post_divider; in cik_set_vce_clocks()
Devergreen.c1072 struct atom_clock_dividers dividers; in sumo_set_uvd_clock() local
1075 clock, false, &dividers); in sumo_set_uvd_clock()
1079 WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK)); in sumo_set_uvd_clock()
Dradeon.h289 struct atom_clock_dividers *dividers);
/linux-4.1.27/Documentation/devicetree/bindings/clock/ti/
Ddivider.txt30 Additionally an array of valid dividers may be supplied like so:
32 ti,dividers = <4>, <8>, <0>, <16>;
45 unless the divider array is provided, min and max dividers. Optionally
63 - ti,dividers : array of integers defining divisors
68 if ti,dividers is not defined.
70 only valid if ti,dividers is not defined.
72 only valid if ti,dividers is not defined.
113 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
/linux-4.1.27/arch/arm/boot/dts/
Domap2420-clocks.dtsi82 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
265 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
269 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
Domap446x-clocks.dtsi17 ti,dividers = <8>, <16>, <32>;
Dpxa27x.dtsi42 * The muxing of external clocks/internal dividers for osc* clock
Domap44xx-clocks.dtsi464 ti,dividers = <2>, <1>;
694 ti,dividers = <14>, <18>;
737 ti,dividers = <0>, <1>, <2>, <0>, <4>;
929 ti,dividers = <4>, <8>;
945 ti,dividers = <2>, <4>;
953 ti,dividers = <2>, <4>;
961 ti,dividers = <1>, <8>;
Domap36xx-omap3430es2plus-clocks.dtsi25 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
Domap3430es1-clocks.dtsi82 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
Ddm816x-clocks.dtsi159 ti,dividers = <2>, <4>;
Ddra7xx-clocks.dtsi893 ti,dividers = <8>, <16>;
917 ti,dividers = <16>, <32>;
1247 ti,dividers = <2>, <1>;
1493 ti,dividers = <1>, <8>;
1718 ti,dividers = <2>;
1751 ti,dividers = <8>, <16>, <32>;
Domap2430-clocks.dtsi92 ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
Domap54xx-clocks.dtsi150 ti,dividers = <2>, <1>;
819 ti,dividers = <1>, <8>;
Dam43xx-clocks.dtsi692 ti,dividers = <8>, <16>, <32>;
Domap24xx-clocks.dtsi511 ti,dividers = <0>, <1>, <2>, <0>, <4>;
/linux-4.1.27/Documentation/arm/Samsung-S3C24XX/
DCPUfreq.txt15 PLL to feed the ARM, memory and peripherals via a series of dividers
26 system. Each CPU registers a driver to control the PLL, clock dividers
/linux-4.1.27/Documentation/devicetree/bindings/clock/
Drenesas,r8a7778-cpg-clocks.txt4 several fixed ratio dividers
Drenesas,r8a7779-cpg-clocks.txt4 several fixed ratio dividers
Drenesas,r8a73a4-cpg-clocks.txt4 and several fixed ratio dividers.
Drenesas,rz-cpg-clocks.txt4 CPU and GPU clocks, and several fixed ratio dividers.
Drenesas,sh73a0-cpg-clocks.txt6 and several fixed ratio dividers.
Drenesas,r8a7740-cpg-clocks.txt6 and several fixed ratio and variable ratio dividers.
Drenesas,rcar-gen2-cpg-clocks.txt4 and several fixed ratio dividers.
/linux-4.1.27/Documentation/ABI/testing/
Dsysfs-bus-iio-frequency-adf43508 that is used to compute the various dividers, is able to
Dsysfs-bus-iio-frequency-ad952326 functionality. All dividers are reset and the channels start
/linux-4.1.27/drivers/clk/ti/
Ddivider.c339 if (setup->dividers[i]) in _get_div_table_from_setup()
350 if (setup->dividers[i]) { in _get_div_table_from_setup()
351 table[valid_div].div = setup->dividers[i]; in _get_div_table_from_setup()
Dclock.h99 int *dividers; member
Dclk-3xxx-legacy.c710 .dividers = ssi_ssr_div_fck_3430es1_divs,
3279 .dividers = ssi_ssr_div_fck_3430es2_divs,
/linux-4.1.27/Documentation/devicetree/bindings/clock/st/
Dst,flexgen.txt6 - a pre and final dividers (represented by a divider and gate elements)
/linux-4.1.27/Documentation/devicetree/bindings/regulator/
Dltc3589.txt14 the resistor values of their external feedback voltage dividers:
/linux-4.1.27/Documentation/devicetree/bindings/iio/frequency/
Dadf4350.txt57 the auxiliary RF output. Default = Output of RF dividers.
/linux-4.1.27/Documentation/hwmon/
Dpc8736069 For reference, here are a few values about clock dividers:
182 The datasheets suggests that some values (fan mins, fan dividers)
/linux-4.1.27/Documentation/scsi/
D53c700.txt48 asynchronous dividers for the chip. As a general rule of thumb,
/linux-4.1.27/arch/arm/mach-omap2/
Dsram243x.S272 str r8, [r4] @ make dividers take
Dsram242x.S272 str r8, [r4] @ make dividers take
/linux-4.1.27/arch/m68k/
DKconfig.cpu437 use internal dividers. In general the kernel won't setup a PLL