Searched refs:clk_lock (Results 1 - 21 of 21) sorted by relevance

/linux-4.1.27/drivers/clk/mmp/
H A Dclk-mmp2.c55 static DEFINE_SPINLOCK(clk_lock);
194 ARRAY_SIZE(uart_factor_tbl), &clk_lock); mmp2_clk_init()
199 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); mmp2_clk_init()
203 apbc_base + APBC_TWSI1, 10, 0, &clk_lock); mmp2_clk_init()
207 apbc_base + APBC_TWSI2, 10, 0, &clk_lock); mmp2_clk_init()
211 apbc_base + APBC_TWSI3, 10, 0, &clk_lock); mmp2_clk_init()
215 apbc_base + APBC_TWSI4, 10, 0, &clk_lock); mmp2_clk_init()
219 apbc_base + APBC_TWSI5, 10, 0, &clk_lock); mmp2_clk_init()
223 apbc_base + APBC_GPIO, 10, 0, &clk_lock); mmp2_clk_init()
227 apbc_base + APBC_KPC, 10, 0, &clk_lock); mmp2_clk_init()
231 apbc_base + APBC_RTC, 10, 0, &clk_lock); mmp2_clk_init()
235 apbc_base + APBC_PWM0, 10, 0, &clk_lock); mmp2_clk_init()
239 apbc_base + APBC_PWM1, 10, 0, &clk_lock); mmp2_clk_init()
243 apbc_base + APBC_PWM2, 10, 0, &clk_lock); mmp2_clk_init()
247 apbc_base + APBC_PWM3, 10, 0, &clk_lock); mmp2_clk_init()
253 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); mmp2_clk_init()
258 apbc_base + APBC_UART0, 10, 0, &clk_lock); mmp2_clk_init()
264 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); mmp2_clk_init()
269 apbc_base + APBC_UART1, 10, 0, &clk_lock); mmp2_clk_init()
275 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); mmp2_clk_init()
280 apbc_base + APBC_UART2, 10, 0, &clk_lock); mmp2_clk_init()
286 apbc_base + APBC_UART3, 4, 3, 0, &clk_lock); mmp2_clk_init()
291 apbc_base + APBC_UART3, 10, 0, &clk_lock); mmp2_clk_init()
297 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); mmp2_clk_init()
301 apbc_base + APBC_SSP0, 10, 0, &clk_lock); mmp2_clk_init()
307 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); mmp2_clk_init()
311 apbc_base + APBC_SSP1, 10, 0, &clk_lock); mmp2_clk_init()
317 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); mmp2_clk_init()
321 apbc_base + APBC_SSP2, 10, 0, &clk_lock); mmp2_clk_init()
327 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); mmp2_clk_init()
331 apbc_base + APBC_SSP3, 10, 0, &clk_lock); mmp2_clk_init()
337 apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock); mmp2_clk_init()
342 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); mmp2_clk_init()
346 0x1b, &clk_lock); mmp2_clk_init()
350 0x1b, &clk_lock); mmp2_clk_init()
354 0x1b, &clk_lock); mmp2_clk_init()
358 0x1b, &clk_lock); mmp2_clk_init()
362 0x9, &clk_lock); mmp2_clk_init()
368 apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock); mmp2_clk_init()
373 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); mmp2_clk_init()
377 apmu_base + APMU_DISP0, 0x1b, &clk_lock); mmp2_clk_init()
381 apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock); mmp2_clk_init()
385 apmu_base + APMU_DISP0, 0x1024, &clk_lock); mmp2_clk_init()
391 apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock); mmp2_clk_init()
396 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); mmp2_clk_init()
400 apmu_base + APMU_DISP1, 0x1b, &clk_lock); mmp2_clk_init()
404 apmu_base + APMU_CCIC0, 0x1800, &clk_lock); mmp2_clk_init()
410 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock); mmp2_clk_init()
415 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); mmp2_clk_init()
419 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); mmp2_clk_init()
423 apmu_base + APMU_CCIC0, 0x24, &clk_lock); mmp2_clk_init()
428 10, 5, 0, &clk_lock); mmp2_clk_init()
432 apmu_base + APMU_CCIC0, 0x300, &clk_lock); mmp2_clk_init()
438 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock); mmp2_clk_init()
443 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); mmp2_clk_init()
447 apmu_base + APMU_CCIC1, 0x1b, &clk_lock); mmp2_clk_init()
451 apmu_base + APMU_CCIC1, 0x24, &clk_lock); mmp2_clk_init()
456 10, 5, 0, &clk_lock); mmp2_clk_init()
460 apmu_base + APMU_CCIC1, 0x300, &clk_lock); mmp2_clk_init()
H A Dclk-pxa168.c48 static DEFINE_SPINLOCK(clk_lock);
161 ARRAY_SIZE(uart_factor_tbl), &clk_lock); pxa168_clk_init()
166 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); pxa168_clk_init()
170 apbc_base + APBC_TWSI1, 10, 0, &clk_lock); pxa168_clk_init()
174 apbc_base + APBC_GPIO, 10, 0, &clk_lock); pxa168_clk_init()
178 apbc_base + APBC_KPC, 10, 0, &clk_lock); pxa168_clk_init()
182 apbc_base + APBC_RTC, 10, 0, &clk_lock); pxa168_clk_init()
186 apbc_base + APBC_PWM0, 10, 0, &clk_lock); pxa168_clk_init()
190 apbc_base + APBC_PWM1, 10, 0, &clk_lock); pxa168_clk_init()
194 apbc_base + APBC_PWM2, 10, 0, &clk_lock); pxa168_clk_init()
198 apbc_base + APBC_PWM3, 10, 0, &clk_lock); pxa168_clk_init()
204 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); pxa168_clk_init()
209 apbc_base + APBC_UART0, 10, 0, &clk_lock); pxa168_clk_init()
215 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); pxa168_clk_init()
220 apbc_base + APBC_UART1, 10, 0, &clk_lock); pxa168_clk_init()
226 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); pxa168_clk_init()
231 apbc_base + APBC_UART2, 10, 0, &clk_lock); pxa168_clk_init()
237 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); pxa168_clk_init()
241 10, 0, &clk_lock); pxa168_clk_init()
247 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); pxa168_clk_init()
251 10, 0, &clk_lock); pxa168_clk_init()
257 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); pxa168_clk_init()
261 10, 0, &clk_lock); pxa168_clk_init()
267 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); pxa168_clk_init()
271 10, 0, &clk_lock); pxa168_clk_init()
277 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock); pxa168_clk_init()
281 10, 0, &clk_lock); pxa168_clk_init()
285 0x19b, &clk_lock); pxa168_clk_init()
291 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); pxa168_clk_init()
295 0x1b, &clk_lock); pxa168_clk_init()
301 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); pxa168_clk_init()
305 0x1b, &clk_lock); pxa168_clk_init()
309 0x9, &clk_lock); pxa168_clk_init()
313 0x12, &clk_lock); pxa168_clk_init()
319 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); pxa168_clk_init()
323 apmu_base + APMU_DISP0, 0x1b, &clk_lock); pxa168_clk_init()
327 apmu_base + APMU_DISP0, 0x24, &clk_lock); pxa168_clk_init()
333 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); pxa168_clk_init()
337 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); pxa168_clk_init()
343 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); pxa168_clk_init()
347 apmu_base + APMU_CCIC0, 0x24, &clk_lock); pxa168_clk_init()
352 10, 5, 0, &clk_lock); pxa168_clk_init()
356 apmu_base + APMU_CCIC0, 0x300, &clk_lock); pxa168_clk_init()
H A Dclk-pxa910.c46 static DEFINE_SPINLOCK(clk_lock);
166 ARRAY_SIZE(uart_factor_tbl), &clk_lock); pxa910_clk_init()
171 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); pxa910_clk_init()
175 apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock); pxa910_clk_init()
179 apbc_base + APBC_GPIO, 10, 0, &clk_lock); pxa910_clk_init()
183 apbc_base + APBC_KPC, 10, 0, &clk_lock); pxa910_clk_init()
187 apbc_base + APBC_RTC, 10, 0, &clk_lock); pxa910_clk_init()
191 apbc_base + APBC_PWM0, 10, 0, &clk_lock); pxa910_clk_init()
195 apbc_base + APBC_PWM1, 10, 0, &clk_lock); pxa910_clk_init()
199 apbc_base + APBC_PWM2, 10, 0, &clk_lock); pxa910_clk_init()
203 apbc_base + APBC_PWM3, 10, 0, &clk_lock); pxa910_clk_init()
209 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); pxa910_clk_init()
214 apbc_base + APBC_UART0, 10, 0, &clk_lock); pxa910_clk_init()
220 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); pxa910_clk_init()
225 apbc_base + APBC_UART1, 10, 0, &clk_lock); pxa910_clk_init()
231 apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock); pxa910_clk_init()
236 apbcp_base + APBCP_UART2, 10, 0, &clk_lock); pxa910_clk_init()
242 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); pxa910_clk_init()
246 apbc_base + APBC_SSP0, 10, 0, &clk_lock); pxa910_clk_init()
252 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); pxa910_clk_init()
256 apbc_base + APBC_SSP1, 10, 0, &clk_lock); pxa910_clk_init()
260 apmu_base + APMU_DFC, 0x19b, &clk_lock); pxa910_clk_init()
266 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); pxa910_clk_init()
270 apmu_base + APMU_SDH0, 0x1b, &clk_lock); pxa910_clk_init()
276 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); pxa910_clk_init()
280 apmu_base + APMU_SDH1, 0x1b, &clk_lock); pxa910_clk_init()
284 apmu_base + APMU_USB, 0x9, &clk_lock); pxa910_clk_init()
288 apmu_base + APMU_USB, 0x12, &clk_lock); pxa910_clk_init()
294 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); pxa910_clk_init()
298 apmu_base + APMU_DISP0, 0x1b, &clk_lock); pxa910_clk_init()
304 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); pxa910_clk_init()
308 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); pxa910_clk_init()
314 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); pxa910_clk_init()
318 apmu_base + APMU_CCIC0, 0x24, &clk_lock); pxa910_clk_init()
323 10, 5, 0, &clk_lock); pxa910_clk_init()
327 apmu_base + APMU_CCIC0, 0x300, &clk_lock); pxa910_clk_init()
/linux-4.1.27/arch/m68k/coldfire/
H A Dclk.c22 static DEFINE_SPINLOCK(clk_lock);
92 spin_lock_irqsave(&clk_lock, flags); clk_enable()
95 spin_unlock_irqrestore(&clk_lock, flags); clk_enable()
104 spin_lock_irqsave(&clk_lock, flags); clk_disable()
107 spin_unlock_irqrestore(&clk_lock, flags); clk_disable()
/linux-4.1.27/arch/avr32/mach-at32ap/
H A Dclock.c28 static DEFINE_SPINLOCK(clk_lock);
86 spin_lock_irqsave(&clk_lock, flags); clk_enable()
88 spin_unlock_irqrestore(&clk_lock, flags); clk_enable()
115 spin_lock_irqsave(&clk_lock, flags); clk_disable()
117 spin_unlock_irqrestore(&clk_lock, flags); clk_disable()
129 spin_lock_irqsave(&clk_lock, flags); clk_get_rate()
131 spin_unlock_irqrestore(&clk_lock, flags); clk_get_rate()
147 spin_lock_irqsave(&clk_lock, flags); clk_round_rate()
149 spin_unlock_irqrestore(&clk_lock, flags); clk_round_rate()
166 spin_lock_irqsave(&clk_lock, flags); clk_set_rate()
168 spin_unlock_irqrestore(&clk_lock, flags); clk_set_rate()
185 spin_lock_irqsave(&clk_lock, flags); clk_set_parent()
187 spin_unlock_irqrestore(&clk_lock, flags); clk_set_parent()
/linux-4.1.27/drivers/media/v4l2-core/
H A Dv4l2-clk.c24 static DEFINE_MUTEX(clk_lock);
57 mutex_lock(&clk_lock); v4l2_clk_get()
62 mutex_unlock(&clk_lock); v4l2_clk_get()
81 mutex_lock(&clk_lock); v4l2_clk_put()
87 mutex_unlock(&clk_lock); v4l2_clk_put()
96 mutex_lock(&clk_lock); v4l2_clk_lock_driver()
106 mutex_unlock(&clk_lock); v4l2_clk_lock_driver()
244 mutex_lock(&clk_lock); v4l2_clk_register()
246 mutex_unlock(&clk_lock); v4l2_clk_register()
251 mutex_unlock(&clk_lock); v4l2_clk_register()
270 mutex_lock(&clk_lock); v4l2_clk_unregister()
272 mutex_unlock(&clk_lock); v4l2_clk_unregister()
/linux-4.1.27/drivers/clk/rockchip/
H A Dclk.c153 static DEFINE_SPINLOCK(clk_lock);
201 list->pll_flags, &clk_lock); rockchip_clk_register_plls()
230 list->mux_flags, &clk_lock); rockchip_clk_register_branches()
239 &clk_lock); rockchip_clk_register_branches()
245 list->div_flags, &clk_lock); rockchip_clk_register_branches()
252 list->gate_flags, flags, &clk_lock); rockchip_clk_register_branches()
260 list->gate_shift, list->gate_flags, &clk_lock); rockchip_clk_register_branches()
270 list->gate_flags, flags, &clk_lock); rockchip_clk_register_branches()
310 &clk_lock); rockchip_clk_register_armclk()
H A Dclk-rockchip.c21 static DEFINE_SPINLOCK(clk_lock);
85 &clk_lock); rk2928_gate_clk_init()
/linux-4.1.27/drivers/mmc/core/
H A Dhost.c81 spin_lock_irqsave(&host->clk_lock, flags); clkgate_delay_store()
83 spin_unlock_irqrestore(&host->clk_lock, flags); clkgate_delay_store()
111 spin_lock_irqsave(&host->clk_lock, flags); mmc_host_clk_gate_delayed()
119 spin_unlock_irqrestore(&host->clk_lock, flags); mmc_host_clk_gate_delayed()
124 spin_unlock_irqrestore(&host->clk_lock, flags); mmc_host_clk_gate_delayed()
128 spin_lock_irqsave(&host->clk_lock, flags); mmc_host_clk_gate_delayed()
130 spin_unlock_irqrestore(&host->clk_lock, flags); mmc_host_clk_gate_delayed()
133 spin_lock_irqsave(&host->clk_lock, flags); mmc_host_clk_gate_delayed()
136 spin_unlock_irqrestore(&host->clk_lock, flags); mmc_host_clk_gate_delayed()
166 spin_lock_irqsave(&host->clk_lock, flags); mmc_host_clk_hold()
168 spin_unlock_irqrestore(&host->clk_lock, flags); mmc_host_clk_hold()
170 spin_lock_irqsave(&host->clk_lock, flags); mmc_host_clk_hold()
174 spin_unlock_irqrestore(&host->clk_lock, flags); mmc_host_clk_hold()
210 spin_lock_irqsave(&host->clk_lock, flags); mmc_host_clk_release()
216 spin_unlock_irqrestore(&host->clk_lock, flags); mmc_host_clk_release()
230 spin_lock_irqsave(&host->clk_lock, flags); mmc_host_clk_rate()
235 spin_unlock_irqrestore(&host->clk_lock, flags); mmc_host_clk_rate()
255 spin_lock_init(&host->clk_lock); mmc_host_clk_init()
H A Dcore.c1047 spin_lock_irqsave(&host->clk_lock, flags); mmc_gate_clock()
1051 spin_unlock_irqrestore(&host->clk_lock, flags); mmc_gate_clock()
1083 spin_lock_irqsave(&host->clk_lock, flags); mmc_set_ungated()
1085 spin_unlock_irqrestore(&host->clk_lock, flags); mmc_set_ungated()
/linux-4.1.27/sound/soc/samsung/
H A Ds3c24xx_uda134x.c46 static DEFINE_MUTEX(clk_lock);
66 mutex_lock(&clk_lock); s3c24xx_uda134x_startup()
97 mutex_unlock(&clk_lock); s3c24xx_uda134x_startup()
113 mutex_lock(&clk_lock); s3c24xx_uda134x_shutdown()
122 mutex_unlock(&clk_lock); s3c24xx_uda134x_shutdown()
/linux-4.1.27/sound/firewire/bebob/
H A Dbebob_maudio.c84 unsigned int clk_lock; member in struct:special_params
165 * clk_lock: 0x00:unlock, 0x01:lock
170 unsigned int clk_lock) avc_maudio_set_special_clk()
193 buf[9] = 0xff & clk_lock; /* lock these settings */ avc_maudio_set_special_clk()
213 params->clk_lock = buf[9]; avc_maudio_set_special_clk()
382 params->clk_lock); special_clk_ctl_put()
494 params->clk_lock); special_dig_in_iface_ctl_set()
562 id, params->clk_lock); special_dig_out_iface_ctl_set()
168 avc_maudio_set_special_clk(struct snd_bebob *bebob, unsigned int clk_src, unsigned int dig_in_fmt, unsigned int dig_out_fmt, unsigned int clk_lock) avc_maudio_set_special_clk() argument
/linux-4.1.27/arch/arm/mach-ep93xx/
H A Dclock.c237 static DEFINE_SPINLOCK(clk_lock);
265 spin_lock_irqsave(&clk_lock, flags); clk_enable()
267 spin_unlock_irqrestore(&clk_lock, flags); clk_enable()
299 spin_lock_irqsave(&clk_lock, flags); clk_disable()
301 spin_unlock_irqrestore(&clk_lock, flags); clk_disable()
/linux-4.1.27/drivers/clk/sunxi/
H A Dclk-sunxi.c27 static DEFINE_SPINLOCK(clk_lock);
167 spin_lock_irqsave(&clk_lock, flags); sun6i_ahb1_clk_set_rate()
179 spin_unlock_irqrestore(&clk_lock, flags); sun6i_ahb1_clk_set_rate()
223 mux->lock = &clk_lock; sun6i_ahb1_clk_setup()
757 return sunxi_factors_register(node, data, &clk_lock, reg); sunxi_factors_clk_setup()
800 0, &clk_lock); sunxi_mux_clk_setup()
882 data->table, &clk_lock); sunxi_divider_clk_setup()
1030 0, &clk_lock); sunxi_gates_clk_setup()
1183 gate->lock = &clk_lock; sunxi_divs_clk_setup()
1210 divider->lock = &clk_lock; sunxi_divs_clk_setup()
/linux-4.1.27/include/linux/mfd/arizona/
H A Dcore.h133 struct mutex clk_lock; member in struct:arizona
/linux-4.1.27/drivers/mfd/
H A Darizona-core.c42 mutex_lock(&arizona->clk_lock); arizona_clk32k_enable()
64 mutex_unlock(&arizona->clk_lock); arizona_clk32k_enable()
74 mutex_lock(&arizona->clk_lock); arizona_clk32k_disable()
91 mutex_unlock(&arizona->clk_lock); arizona_clk32k_disable()
672 mutex_init(&arizona->clk_lock); arizona_dev_init()
/linux-4.1.27/drivers/clk/
H A Dclk-xgene.c43 static DEFINE_SPINLOCK(clk_lock);
180 CLK_IS_ROOT, reg, 0, pll_type, &clk_lock); xgene_pllclk_init()
501 of_clk_get_parent_name(np, 0), &parameters, &clk_lock); xgene_devclk_init()
/linux-4.1.27/drivers/mmc/host/
H A Domap.c167 spinlock_t clk_lock; /* for changing enabled state */ member in struct:mmc_omap_host
189 spin_lock_irqsave(&host->clk_lock, flags); mmc_omap_fclk_enable()
197 spin_unlock_irqrestore(&host->clk_lock, flags); mmc_omap_fclk_enable()
1358 spin_lock_init(&host->clk_lock); mmc_omap_probe()
/linux-4.1.27/drivers/media/platform/soc_camera/
H A Dsoc_camera.c187 mutex_lock(&ici->clk_lock); soc_camera_clock_start()
189 mutex_unlock(&ici->clk_lock); soc_camera_clock_start()
199 mutex_lock(&ici->clk_lock); soc_camera_clock_stop()
201 mutex_unlock(&ici->clk_lock); soc_camera_clock_stop()
1979 mutex_init(&ici->clk_lock); soc_camera_host_register()
/linux-4.1.27/include/media/
H A Dsoc_camera.h82 struct mutex clk_lock; /* Protect pipeline modifications */ member in struct:soc_camera_host
/linux-4.1.27/include/linux/mmc/
H A Dhost.h297 spinlock_t clk_lock; /* lock for clk fields */ member in struct:mmc_host

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