55 static DEFINE_SPINLOCK(clk_lock);
194 				ARRAY_SIZE(uart_factor_tbl), &clk_lock);  in mmp2_clk_init()
199 				apbc_base + APBC_TWSI0, 10, 0, &clk_lock);  in mmp2_clk_init()
203 				apbc_base + APBC_TWSI1, 10, 0, &clk_lock);  in mmp2_clk_init()
207 				apbc_base + APBC_TWSI2, 10, 0, &clk_lock);  in mmp2_clk_init()
211 				apbc_base + APBC_TWSI3, 10, 0, &clk_lock);  in mmp2_clk_init()
215 				apbc_base + APBC_TWSI4, 10, 0, &clk_lock);  in mmp2_clk_init()
219 				apbc_base + APBC_TWSI5, 10, 0, &clk_lock);  in mmp2_clk_init()
223 				apbc_base + APBC_GPIO, 10, 0, &clk_lock);  in mmp2_clk_init()
227 				apbc_base + APBC_KPC, 10, 0, &clk_lock);  in mmp2_clk_init()
231 				apbc_base + APBC_RTC, 10, 0, &clk_lock);  in mmp2_clk_init()
235 				apbc_base + APBC_PWM0, 10, 0, &clk_lock);  in mmp2_clk_init()
239 				apbc_base + APBC_PWM1, 10, 0, &clk_lock);  in mmp2_clk_init()
243 				apbc_base + APBC_PWM2, 10, 0, &clk_lock);  in mmp2_clk_init()
247 				apbc_base + APBC_PWM3, 10, 0, &clk_lock);  in mmp2_clk_init()
253 				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
258 				apbc_base + APBC_UART0, 10, 0, &clk_lock);  in mmp2_clk_init()
264 				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
269 				apbc_base + APBC_UART1, 10, 0, &clk_lock);  in mmp2_clk_init()
275 				apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
280 				apbc_base + APBC_UART2, 10, 0, &clk_lock);  in mmp2_clk_init()
286 				apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
291 				apbc_base + APBC_UART3, 10, 0, &clk_lock);  in mmp2_clk_init()
297 				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
301 				apbc_base + APBC_SSP0, 10, 0, &clk_lock);  in mmp2_clk_init()
307 				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
311 				apbc_base + APBC_SSP1, 10, 0, &clk_lock);  in mmp2_clk_init()
317 				apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
321 				apbc_base + APBC_SSP2, 10, 0, &clk_lock);  in mmp2_clk_init()
327 				apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
331 				apbc_base + APBC_SSP3, 10, 0, &clk_lock);  in mmp2_clk_init()
337 				apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);  in mmp2_clk_init()
342 				10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);  in mmp2_clk_init()
346 				0x1b, &clk_lock);  in mmp2_clk_init()
350 				0x1b, &clk_lock);  in mmp2_clk_init()
354 				0x1b, &clk_lock);  in mmp2_clk_init()
358 				0x1b, &clk_lock);  in mmp2_clk_init()
362 				0x9, &clk_lock);  in mmp2_clk_init()
368 				apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
373 				8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);  in mmp2_clk_init()
377 				apmu_base + APMU_DISP0, 0x1b, &clk_lock);  in mmp2_clk_init()
381 				apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);  in mmp2_clk_init()
385 				apmu_base + APMU_DISP0, 0x1024, &clk_lock);  in mmp2_clk_init()
391 				apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
396 				8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);  in mmp2_clk_init()
400 				apmu_base + APMU_DISP1, 0x1b, &clk_lock);  in mmp2_clk_init()
404 				apmu_base + APMU_CCIC0, 0x1800, &clk_lock);  in mmp2_clk_init()
410 				apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
415 				17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);  in mmp2_clk_init()
419 				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);  in mmp2_clk_init()
423 				apmu_base + APMU_CCIC0, 0x24, &clk_lock);  in mmp2_clk_init()
428 				10, 5, 0, &clk_lock);  in mmp2_clk_init()
432 				apmu_base + APMU_CCIC0, 0x300, &clk_lock);  in mmp2_clk_init()
438 				apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
443 				16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);  in mmp2_clk_init()
447 				apmu_base + APMU_CCIC1, 0x1b, &clk_lock);  in mmp2_clk_init()
451 				apmu_base + APMU_CCIC1, 0x24, &clk_lock);  in mmp2_clk_init()
456 				10, 5, 0, &clk_lock);  in mmp2_clk_init()
460 				apmu_base + APMU_CCIC1, 0x300, &clk_lock);  in mmp2_clk_init()