48 static DEFINE_SPINLOCK(clk_lock);
161 				ARRAY_SIZE(uart_factor_tbl), &clk_lock);  in pxa168_clk_init()
166 				apbc_base + APBC_TWSI0, 10, 0, &clk_lock);  in pxa168_clk_init()
170 				apbc_base + APBC_TWSI1, 10, 0, &clk_lock);  in pxa168_clk_init()
174 				apbc_base + APBC_GPIO, 10, 0, &clk_lock);  in pxa168_clk_init()
178 				apbc_base + APBC_KPC, 10, 0, &clk_lock);  in pxa168_clk_init()
182 				apbc_base + APBC_RTC, 10, 0, &clk_lock);  in pxa168_clk_init()
186 				apbc_base + APBC_PWM0, 10, 0, &clk_lock);  in pxa168_clk_init()
190 				apbc_base + APBC_PWM1, 10, 0, &clk_lock);  in pxa168_clk_init()
194 				apbc_base + APBC_PWM2, 10, 0, &clk_lock);  in pxa168_clk_init()
198 				apbc_base + APBC_PWM3, 10, 0, &clk_lock);  in pxa168_clk_init()
204 				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
209 				apbc_base + APBC_UART0, 10, 0, &clk_lock);  in pxa168_clk_init()
215 				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
220 				apbc_base + APBC_UART1,	10, 0, &clk_lock);  in pxa168_clk_init()
226 				apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
231 				apbc_base + APBC_UART2,	10, 0, &clk_lock);  in pxa168_clk_init()
237 				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
241 				10, 0, &clk_lock);  in pxa168_clk_init()
247 				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
251 				10, 0, &clk_lock);  in pxa168_clk_init()
257 				apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
261 				10, 0, &clk_lock);  in pxa168_clk_init()
267 				apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
271 				10, 0, &clk_lock);  in pxa168_clk_init()
277 				apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
281 				10, 0, &clk_lock);  in pxa168_clk_init()
285 				0x19b, &clk_lock);  in pxa168_clk_init()
291 				apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);  in pxa168_clk_init()
295 				0x1b, &clk_lock);  in pxa168_clk_init()
301 				apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);  in pxa168_clk_init()
305 				0x1b, &clk_lock);  in pxa168_clk_init()
309 				0x9, &clk_lock);  in pxa168_clk_init()
313 				0x12, &clk_lock);  in pxa168_clk_init()
319 				apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);  in pxa168_clk_init()
323 				apmu_base + APMU_DISP0, 0x1b, &clk_lock);  in pxa168_clk_init()
327 				apmu_base + APMU_DISP0, 0x24, &clk_lock);  in pxa168_clk_init()
333 				apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);  in pxa168_clk_init()
337 				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);  in pxa168_clk_init()
343 				apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);  in pxa168_clk_init()
347 				apmu_base + APMU_CCIC0, 0x24, &clk_lock);  in pxa168_clk_init()
352 				10, 5, 0, &clk_lock);  in pxa168_clk_init()
356 				apmu_base + APMU_CCIC0, 0x300, &clk_lock);  in pxa168_clk_init()