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Searched refs:clk_base (Results 1 – 15 of 15) sorted by relevance

/linux-4.1.27/drivers/clk/tegra/
Dclk-tegra-super-gen4.c53 static void __init tegra_sclk_init(void __iomem *clk_base, in tegra_sclk_init() argument
65 clk_base + SCLK_BURST_POLICY, in tegra_sclk_init()
74 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, in tegra_sclk_init()
78 clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
89 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, in tegra_sclk_init()
92 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
97 void __init tegra_super_clk_gen4_init(void __iomem *clk_base, in tegra_super_clk_gen4_init() argument
111 clk_base + CCLKG_BURST_POLICY, in tegra_super_clk_gen4_init()
122 clk_base + CCLKLP_BURST_POLICY, in tegra_super_clk_gen4_init()
127 tegra_sclk_init(clk_base, tegra_clks); in tegra_super_clk_gen4_init()
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Dclk-tegra20.c140 static void __iomem *clk_base; variable
585 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); in tegra20_clk_measure_input_freq()
619 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & in tegra20_get_pll_ref_div()
641 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
647 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
650 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra20_pll_init()
655 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
662 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
665 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra20_pll_init()
670 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
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Dclk-tegra114.c169 static void __iomem *clk_base; variable
943 static void __init tegra114_fixed_clk_init(void __iomem *clk_base) in tegra114_fixed_clk_init() argument
964 static __init void tegra114_utmi_param_configure(void __iomem *clk_base) in tegra114_utmi_param_configure() argument
980 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra114_utmi_param_configure()
997 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra114_utmi_param_configure()
1000 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
1015 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
1018 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1022 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1024 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
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Dclk-tegra30.c174 static void __iomem *clk_base; variable
883 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra30_utmi_param_configure()
900 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra30_utmi_param_configure()
903 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra30_utmi_param_configure()
918 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra30_utmi_param_configure()
928 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
934 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
937 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra30_pll_init()
942 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, in tegra30_pll_init()
949 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
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Dclk-periph-gate.c32 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
34 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
36 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
39 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
41 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
88 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
89 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
91 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
132 const char *parent_name, u8 gate_flags, void __iomem *clk_base, in tegra_clk_register_periph_gate() argument
157 gate->clk_base = clk_base; in tegra_clk_register_periph_gate()
Dclk-tegra124.c132 static void __iomem *clk_base; variable
1024 static void tegra124_utmi_param_configure(void __iomem *clk_base) in tegra124_utmi_param_configure() argument
1040 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra124_utmi_param_configure()
1057 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra124_utmi_param_configure()
1060 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
1075 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
1078 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra124_utmi_param_configure()
1082 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra124_utmi_param_configure()
1084 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
1087 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
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Dclk.h241 void __iomem *clk_base; member
264 void __iomem *clk_base, void __iomem *pmc,
269 void __iomem *clk_base, void __iomem *pmc,
274 void __iomem *clk_base, void __iomem *pmc,
280 void __iomem *clk_base, void __iomem *pmc,
286 void __iomem *clk_base, void __iomem *pmc,
292 void __iomem *clk_base, void __iomem *pmc,
299 void __iomem *clk_base, unsigned long flags,
304 void __iomem *clk_base, unsigned long flags,
379 void __iomem *clk_base; member
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Dclk-tegra-audio.c127 void __init tegra_audio_clk_init(void __iomem *clk_base, in tegra_audio_clk_init() argument
138 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, in tegra_audio_clk_init()
147 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra_audio_clk_init()
150 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra_audio_clk_init()
180 clk_base + data->offset, 0, 3, 0, in tegra_audio_clk_init()
189 0, clk_base + data->offset, 4, in tegra_audio_clk_init()
205 data->name_2x, clk_base + AUDIO_SYNC_DOUBLER, in tegra_audio_clk_init()
210 clk_base, CLK_SET_RATE_PARENT, data->clk_num, in tegra_audio_clk_init()
Dclk-periph.c144 void __iomem *clk_base, u32 offset, in _tegra_clk_register_periph() argument
172 periph->mux.reg = clk_base + offset; in _tegra_clk_register_periph()
173 periph->divider.reg = div ? (clk_base + offset) : NULL; in _tegra_clk_register_periph()
174 periph->gate.clk_base = clk_base; in _tegra_clk_register_periph()
191 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph() argument
195 periph, clk_base, offset, flags); in tegra_clk_register_periph()
200 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph_nodiv() argument
205 periph, clk_base, offset, CLK_SET_RATE_PARENT); in tegra_clk_register_periph_nodiv()
Dclk-pll.c186 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
191 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
249 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
771 val = readl(pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
774 writel(val, pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
839 void __iomem *clk_base, in _setup_dynamic_ramp() argument
869 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); in _setup_dynamic_ramp()
1414 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, in _tegra_init_pll() argument
1424 pll->clk_base = clk_base; in _tegra_init_pll()
1455 void __iomem *clk_base, void __iomem *pmc, in tegra_clk_register_pll() argument
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Dclk-tegra-periph.c582 static void __init periph_clk_init(void __iomem *clk_base, in periph_clk_init() argument
606 &data->periph, clk_base, data->offset, in periph_clk_init()
612 static void __init gate_clk_init(void __iomem *clk_base, in gate_clk_init() argument
630 clk_base, data->flags, in gate_clk_init()
637 static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, in init_pllp() argument
648 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, in init_pllp()
664 clk_base + data->offset, 0, data->div_flags, in init_pllp()
667 data->div_name, clk_base + data->offset, in init_pllp()
675 void __init tegra_periph_clk_init(void __iomem *clk_base, in tegra_periph_clk_init() argument
679 init_pllp(clk_base, pmc_base, tegra_clks, pll_params); in tegra_periph_clk_init()
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Dclk.c141 static void __iomem *clk_base; variable
156 clk_base + periph_regs[id / 32].rst_set_reg); in tegra_clk_rst_assert()
165 clk_base + periph_regs[id / 32].rst_clr_reg); in tegra_clk_rst_deassert()
184 clk_base = regs; in tegra_clk_init()
Dclk-tegra-fixed.c33 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, in tegra_osc_clk_init() argument
43 val = readl_relaxed(clk_base + OSC_CTRL); in tegra_osc_clk_init()
/linux-4.1.27/arch/arm/mach-prima2/
Dplatsmp.c23 static void __iomem *clk_base; variable
57 clk_base = of_iomap(np, 0); in sirfsoc_boot_secondary()
58 if (!clk_base) in sirfsoc_boot_secondary()
69 clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET); in sirfsoc_boot_secondary()
73 clk_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET); in sirfsoc_boot_secondary()
/linux-4.1.27/drivers/cpufreq/
Ds5pv210-cpufreq.c25 static void __iomem *clk_base; variable
28 #define S5P_CLKREG(x) (clk_base + (x))
609 clk_base = of_iomap(np, 0); in s5pv210_cpufreq_probe()
610 if (!clk_base) { in s5pv210_cpufreq_probe()