174 static void __iomem *clk_base;  variable
883 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);  in tegra30_utmi_param_configure()
900 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);  in tegra30_utmi_param_configure()
903 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);  in tegra30_utmi_param_configure()
918 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);  in tegra30_utmi_param_configure()
928 	clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
934 				clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra30_pll_init()
937 				clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,  in tegra30_pll_init()
942 	clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,  in tegra30_pll_init()
949 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra30_pll_init()
952 				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |  in tegra30_pll_init()
957 	clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
967 	clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
974 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
984 	clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
997 			       clk_base + PLLE_AUX, 2, 1, 0, NULL);  in tegra30_pll_init()
998 	clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,  in tegra30_pll_init()
1023 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
1032 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
1041 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
1049 				  clk_base + CCLKG_BURST_POLICY,  in tegra30_super_clk_init()
1058 				clk_base + SUPER_CCLKLP_DIVIDER, 0,  in tegra30_super_clk_init()
1067 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
1076 				clk_base + SUPER_CCLKLP_DIVIDER, 0,  in tegra30_super_clk_init()
1084 				  clk_base + CCLKLP_BURST_POLICY,  in tegra30_super_clk_init()
1093 				  clk_base + SCLK_BURST_POLICY,  in tegra30_super_clk_init()
1102 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);  in tegra30_super_clk_init()
1142 	clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,  in tegra30_periph_clk_init()
1147 	clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,  in tegra30_periph_clk_init()
1152 	clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,  in tegra30_periph_clk_init()
1160 			       clk_base + CLK_SOURCE_EMC,  in tegra30_periph_clk_init()
1162 	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,  in tegra30_periph_clk_init()
1166 	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,  in tegra30_periph_clk_init()
1171 	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,  in tegra30_periph_clk_init()
1176 	clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,  in tegra30_periph_clk_init()
1184 				clk_base, data->offset, data->flags);  in tegra30_periph_clk_init()
1193 					clk_base, data->offset);  in tegra30_periph_clk_init()
1197 	tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);  in tegra30_periph_clk_init()
1206 		reg = readl(clk_base +  in tegra30_wait_cpu_in_reset()
1217 	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);  in tegra30_put_cpu_in_reset()
1224 	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);  in tegra30_cpu_out_of_reset()
1234 	       clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);  in tegra30_enable_cpu_clock()
1235 	reg = readl(clk_base +  in tegra30_enable_cpu_clock()
1244 	reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra30_disable_cpu_clock()
1246 	       clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra30_disable_cpu_clock()
1255 	cpu_rst_status = readl(clk_base +  in tegra30_cpu_rail_off_ready()
1271 				readl(clk_base + CLK_RESET_SOURCE_CSITE);  in tegra30_cpu_clock_suspend()
1272 	writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE);  in tegra30_cpu_clock_suspend()
1275 				readl(clk_base + CLK_RESET_CCLK_BURST);  in tegra30_cpu_clock_suspend()
1277 				readl(clk_base + CLK_RESET_PLLX_BASE);  in tegra30_cpu_clock_suspend()
1279 				readl(clk_base + CLK_RESET_PLLX_MISC);  in tegra30_cpu_clock_suspend()
1281 				readl(clk_base + CLK_RESET_CCLK_DIVIDER);  in tegra30_cpu_clock_suspend()
1289 	reg = readl(clk_base + CLK_RESET_CCLK_BURST);  in tegra30_cpu_clock_resume()
1302 					clk_base + CLK_RESET_PLLX_MISC);  in tegra30_cpu_clock_resume()
1304 					clk_base + CLK_RESET_PLLX_BASE);  in tegra30_cpu_clock_resume()
1316 					clk_base + CLK_RESET_CCLK_DIVIDER);  in tegra30_cpu_clock_resume()
1318 					clk_base + CLK_RESET_CCLK_BURST);  in tegra30_cpu_clock_resume()
1321 					clk_base + CLK_RESET_SOURCE_CSITE);  in tegra30_cpu_clock_resume()
1413 	clk_base = of_iomap(np, 0);  in tegra30_clock_init()
1414 	if (!clk_base) {  in tegra30_clock_init()
1431 	clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,  in tegra30_clock_init()
1436 	if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,  in tegra30_clock_init()
1446 	tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, &pll_a_params);  in tegra30_clock_init()