140 static void __iomem *clk_base;  variable
585 	u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);  in tegra20_clk_measure_input_freq()
619 	u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &  in tegra20_get_pll_ref_div()
641 	clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,  in tegra20_pll_init()
647 				clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra20_pll_init()
650 				clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,  in tegra20_pll_init()
655 	clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,  in tegra20_pll_init()
662 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra20_pll_init()
665 				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |  in tegra20_pll_init()
670 	clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,  in tegra20_pll_init()
675 	clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,  in tegra20_pll_init()
680 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,  in tegra20_pll_init()
690 	clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,  in tegra20_pll_init()
696 				clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra20_pll_init()
699 				clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |  in tegra20_pll_init()
704 	clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,  in tegra20_pll_init()
723 			      clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL);  in tegra20_super_clk_init()
729 			      clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);  in tegra20_super_clk_init()
749 				clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);  in tegra20_audio_clk_init()
751 				clk_base + AUDIO_SYNC_CLK, 4,  in tegra20_audio_clk_init()
759 				    TEGRA_PERIPH_NO_RESET, clk_base,  in tegra20_audio_clk_init()
811 				    clk_base, 0, 3, periph_clk_enb_refcnt);  in tegra20_periph_clk_init()
815 	clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,  in tegra20_periph_clk_init()
823 			       clk_base + CLK_SOURCE_EMC,  in tegra20_periph_clk_init()
825 	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,  in tegra20_periph_clk_init()
829 	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,  in tegra20_periph_clk_init()
834 	clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,  in tegra20_periph_clk_init()
840 	clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,  in tegra20_periph_clk_init()
848 				    clk_base, 0, 94, periph_clk_enb_refcnt);  in tegra20_periph_clk_init()
855 				    clk_base, 0, 93, periph_clk_enb_refcnt);  in tegra20_periph_clk_init()
862 				clk_base, data->offset, data->flags);  in tegra20_periph_clk_init()
871 					clk_base, data->offset);  in tegra20_periph_clk_init()
875 	tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);  in tegra20_periph_clk_init()
904 		reg = readl(clk_base +  in tegra20_wait_cpu_in_reset()
915 	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);  in tegra20_put_cpu_in_reset()
922 	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);  in tegra20_cpu_out_of_reset()
930 	reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra20_enable_cpu_clock()
932 	       clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra20_enable_cpu_clock()
934 	reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra20_enable_cpu_clock()
941 	reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra20_disable_cpu_clock()
943 	       clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra20_disable_cpu_clock()
951 	cpu_rst_status = readl(clk_base +  in tegra20_cpu_rail_off_ready()
961 				readl(clk_base + CLK_SOURCE_CSITE);  in tegra20_cpu_clock_suspend()
962 	writel(3<<30, clk_base + CLK_SOURCE_CSITE);  in tegra20_cpu_clock_suspend()
965 				readl(clk_base + CCLK_BURST_POLICY);  in tegra20_cpu_clock_suspend()
967 				readl(clk_base + PLLX_BASE);  in tegra20_cpu_clock_suspend()
969 				readl(clk_base + PLLX_MISC);  in tegra20_cpu_clock_suspend()
971 				readl(clk_base + SUPER_CCLK_DIVIDER);  in tegra20_cpu_clock_suspend()
979 	reg = readl(clk_base + CCLK_BURST_POLICY);  in tegra20_cpu_clock_resume()
992 					clk_base + PLLX_MISC);  in tegra20_cpu_clock_resume()
994 					clk_base + PLLX_BASE);  in tegra20_cpu_clock_resume()
1006 					clk_base + SUPER_CCLK_DIVIDER);  in tegra20_cpu_clock_resume()
1008 					clk_base + CCLK_BURST_POLICY);  in tegra20_cpu_clock_resume()
1011 					clk_base + CLK_SOURCE_CSITE);  in tegra20_cpu_clock_resume()
1096 	clk_base = of_iomap(np, 0);  in tegra20_clock_init()
1097 	if (!clk_base) {  in tegra20_clock_init()
1114 	clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,  in tegra20_clock_init()
1123 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);  in tegra20_clock_init()