132 static void __iomem *clk_base;  variable
1024 static void tegra124_utmi_param_configure(void __iomem *clk_base)  in tegra124_utmi_param_configure()  argument
1040 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);  in tegra124_utmi_param_configure()
1057 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);  in tegra124_utmi_param_configure()
1060 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);  in tegra124_utmi_param_configure()
1075 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);  in tegra124_utmi_param_configure()
1078 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1082 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1084 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);  in tegra124_utmi_param_configure()
1087 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);  in tegra124_utmi_param_configure()
1093 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1096 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1101 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1103 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1106 static __init void tegra124_periph_clk_init(void __iomem *clk_base,  in tegra124_periph_clk_init()  argument
1117 				clk_base + PLLD_MISC, 30, 0, &pll_d_lock);  in tegra124_periph_clk_init()
1121 					     clk_base, 0, 48,  in tegra124_periph_clk_init()
1126 					     clk_base, 0, 82,  in tegra124_periph_clk_init()
1133 			       clk_base + CLK_SOURCE_EMC,  in tegra124_periph_clk_init()
1136 	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,  in tegra124_periph_clk_init()
1141 	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,  in tegra124_periph_clk_init()
1147 	clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,  in tegra124_periph_clk_init()
1152 	tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);  in tegra124_periph_clk_init()
1155 static void __init tegra124_pll_init(void __iomem *clk_base,  in tegra124_pll_init()  argument
1162 	clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,  in tegra124_pll_init()
1169 			clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra124_pll_init()
1172 				clk_base + PLLC_OUT, 1, 0,  in tegra124_pll_init()
1184 	clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1190 	clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1196 	clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,  in tegra124_pll_init()
1204 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra124_pll_init()
1207 				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |  in tegra124_pll_init()
1219 	val = readl(clk_base + pll_u_params.base_reg);  in tegra124_pll_init()
1221 	writel(val, clk_base + pll_u_params.base_reg);  in tegra124_pll_init()
1223 	clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1228 	tegra124_utmi_param_configure(clk_base);  in tegra124_pll_init()
1232 				CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,  in tegra124_pll_init()
1256 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1268 	clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,  in tegra124_pll_init()
1274 					 clk_base + PLLRE_BASE, 16, 4, 0,  in tegra124_pll_init()
1281 				      clk_base, 0, &pll_e_params, NULL);  in tegra124_pll_init()
1286 	clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1292 	clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1298 	clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1317 		reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);  in tegra124_wait_cpu_in_reset()
1332 				readl(clk_base + CLK_SOURCE_CSITE);  in tegra124_cpu_clock_suspend()
1333 	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);  in tegra124_cpu_clock_suspend()
1339 				clk_base + CLK_SOURCE_CSITE);  in tegra124_cpu_clock_resume()
1459 	clk_base = of_iomap(np, 0);  in tegra124_132_clock_init_pre()
1460 	if (!clk_base) {  in tegra124_132_clock_init_pre()
1479 	clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,  in tegra124_132_clock_init_pre()
1484 	if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,  in tegra124_132_clock_init_pre()
1490 	tegra124_pll_init(clk_base, pmc_base);  in tegra124_132_clock_init_pre()
1491 	tegra124_periph_clk_init(clk_base, pmc_base);  in tegra124_132_clock_init_pre()
1492 	tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);  in tegra124_132_clock_init_pre()
1496 	plld_base = clk_readl(clk_base + PLLD_BASE);  in tegra124_132_clock_init_pre()
1498 	clk_writel(plld_base, clk_base + PLLD_BASE);  in tegra124_132_clock_init_pre()
1513 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,  in tegra124_132_clock_init_post()