Searched refs:bits (Results 1 - 200 of 7440) sorted by relevance

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/linux-4.1.27/arch/sparc/include/asm/
H A Dpcic.h49 #define PCI_DIAGNOSTIC_0 0x40 /* 32 bits */
50 #define PCI_SIZE_0 0x44 /* 32 bits */
51 #define PCI_SIZE_1 0x48 /* 32 bits */
52 #define PCI_SIZE_2 0x4c /* 32 bits */
53 #define PCI_SIZE_3 0x50 /* 32 bits */
54 #define PCI_SIZE_4 0x54 /* 32 bits */
55 #define PCI_SIZE_5 0x58 /* 32 bits */
56 #define PCI_PIO_CONTROL 0x60 /* 8 bits */
57 #define PCI_DVMA_CONTROL 0x62 /* 8 bits */
62 #define PCI_INTERRUPT_CONTROL 0x63 /* 8 bits */
63 #define PCI_CPU_INTERRUPT_PENDING 0x64 /* 32 bits */
64 #define PCI_DIAGNOSTIC_1 0x68 /* 16 bits */
65 #define PCI_SOFTWARE_INT_CLEAR 0x6a /* 16 bits */
66 #define PCI_SOFTWARE_INT_SET 0x6e /* 16 bits */
67 #define PCI_SYS_INT_PENDING 0x70 /* 32 bits */
72 #define PCI_SYS_INT_TARGET_MASK 0x74 /* 32 bits */
73 #define PCI_SYS_INT_TARGET_MASK_CLEAR 0x78 /* 32 bits */
74 #define PCI_SYS_INT_TARGET_MASK_SET 0x7c /* 32 bits */
75 #define PCI_SYS_INT_PENDING_CLEAR 0x83 /* 8 bits */
80 #define PCI_IOTLB_CONTROL 0x84 /* 8 bits */
81 #define PCI_INT_SELECT_LO 0x88 /* 16 bits */
82 #define PCI_ARBITRATION_SELECT 0x8a /* 16 bits */
83 #define PCI_INT_SELECT_HI 0x8c /* 16 bits */
84 #define PCI_HW_INT_OUTPUT 0x8e /* 16 bits */
85 #define PCI_IOTLB_RAM_INPUT 0x90 /* 32 bits */
86 #define PCI_IOTLB_CAM_INPUT 0x94 /* 32 bits */
87 #define PCI_IOTLB_RAM_OUTPUT 0x98 /* 32 bits */
88 #define PCI_IOTLB_CAM_OUTPUT 0x9c /* 32 bits */
89 #define PCI_SMBAR0 0xa0 /* 8 bits */
90 #define PCI_MSIZE0 0xa1 /* 8 bits */
91 #define PCI_PMBAR0 0xa2 /* 8 bits */
92 #define PCI_SMBAR1 0xa4 /* 8 bits */
93 #define PCI_MSIZE1 0xa5 /* 8 bits */
94 #define PCI_PMBAR1 0xa6 /* 8 bits */
95 #define PCI_SIBAR 0xa8 /* 8 bits */
97 #define PCI_ISIZE 0xa9 /* 8 bits */
103 #define PCI_PIBAR 0xaa /* 8 bits */
104 #define PCI_CPU_COUNTER_LIMIT_HI 0xac /* 32 bits */
105 #define PCI_CPU_COUNTER_LIMIT_LO 0xb0 /* 32 bits */
106 #define PCI_CPU_COUNTER_LIMIT 0xb4 /* 32 bits */
107 #define PCI_SYS_LIMIT 0xb8 /* 32 bits */
108 #define PCI_SYS_COUNTER 0xbc /* 32 bits */
110 #define PCI_SYS_LIMIT_PSEUDO 0xc0 /* 32 bits */
111 #define PCI_USER_TIMER_CONTROL 0xc4 /* 8 bits */
112 #define PCI_USER_TIMER_CONFIG 0xc5 /* 8 bits */
113 #define PCI_COUNTER_IRQ 0xc6 /* 8 bits */
118 #define PCI_PIO_ERROR_COMMAND 0xc7 /* 8 bits */
119 #define PCI_PIO_ERROR_ADDRESS 0xc8 /* 32 bits */
120 #define PCI_IOTLB_ERROR_ADDRESS 0xcc /* 32 bits */
121 #define PCI_SYS_STATUS 0xd0 /* 8 bits */
H A Dns87303.h28 /* Function Enable Register (FER) bits */
31 /* Function Address Register (FAR) bits */
37 /* Power and Test Register (PTR) bits */
43 /* Function Control Register (FCR) bits */
47 /* Printer Control Register (PCR) bits */
56 /* Tape UARTs and Parallel Port Config Register (TUP) bits */
59 /* Advanced SuperIO Config Register (ASC) bits */
/linux-4.1.27/arch/alpha/include/asm/
H A Dword-at-a-time.h21 static inline unsigned long has_zero(unsigned long val, unsigned long *bits, const struct word_at_a_time *c) has_zero() argument
24 *bits = zero_locations; has_zero()
28 static inline unsigned long prep_zero_mask(unsigned long val, unsigned long bits, const struct word_at_a_time *c) prep_zero_mask() argument
30 return bits; prep_zero_mask()
33 #define create_zero_mask(bits) (bits)
35 static inline unsigned long find_zero(unsigned long bits) find_zero() argument
39 return __kernel_cttz(bits); find_zero()
43 bits &= -bits; find_zero()
45 t1 = bits & 0xf0; find_zero()
46 t2 = bits & 0xcc; find_zero()
47 t3 = bits & 0xaa; find_zero()
H A Dsocket.h6 /* O_NONBLOCK clashes with the bits used for socket types. Therefore we
/linux-4.1.27/tools/perf/util/
H A Dpmu.y26 %type <bits> bit_term
27 %type <bits> bits
32 DECLARE_BITMAP(bits, PERF_PMU_FORMAT_BITS);
43 PP_CONFIG ':' bits
50 PP_CONFIG1 ':' bits
57 PP_CONFIG2 ':' bits
64 bits: label
65 bits ',' bit_term
H A Dbitmap.c10 int __bitmap_weight(const unsigned long *bitmap, int bits) __bitmap_weight() argument
12 int k, w = 0, lim = bits/BITS_PER_LONG; __bitmap_weight()
17 if (bits % BITS_PER_LONG) __bitmap_weight()
18 w += hweight_long(bitmap[k] & BITMAP_LAST_WORD_MASK(bits)); __bitmap_weight()
24 const unsigned long *bitmap2, int bits) __bitmap_or()
27 int nr = BITS_TO_LONGS(bits); __bitmap_or()
23 __bitmap_or(unsigned long *dst, const unsigned long *bitmap1, const unsigned long *bitmap2, int bits) __bitmap_or() argument
/linux-4.1.27/include/sound/
H A Dcs8403.h39 SND_CS8403_DECL void SND_CS8403_DECODE(struct snd_aes_iec958 *diga, unsigned char bits) SND_CS8403_DECODE() argument
41 if (bits & 0x01) { /* consumer */ SND_CS8403_DECODE()
42 if (!(bits & 0x02)) SND_CS8403_DECODE()
44 if (!(bits & 0x08)) SND_CS8403_DECODE()
46 switch (bits & 0x10) { SND_CS8403_DECODE()
50 if (!(bits & 0x80)) SND_CS8403_DECODE()
52 switch (bits & 0x60) { SND_CS8403_DECODE()
58 switch (bits & 0x06) { SND_CS8403_DECODE()
65 switch (bits & 0x18) { SND_CS8403_DECODE()
71 switch (bits & 0x60) { SND_CS8403_DECODE()
77 if (bits & 0x80) SND_CS8403_DECODE()
84 unsigned char bits; SND_CS8403_ENCODE() local
87 bits = 0x01; /* consumer mode */ SND_CS8403_ENCODE()
89 bits &= ~0x02; SND_CS8403_ENCODE()
91 bits |= 0x02; SND_CS8403_ENCODE()
93 bits &= ~0x08; SND_CS8403_ENCODE()
95 bits |= 0x08; SND_CS8403_ENCODE()
98 case IEC958_AES0_CON_EMPHASIS_NONE: bits |= 0x10; break; SND_CS8403_ENCODE()
99 case IEC958_AES0_CON_EMPHASIS_5015: bits |= 0x00; break; SND_CS8403_ENCODE()
102 bits &= ~0x80; SND_CS8403_ENCODE()
104 bits |= 0x80; SND_CS8403_ENCODE()
106 bits |= 0x60; SND_CS8403_ENCODE()
110 bits |= 0x00; break; SND_CS8403_ENCODE()
112 bits |= 0x20; break; SND_CS8403_ENCODE()
115 bits |= 0x40; break; SND_CS8403_ENCODE()
120 case IEC958_AES3_CON_FS_44100: bits |= 0x00; break; SND_CS8403_ENCODE()
121 case IEC958_AES3_CON_FS_48000: bits |= 0x02; break; SND_CS8403_ENCODE()
122 case IEC958_AES3_CON_FS_32000: bits |= 0x04; break; SND_CS8403_ENCODE()
125 bits = 0x00; /* professional mode */ SND_CS8403_ENCODE()
127 bits &= ~0x02; SND_CS8403_ENCODE()
129 bits |= 0x02; SND_CS8403_ENCODE()
132 case IEC958_AES0_PRO_FS_32000: bits |= 0x00; break; SND_CS8403_ENCODE()
133 case IEC958_AES0_PRO_FS_44100: bits |= 0x10; break; /* 44.1kHz */ SND_CS8403_ENCODE()
134 case IEC958_AES0_PRO_FS_48000: bits |= 0x08; break; /* 48kHz */ SND_CS8403_ENCODE()
136 case IEC958_AES0_PRO_FS_NOTID: bits |= 0x18; break; SND_CS8403_ENCODE()
139 case IEC958_AES0_PRO_EMPHASIS_NONE: bits |= 0x20; break; SND_CS8403_ENCODE()
140 case IEC958_AES0_PRO_EMPHASIS_5015: bits |= 0x40; break; SND_CS8403_ENCODE()
141 case IEC958_AES0_PRO_EMPHASIS_CCITT: bits |= 0x00; break; SND_CS8403_ENCODE()
143 case IEC958_AES0_PRO_EMPHASIS_NOTID: bits |= 0x60; break; SND_CS8403_ENCODE()
147 case IEC958_AES1_PRO_MODE_STEREOPHONIC: bits |= 0x00; break; SND_CS8403_ENCODE()
148 default: bits |= 0x80; break; SND_CS8403_ENCODE()
151 return bits; SND_CS8403_ENCODE()
169 SND_CS8404_DECL void SND_CS8404_DECODE(struct snd_aes_iec958 *diga, unsigned char bits) SND_CS8404_DECODE() argument
171 if (bits & 0x10) { /* consumer */ SND_CS8404_DECODE()
172 if (!(bits & 0x20)) SND_CS8404_DECODE()
174 if (!(bits & 0x40)) SND_CS8404_DECODE()
176 if (!(bits & 0x80)) SND_CS8404_DECODE()
178 switch (bits & 0x03) { SND_CS8404_DECODE()
182 switch (bits & 0x06) { SND_CS8404_DECODE()
189 if (!(bits & 0x04)) SND_CS8404_DECODE()
191 switch (bits & 0x60) { SND_CS8404_DECODE()
197 switch (bits & 0x03) { SND_CS8404_DECODE()
203 if (!(bits & 0x80)) SND_CS8404_DECODE()
210 unsigned char bits; SND_CS8404_ENCODE() local
213 bits = 0x10; /* consumer mode */ SND_CS8404_ENCODE()
215 bits |= 0x20; SND_CS8404_ENCODE()
217 bits |= 0x40; SND_CS8404_ENCODE()
219 bits |= 0x80; SND_CS8404_ENCODE()
221 bits |= 0x03; SND_CS8404_ENCODE()
224 case IEC958_AES3_CON_FS_44100: bits |= 0x06; break; SND_CS8404_ENCODE()
225 case IEC958_AES3_CON_FS_48000: bits |= 0x04; break; SND_CS8404_ENCODE()
226 case IEC958_AES3_CON_FS_32000: bits |= 0x02; break; SND_CS8404_ENCODE()
229 bits = 0x00; /* professional mode */ SND_CS8404_ENCODE()
231 bits |= 0x04; SND_CS8404_ENCODE()
233 case IEC958_AES0_PRO_FS_32000: bits |= 0x00; break; SND_CS8404_ENCODE()
234 case IEC958_AES0_PRO_FS_44100: bits |= 0x40; break; /* 44.1kHz */ SND_CS8404_ENCODE()
235 case IEC958_AES0_PRO_FS_48000: bits |= 0x20; break; /* 48kHz */ SND_CS8404_ENCODE()
237 case IEC958_AES0_PRO_FS_NOTID: bits |= 0x00; break; SND_CS8404_ENCODE()
240 case IEC958_AES0_PRO_EMPHASIS_NONE: bits |= 0x02; break; SND_CS8404_ENCODE()
241 case IEC958_AES0_PRO_EMPHASIS_5015: bits |= 0x01; break; SND_CS8404_ENCODE()
242 case IEC958_AES0_PRO_EMPHASIS_CCITT: bits |= 0x00; break; SND_CS8404_ENCODE()
244 case IEC958_AES0_PRO_EMPHASIS_NOTID: bits |= 0x03; break; SND_CS8404_ENCODE()
248 case IEC958_AES1_PRO_MODE_STEREOPHONIC: bits |= 0x00; break; SND_CS8404_ENCODE()
249 default: bits |= 0x80; break; SND_CS8404_ENCODE()
252 return bits; SND_CS8404_ENCODE()
H A Dpcm_params.h36 #define SNDRV_MASK_BITS 64 /* we use so far 64bits only */
60 if (mask->bits[i]) snd_mask_empty()
69 if (mask->bits[i]) snd_mask_min()
70 return __ffs(mask->bits[i]) + (i << 5); snd_mask_min()
79 if (mask->bits[i]) snd_mask_max()
80 return __fls(mask->bits[i]) + (i << 5); snd_mask_max()
87 mask->bits[MASK_OFS(val)] |= MASK_BIT(val); snd_mask_set()
92 mask->bits[MASK_OFS(val)] &= ~MASK_BIT(val); snd_mask_reset()
100 mask->bits[MASK_OFS(i)] |= MASK_BIT(i); snd_mask_set_range()
108 mask->bits[MASK_OFS(i)] &= ~MASK_BIT(i); snd_mask_reset_range()
114 v = mask->bits[MASK_OFS(val)] & MASK_BIT(val); snd_mask_leave()
116 mask->bits[MASK_OFS(val)] = v; snd_mask_leave()
124 mask->bits[i] &= v->bits[i]; snd_mask_intersect()
141 return mask->bits[MASK_OFS(val)] & MASK_BIT(val); snd_mask_test()
148 if (! mask->bits[i]) snd_mask_single()
150 if (mask->bits[i] & (mask->bits[i] - 1)) snd_mask_single()
345 * params_width - get the number of bits of the sample format from the hw params
348 * This function returns the number of bits per sample that the selected sample
360 * This functions returns the number of bits per sample that the selected sample
/linux-4.1.27/arch/sh/include/asm/
H A Dword-at-a-time.h26 static inline unsigned long has_zero(unsigned long a, unsigned long *bits, const struct word_at_a_time *c) has_zero() argument
29 *bits = mask; has_zero()
33 static inline unsigned long prep_zero_mask(unsigned long a, unsigned long bits, const struct word_at_a_time *c) prep_zero_mask() argument
35 return bits; prep_zero_mask()
38 static inline unsigned long create_zero_mask(unsigned long bits) create_zero_mask() argument
40 bits = (bits - 1) & ~bits; create_zero_mask()
41 return bits >> 7; create_zero_mask()
H A Dpgtable-2level.h11 /* PTE bits */
17 /* PGD bits */
H A Dsyscalls_64.h12 /* Misc syscall related bits */
/linux-4.1.27/drivers/media/radio/si470x/
H A Dradio-si470x.h54 #define DEVICEID_PN 0xf000 /* bits 15..12: Part Number */
55 #define DEVICEID_MFGID 0x0fff /* bits 11..00: Manufacturer ID */
58 #define CHIPID_REV 0xfc00 /* bits 15..10: Chip Version */
59 #define CHIPID_DEV 0x0200 /* bits 09..09: Device */
60 #define CHIPID_FIRMWARE 0x01ff /* bits 08..00: Firmware Version */
63 #define POWERCFG_DSMUTE 0x8000 /* bits 15..15: Softmute Disable */
64 #define POWERCFG_DMUTE 0x4000 /* bits 14..14: Mute Disable */
65 #define POWERCFG_MONO 0x2000 /* bits 13..13: Mono Select */
66 #define POWERCFG_RDSM 0x0800 /* bits 11..11: RDS Mode (Si4701 only) */
67 #define POWERCFG_SKMODE 0x0400 /* bits 10..10: Seek Mode */
68 #define POWERCFG_SEEKUP 0x0200 /* bits 09..09: Seek Direction */
69 #define POWERCFG_SEEK 0x0100 /* bits 08..08: Seek */
70 #define POWERCFG_DISABLE 0x0040 /* bits 06..06: Powerup Disable */
71 #define POWERCFG_ENABLE 0x0001 /* bits 00..00: Powerup Enable */
74 #define CHANNEL_TUNE 0x8000 /* bits 15..15: Tune */
75 #define CHANNEL_CHAN 0x03ff /* bits 09..00: Channel Select */
78 #define SYSCONFIG1_RDSIEN 0x8000 /* bits 15..15: RDS Interrupt Enable (Si4701 only) */
79 #define SYSCONFIG1_STCIEN 0x4000 /* bits 14..14: Seek/Tune Complete Interrupt Enable */
80 #define SYSCONFIG1_RDS 0x1000 /* bits 12..12: RDS Enable (Si4701 only) */
81 #define SYSCONFIG1_DE 0x0800 /* bits 11..11: De-emphasis (0=75us 1=50us) */
82 #define SYSCONFIG1_AGCD 0x0400 /* bits 10..10: AGC Disable */
83 #define SYSCONFIG1_BLNDADJ 0x00c0 /* bits 07..06: Stereo/Mono Blend Level Adjustment */
84 #define SYSCONFIG1_GPIO3 0x0030 /* bits 05..04: General Purpose I/O 3 */
85 #define SYSCONFIG1_GPIO2 0x000c /* bits 03..02: General Purpose I/O 2 */
86 #define SYSCONFIG1_GPIO1 0x0003 /* bits 01..00: General Purpose I/O 1 */
89 #define SYSCONFIG2_SEEKTH 0xff00 /* bits 15..08: RSSI Seek Threshold */
90 #define SYSCONFIG2_BAND 0x00c0 /* bits 07..06: Band Select */
91 #define SYSCONFIG2_SPACE 0x0030 /* bits 05..04: Channel Spacing */
92 #define SYSCONFIG2_VOLUME 0x000f /* bits 03..00: Volume */
95 #define SYSCONFIG3_SMUTER 0xc000 /* bits 15..14: Softmute Attack/Recover Rate */
96 #define SYSCONFIG3_SMUTEA 0x3000 /* bits 13..12: Softmute Attenuation */
97 #define SYSCONFIG3_SKSNR 0x00f0 /* bits 07..04: Seek SNR Threshold */
98 #define SYSCONFIG3_SKCNT 0x000f /* bits 03..00: Seek FM Impulse Detection Threshold */
101 #define TEST1_AHIZEN 0x4000 /* bits 14..14: Audio High-Z Enable */
104 /* TEST2 only contains reserved bits */
107 /* BOOTCONFIG only contains reserved bits */
110 #define STATUSRSSI_RDSR 0x8000 /* bits 15..15: RDS Ready (Si4701 only) */
111 #define STATUSRSSI_STC 0x4000 /* bits 14..14: Seek/Tune Complete */
112 #define STATUSRSSI_SF 0x2000 /* bits 13..13: Seek Fail/Band Limit */
113 #define STATUSRSSI_AFCRL 0x1000 /* bits 12..12: AFC Rail */
114 #define STATUSRSSI_RDSS 0x0800 /* bits 11..11: RDS Synchronized (Si4701 only) */
115 #define STATUSRSSI_BLERA 0x0600 /* bits 10..09: RDS Block A Errors (Si4701 only) */
116 #define STATUSRSSI_ST 0x0100 /* bits 08..08: Stereo Indicator */
117 #define STATUSRSSI_RSSI 0x00ff /* bits 07..00: RSSI (Received Signal Strength Indicator) */
120 #define READCHAN_BLERB 0xc000 /* bits 15..14: RDS Block D Errors (Si4701 only) */
121 #define READCHAN_BLERC 0x3000 /* bits 13..12: RDS Block C Errors (Si4701 only) */
122 #define READCHAN_BLERD 0x0c00 /* bits 11..10: RDS Block B Errors (Si4701 only) */
123 #define READCHAN_READCHAN 0x03ff /* bits 09..00: Read Channel */
126 #define RDSA_RDSA 0xffff /* bits 15..00: RDS Block A Data (Si4701 only) */
129 #define RDSB_RDSB 0xffff /* bits 15..00: RDS Block B Data (Si4701 only) */
132 #define RDSC_RDSC 0xffff /* bits 15..00: RDS Block C Data (Si4701 only) */
135 #define RDSD_RDSD 0xffff /* bits 15..00: RDS Block D Data (Si4701 only) */
/linux-4.1.27/arch/arm/mach-iop13xx/include/mach/
H A Dhardware.h11 * Generic chipset bits
17 * Board specific bits
/linux-4.1.27/arch/ia64/include/uapi/asm/
H A Dposix_types.h4 typedef unsigned long __kernel_sigset_t; /* at least 32 bits */
/linux-4.1.27/drivers/video/fbdev/core/
H A Dsyscopyarea.c29 const unsigned long *src, unsigned src_idx, int bits, unsigned n) bitcpy()
36 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); bitcpy()
40 if (dst_idx+n <= bits) { bitcpy()
47 /* Leading bits */ bitcpy()
52 n -= bits - dst_idx; bitcpy()
56 n /= bits; bitcpy()
71 /* Trailing bits */ bitcpy()
80 right = shift & (bits - 1); bitcpy()
81 left = -shift & (bits - 1); bitcpy()
83 if (dst_idx+n <= bits) { bitcpy()
90 } else if (src_idx+n <= bits) { bitcpy()
109 /* Leading bits */ bitcpy()
114 n -= bits - dst_idx; bitcpy()
122 n -= bits - dst_idx; bitcpy()
126 m = n % bits; bitcpy()
127 n /= bits; bitcpy()
149 /* Trailing bits */ bitcpy()
151 if (m <= bits - right) { bitcpy()
171 const unsigned long *src, unsigned src_idx, unsigned bits, bitcpy_rev()
177 dst += (dst_idx + n - 1) / bits; bitcpy_rev()
178 src += (src_idx + n - 1) / bits; bitcpy_rev()
179 dst_idx = (dst_idx + n - 1) % bits; bitcpy_rev()
180 src_idx = (src_idx + n - 1) % bits; bitcpy_rev()
184 first = ~FB_SHIFT_HIGH(p, ~0UL, (dst_idx + 1) % bits); bitcpy_rev()
185 last = FB_SHIFT_HIGH(p, ~0UL, (bits + dst_idx + 1 - n) % bits); bitcpy_rev()
197 /* Leading bits */ bitcpy_rev()
206 n /= bits; bitcpy_rev()
220 /* Trailing bits */ bitcpy_rev()
227 int const left = shift & (bits-1); bitcpy_rev()
228 int const right = -shift & (bits-1); bitcpy_rev()
257 /* Leading bits */ bitcpy_rev()
276 m = n % bits; bitcpy_rev()
277 n /= bits; bitcpy_rev()
299 /* Trailing bits */ bitcpy_rev()
301 if (m <= bits - left) { bitcpy_rev()
321 int bits = BITS_PER_LONG, bytes = bits >> 3; sys_copyarea() local
350 bitcpy_rev(p, base + (dst_idx / bits), dst_idx % bits, sys_copyarea()
351 base + (src_idx / bits), src_idx % bits, bits, sys_copyarea()
356 bitcpy(p, base + (dst_idx / bits), dst_idx % bits, sys_copyarea()
357 base + (src_idx / bits), src_idx % bits, bits, sys_copyarea()
28 bitcpy(struct fb_info *p, unsigned long *dst, unsigned dst_idx, const unsigned long *src, unsigned src_idx, int bits, unsigned n) bitcpy() argument
170 bitcpy_rev(struct fb_info *p, unsigned long *dst, unsigned dst_idx, const unsigned long *src, unsigned src_idx, unsigned bits, unsigned n) bitcpy_rev() argument
H A Dcfbcopyarea.c47 const unsigned long __iomem *src, unsigned src_idx, int bits, bitcpy()
58 memmove((char *)dst + ((dst_idx & (bits - 1))) / 8, bitcpy()
59 (char *)src + ((src_idx & (bits - 1))) / 8, n / 8); bitcpy()
64 last = ~fb_shifted_pixels_mask_long(p, (dst_idx+n) % bits, bswapmask); bitcpy()
69 if (dst_idx+n <= bits) { bitcpy()
77 // Leading bits bitcpy()
82 n -= bits - dst_idx; bitcpy()
86 n /= bits; bitcpy()
101 // Trailing bits bitcpy()
110 int const left = shift & (bits - 1); bitcpy()
111 int const right = -shift & (bits - 1); bitcpy()
113 if (dst_idx+n <= bits) { bitcpy()
122 } else if (src_idx+n <= bits) { bitcpy()
142 // Leading bits bitcpy()
147 n -= bits - dst_idx; bitcpy()
154 n -= bits - dst_idx; bitcpy()
162 m = n % bits; bitcpy()
163 n /= bits; bitcpy()
188 // Trailing bits bitcpy()
190 if (m <= bits - right) { bitcpy()
213 const unsigned long __iomem *src, unsigned src_idx, int bits, bitcpy_rev()
224 memmove((char *)dst + ((dst_idx & (bits - 1))) / 8, bitcpy_rev()
225 (char *)src + ((src_idx & (bits - 1))) / 8, n / 8); bitcpy_rev()
229 dst += (dst_idx + n - 1) / bits; bitcpy_rev()
230 src += (src_idx + n - 1) / bits; bitcpy_rev()
231 dst_idx = (dst_idx + n - 1) % bits; bitcpy_rev()
232 src_idx = (src_idx + n - 1) % bits; bitcpy_rev()
236 first = ~fb_shifted_pixels_mask_long(p, (dst_idx + 1) % bits, bswapmask); bitcpy_rev()
237 last = fb_shifted_pixels_mask_long(p, (bits + dst_idx + 1 - n) % bits, bswapmask); bitcpy_rev()
250 // Leading bits bitcpy_rev()
259 n /= bits; bitcpy_rev()
274 // Trailing bits bitcpy_rev()
283 int const left = shift & (bits-1); bitcpy_rev()
284 int const right = -shift & (bits-1); bitcpy_rev()
315 // Leading bits bitcpy_rev()
336 m = n % bits; bitcpy_rev()
337 n /= bits; bitcpy_rev()
362 // Trailing bits bitcpy_rev()
364 if (m <= bits - left) { bitcpy_rev()
387 int bits = BITS_PER_LONG, bytes = bits >> 3; cfb_copyarea() local
417 bitcpy_rev(p, base + (dst_idx / bits), dst_idx % bits, cfb_copyarea()
418 base + (src_idx / bits), src_idx % bits, bits, cfb_copyarea()
423 bitcpy(p, base + (dst_idx / bits), dst_idx % bits, cfb_copyarea()
424 base + (src_idx / bits), src_idx % bits, bits, cfb_copyarea()
46 bitcpy(struct fb_info *p, unsigned long __iomem *dst, unsigned dst_idx, const unsigned long __iomem *src, unsigned src_idx, int bits, unsigned n, u32 bswapmask) bitcpy() argument
212 bitcpy_rev(struct fb_info *p, unsigned long __iomem *dst, unsigned dst_idx, const unsigned long __iomem *src, unsigned src_idx, int bits, unsigned n, u32 bswapmask) bitcpy_rev() argument
H A Dcfbfillrect.c36 unsigned long pat, unsigned n, int bits, u32 bswapmask) bitfill_aligned()
44 last = ~fb_shifted_pixels_mask_long(p, (dst_idx+n) % bits, bswapmask); bitfill_aligned()
46 if (dst_idx+n <= bits) { bitfill_aligned()
54 // Leading bits bitfill_aligned()
58 n -= bits - dst_idx; bitfill_aligned()
62 n /= bits; bitfill_aligned()
77 // Trailing bits bitfill_aligned()
93 unsigned long pat, int left, int right, unsigned n, int bits) bitfill_unaligned()
101 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); bitfill_unaligned()
103 if (dst_idx+n <= bits) { bitfill_unaligned()
110 // Leading bits bitfill_unaligned()
115 n -= bits - dst_idx; bitfill_unaligned()
119 n /= bits; bitfill_unaligned()
136 // Trailing bits bitfill_unaligned()
147 int dst_idx, unsigned long pat, unsigned n, int bits, bitfill_aligned_rev()
157 last = ~fb_shifted_pixels_mask_long(p, (dst_idx+n) % bits, bswapmask); bitfill_aligned_rev()
159 if (dst_idx+n <= bits) { bitfill_aligned_rev()
167 // Leading bits bitfill_aligned_rev()
172 n -= bits - dst_idx; bitfill_aligned_rev()
176 n /= bits; bitfill_aligned_rev()
200 // Trailing bits bitfill_aligned_rev()
219 unsigned n, int bits) bitfill_unaligned_rev()
227 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); bitfill_unaligned_rev()
229 if (dst_idx+n <= bits) { bitfill_unaligned_rev()
238 // Leading bits bitfill_unaligned_rev()
244 n -= bits - dst_idx; bitfill_unaligned_rev()
248 n /= bits; bitfill_unaligned_rev()
270 // Trailing bits bitfill_unaligned_rev()
282 int bits = BITS_PER_LONG, bytes = bits >> 3; cfb_fillrect() local
302 left = bits % bpp; cfb_fillrect()
309 unsigned long pat, unsigned n, int bits, cfb_fillrect()
325 dst += dst_idx >> (ffs(bits) - 1); cfb_fillrect()
326 dst_idx &= (bits - 1); cfb_fillrect()
327 fill_op32(p, dst, dst_idx, pat, width*bpp, bits, cfb_fillrect()
335 int right, unsigned n, int bits) = NULL; cfb_fillrect()
355 dst += dst_idx / bits; cfb_fillrect()
356 dst_idx &= (bits - 1); cfb_fillrect()
361 width*bpp, bits); cfb_fillrect()
35 bitfill_aligned(struct fb_info *p, unsigned long __iomem *dst, int dst_idx, unsigned long pat, unsigned n, int bits, u32 bswapmask) bitfill_aligned() argument
92 bitfill_unaligned(struct fb_info *p, unsigned long __iomem *dst, int dst_idx, unsigned long pat, int left, int right, unsigned n, int bits) bitfill_unaligned() argument
146 bitfill_aligned_rev(struct fb_info *p, unsigned long __iomem *dst, int dst_idx, unsigned long pat, unsigned n, int bits, u32 bswapmask) bitfill_aligned_rev() argument
217 bitfill_unaligned_rev(struct fb_info *p, unsigned long __iomem *dst, int dst_idx, unsigned long pat, int left, int right, unsigned n, int bits) bitfill_unaligned_rev() argument
H A Dsysfillrect.c26 unsigned long pat, unsigned n, int bits) bitfill_aligned()
34 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); bitfill_aligned()
36 if (dst_idx+n <= bits) { bitfill_aligned()
44 /* Leading bits */ bitfill_aligned()
48 n -= bits - dst_idx; bitfill_aligned()
52 n /= bits; bitfill_aligned()
66 /* Trailing bits */ bitfill_aligned()
82 unsigned long pat, int left, int right, unsigned n, int bits) bitfill_unaligned()
90 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); bitfill_unaligned()
92 if (dst_idx+n <= bits) { bitfill_unaligned()
99 /* Leading bits */ bitfill_unaligned()
104 n -= bits - dst_idx; bitfill_unaligned()
108 n /= bits; bitfill_unaligned()
125 /* Trailing bits */ bitfill_unaligned()
136 unsigned long pat, unsigned n, int bits) bitfill_aligned_rev()
145 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); bitfill_aligned_rev()
147 if (dst_idx+n <= bits) { bitfill_aligned_rev()
154 /* Leading bits */ bitfill_aligned_rev()
158 n -= bits - dst_idx; bitfill_aligned_rev()
162 n /= bits; bitfill_aligned_rev()
176 /* Trailing bits */ bitfill_aligned_rev()
193 int bits) bitfill_unaligned_rev()
201 last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits)); bitfill_unaligned_rev()
203 if (dst_idx+n <= bits) { bitfill_unaligned_rev()
211 /* Leading bits */ bitfill_unaligned_rev()
216 n -= bits - dst_idx; bitfill_unaligned_rev()
220 n /= bits; bitfill_unaligned_rev()
237 /* Trailing bits */ bitfill_unaligned_rev()
247 int bits = BITS_PER_LONG, bytes = bits >> 3; sys_fillrect() local
267 left = bits % bpp; sys_fillrect()
273 int bits) = NULL; sys_fillrect()
289 dst += dst_idx >> (ffs(bits) - 1); sys_fillrect()
290 dst_idx &= (bits - 1); sys_fillrect()
291 fill_op32(p, dst, dst_idx, pat, width*bpp, bits); sys_fillrect()
298 int right, unsigned n, int bits) = NULL; sys_fillrect()
319 dst += dst_idx / bits; sys_fillrect()
320 dst_idx &= (bits - 1); sys_fillrect()
325 width*bpp, bits); sys_fillrect()
25 bitfill_aligned(struct fb_info *p, unsigned long *dst, int dst_idx, unsigned long pat, unsigned n, int bits) bitfill_aligned() argument
81 bitfill_unaligned(struct fb_info *p, unsigned long *dst, int dst_idx, unsigned long pat, int left, int right, unsigned n, int bits) bitfill_unaligned() argument
135 bitfill_aligned_rev(struct fb_info *p, unsigned long *dst, int dst_idx, unsigned long pat, unsigned n, int bits) bitfill_aligned_rev() argument
191 bitfill_unaligned_rev(struct fb_info *p, unsigned long *dst, int dst_idx, unsigned long pat, int left, int right, unsigned n, int bits) bitfill_unaligned_rev() argument
/linux-4.1.27/include/linux/netfilter/ipset/
H A Dip_set_bitmap.h17 range_to_mask(u32 from, u32 to, u8 *bits) range_to_mask() argument
21 *bits = 32; range_to_mask()
22 while (--(*bits) > 0 && mask && (to & mask) != from) range_to_mask()
/linux-4.1.27/include/rdma/
H A Dib_smi.h98 u8 linkspeed_portstate; /* 4 bits, 4 bits */
99 u8 portphysstate_linkdown; /* 4 bits, 4 bits */
100 u8 mkeyprot_resv_lmc; /* 2 bits, 3, 3 */
101 u8 linkspeedactive_enabled; /* 4 bits, 4 bits */
102 u8 neighbormtu_mastersmsl; /* 4 bits, 4 bits */
103 u8 vlcap_inittype; /* 4 bits, 4 bits */
107 u8 inittypereply_mtucap; /* 4 bits, 4 bits */
108 u8 vlstallcnt_hoqlife; /* 3 bits, 5 bits */
109 u8 operationalvl_pei_peo_fpi_fpo; /* 4 bits, 1, 1, 1, 1 */
114 u8 clientrereg_resv_subnetto; /* 1 bit, 2 bits, 5 */
115 u8 resv_resptimevalue; /* 3 bits, 5 bits */
116 u8 localphyerrors_overrunerrors; /* 4 bits, 4 bits */
/linux-4.1.27/drivers/net/wireless/zd1211rw/
H A Dzd_rf_rf2959.c44 static int bits(u32 rw, int from, int to)
53 return bits(rw, bit, bit);
58 int reg = bits(rw, 18, 22);
59 int rw_flag = bits(rw, 23, 23);
66 bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
75 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
79 bits(rw, 6, 17), bits(rw, 0, 5));
82 PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
86 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
94 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
98 bits(rw, 6, 17), bits(rw, 0, 5));
101 PDEBUG("reg7 RFPLL3 num2 %d", bits(rw, 0, 17));
105 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
109 bits(rw, 13, 17), bits(rw, 8, 12), bits(rw, 3, 7),
110 bits(rw, 0, 2));
116 bit(rw, 17), bits(rw, 15, 16), bits(rw, 10, 14),
117 bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2),
123 bits(rw, 15, 17), bits(rw, 9, 14), bits(rw, 3, 8),
124 bits(rw, 0, 2));
128 bits(rw, 12, 17), bits(rw, 6, 11), bits(rw, 0, 5));
135 bits(rw, 8, 9), bits(rw, 5, 7), bits(rw, 3, 4),
136 bits(rw, 0, 2));
141 bits(rw, 13, 17), bits(rw, 9, 12), bits(rw, 4, 8),
142 bits(rw, 0, 3));
/linux-4.1.27/arch/parisc/include/asm/
H A Delf.h60 #define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */
61 #define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */
62 #define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */
63 #define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */
65 #define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */
66 #define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */
67 #define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */
68 #define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */
69 #define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */
70 #define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */
71 #define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */
72 #define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */
73 #define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */
74 #define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */
75 #define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */
77 #define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */
78 #define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */
79 #define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */
80 #define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */
81 #define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */
82 #define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */
83 #define R_PARISC_FPTR64 64 /* 64 bits function address. */
84 #define R_PARISC_PLABEL32 65 /* 32 bits function address. */
85 #define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */
86 #define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */
87 #define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */
88 #define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */
89 #define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */
90 #define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */
91 #define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */
92 #define R_PARISC_DIR64 80 /* 64 bits of eff. address. */
93 #define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */
94 #define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */
95 #define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */
96 #define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */
97 #define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */
98 #define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */
99 #define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */
100 #define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */
101 #define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */
102 #define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */
103 #define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */
104 #define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */
105 #define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */
106 #define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */
107 #define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */
108 #define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */
109 #define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */
110 #define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */
111 #define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */
112 #define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */
113 #define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */
114 #define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */
115 #define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */
116 #define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */
117 #define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */
118 #define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */
119 #define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */
120 #define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */
121 #define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */
122 #define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */
127 #define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */
128 #define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */
129 #define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */
130 #define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */
131 #define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/
132 #define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */
133 #define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */
134 #define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */
135 #define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */
136 #define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */
137 #define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */
138 #define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */
139 #define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */
140 #define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/
141 #define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/
142 #define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */
143 #define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */
144 #define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */
278 memset(dst, 0, sizeof(dst)); /* don't leak any "random" bits */ \
H A Dsocket.h6 /* O_NONBLOCK clashes with the bits used for socket types. Therefore we
H A Dsignal.h7 /* bits-per-word, where word apparently means 'long' not 'int' */
16 typedef unsigned long old_sigset_t; /* at least 32 bits */
/linux-4.1.27/drivers/block/drbd/
H A Ddrbd_vli.h41 * gives the number of set or unset bits.
47 * Still, there may be areas where the polarity flips every few bits,
56 * For some cases, we produce more code bits than plaintext input.
88 * Number of data bits follow fibonacci sequence, with the exception of the
90 * encoding bit polarity runlength is 1 plain bits => 2 code bits.
91 prefix data bits max val Nº data bits
119 #................. s ........................... plain bits ..........
124 /* LEVEL: (total bits, prefix bits, prefix value),
125 * sorted ascending by number of total bits.
143 * returns number of bits consumed.
166 /* return number of code bits needed,
217 /* advance cursor by that many bits; maximum expected input value: 64,
219 static inline void bitstream_cursor_advance(struct bitstream_cursor *cur, unsigned int bits) bitstream_cursor_advance() argument
221 bits += cur->bit; bitstream_cursor_advance()
222 cur->b = cur->b + (bits >> 3); bitstream_cursor_advance()
223 cur->bit = bits & 7; bitstream_cursor_advance()
233 * number of trailing 0 bits for padding
234 * total number of valid bits in stream: buf_len * 8 - pad_bits */
252 /* Put (at most 64) least significant bits of val into bitstream, and advance cursor.
254 * Returns zero if bits == 0 (nothing to do).
255 * Returns number of bits used if successful.
260 static inline int bitstream_put_bits(struct bitstream *bs, u64 val, const unsigned int bits) bitstream_put_bits() argument
265 if (bits == 0) bitstream_put_bits()
268 if ((bs->cur.b + ((bs->cur.bit + bits -1) >> 3)) - bs->buf >= bs->buf_len) bitstream_put_bits()
271 /* paranoia: strip off hi bits; they should not be set anyways. */ bitstream_put_bits()
272 if (bits < 64) bitstream_put_bits()
273 val &= ~0ULL >> (64 - bits); bitstream_put_bits()
277 for (tmp = 8 - bs->cur.bit; tmp < bits; tmp += 8) bitstream_put_bits()
280 bitstream_cursor_advance(&bs->cur, bits); bitstream_put_bits()
281 return bits; bitstream_put_bits()
284 /* Fetch (at most 64) bits from bitstream into *out, and advance cursor.
286 * If more than 64 bits are requested, returns -EINVAL and leave *out unchanged.
288 * If there are less than the requested number of valid bits left in the
289 * bitstream, still fetches all available bits.
291 * Returns number of actually fetched bits.
293 static inline int bitstream_get_bits(struct bitstream *bs, u64 *out, int bits) bitstream_get_bits() argument
298 if (bits > 64) bitstream_get_bits()
301 if (bs->cur.b + ((bs->cur.bit + bs->pad_bits + bits -1) >> 3) - bs->buf >= bs->buf_len) bitstream_get_bits()
302 bits = ((bs->buf_len - (bs->cur.b - bs->buf)) << 3) bitstream_get_bits()
305 if (bits == 0) { bitstream_get_bits()
310 /* get the high bits */ bitstream_get_bits()
312 n = (bs->cur.bit + bits + 7) >> 3; bitstream_get_bits()
313 /* n may be at most 9, if cur.bit + bits > 64 */ bitstream_get_bits()
320 /* we still need the low bits */ bitstream_get_bits()
323 /* and mask out bits we don't want */ bitstream_get_bits()
324 val &= ~0ULL >> (64 - bits); bitstream_get_bits()
326 bitstream_cursor_advance(&bs->cur, bits); bitstream_get_bits()
329 return bits; bitstream_get_bits()
335 * > 0: number of bits successfully stored in bitstream
343 int bits = __vli_encode_bits(&code, in); vli_encode_bits() local
345 if (bits <= 0) vli_encode_bits()
346 return bits; vli_encode_bits()
348 return bitstream_put_bits(bs, code, bits); vli_encode_bits()
/linux-4.1.27/fs/jffs2/
H A Dcompr_rubin.c44 int bits[8]; member in struct:rubin_state
88 static void init_rubin(struct rubin_state *rs, int div, int *bits) init_rubin() argument
98 rs->bits[c] = bits[c]; init_rubin()
151 static void init_decode(struct rubin_state *rs, int div, int *bits) init_decode() argument
153 init_rubin(rs, div, bits); init_decode()
168 int c, bits = 0; __do_decode() local
171 * First, work out how many bits we need from the input stream. __do_decode()
176 bits++; __do_decode()
185 rs->bit_number += bits; __do_decode()
188 * Now get the bits. We really want this to be "get n bits". __do_decode()
196 } while (--bits); __do_decode()
237 ret = encode(rs, rs->bit_divider-rs->bits[i], out_byte()
238 rs->bits[i], byte & 1); out_byte()
254 result |= decode(rs, bit_divider - rs->bits[i], in_byte()
255 rs->bits[i]) << i; in_byte()
262 static int rubin_do_compress(int bit_divider, int *bits, unsigned char *data_in, rubin_do_compress() argument
272 init_rubin(&rs, bit_divider, bits); rubin_do_compress()
308 int bits[8]; jffs2_dynrubin_compress() local
323 memset(bits, 0, sizeof(int)*8); jffs2_dynrubin_compress()
326 bits[7] += histo[i]; jffs2_dynrubin_compress()
328 bits[6] += histo[i]; jffs2_dynrubin_compress()
330 bits[5] += histo[i]; jffs2_dynrubin_compress()
332 bits[4] += histo[i]; jffs2_dynrubin_compress()
334 bits[3] += histo[i]; jffs2_dynrubin_compress()
336 bits[2] += histo[i]; jffs2_dynrubin_compress()
338 bits[1] += histo[i]; jffs2_dynrubin_compress()
340 bits[0] += histo[i]; jffs2_dynrubin_compress()
344 bits[i] = (bits[i] * 256) / mysrclen; jffs2_dynrubin_compress()
345 if (!bits[i]) bits[i] = 1; jffs2_dynrubin_compress()
346 if (bits[i] > 255) bits[i] = 255; jffs2_dynrubin_compress()
347 cpage_out[i] = bits[i]; jffs2_dynrubin_compress()
350 ret = rubin_do_compress(256, bits, data_in, cpage_out+8, &mysrclen, jffs2_dynrubin_compress()
368 static void rubin_do_decompress(int bit_divider, int *bits, rubin_do_decompress() argument
377 init_decode(&rs, bit_divider, bits); rubin_do_decompress()
397 int bits[8]; jffs2_dynrubin_decompress() local
401 bits[c] = data_in[c]; jffs2_dynrubin_decompress()
403 rubin_do_decompress(256, bits, data_in+8, cpage_out, sourcelen-8, jffs2_dynrubin_decompress()
/linux-4.1.27/drivers/staging/skein/
H A Dskein_iv.h22 /* blkSize = 256 bits. hashSize = 128 bits */
30 /* blkSize = 256 bits. hashSize = 160 bits */
38 /* blkSize = 256 bits. hashSize = 224 bits */
46 /* blkSize = 256 bits. hashSize = 256 bits */
54 /* blkSize = 512 bits. hashSize = 128 bits */
66 /* blkSize = 512 bits. hashSize = 160 bits */
78 /* blkSize = 512 bits. hashSize = 224 bits */
90 /* blkSize = 512 bits. hashSize = 256 bits */
102 /* blkSize = 512 bits. hashSize = 384 bits */
114 /* blkSize = 512 bits. hashSize = 512 bits */
126 /* blkSize = 1024 bits. hashSize = 384 bits */
146 /* blkSize = 1024 bits. hashSize = 512 bits */
166 /* blkSize = 1024 bits. hashSize = 1024 bits */
H A Dthreefish_api.h63 * the given size. The key data must have the same length (number of bits)
71 * Pointer to the key words (word has 64 bits).
73 * Pointer to the two tweak words (word has 64 bits).
82 * The buffer must have at least the same length (number of bits) as the
83 * state size for this key. The function uses the first @c state_size bits
100 * The buffer must have at least the same length (number of bits) as the
101 * state size for this key. The function uses the first @c state_size bits
105 * The wordsize ist set to 64 bits.
120 * The buffer must have at least the same length (number of bits) as the
121 * state size for this key. The function uses the first @c state_size bits
138 * The buffer must have at least the same length (number of bits) as the
139 * state size for this key. The function uses the first @c state_size bits
143 * The wordsize ist set to 64 bits.
/linux-4.1.27/include/linux/
H A Dhash.h27 #define hash_long(val, bits) hash_32(val, bits)
29 #define hash_long(val, bits) hash_64(val, bits)
51 static __always_inline u64 hash_64(u64 val, unsigned int bits) hash_64() argument
58 /* Sigh, gcc can't optimise this alone like it does for 32 bits. */ hash_64()
74 /* High bits are more random, so use them. */ hash_64()
75 return hash >> (64 - bits); hash_64()
78 static inline u32 hash_32(u32 val, unsigned int bits) hash_32() argument
83 /* High bits are more random, so use them. */ hash_32()
84 return hash >> (32 - bits); hash_32()
87 static inline unsigned long hash_ptr(const void *ptr, unsigned int bits) hash_ptr() argument
89 return hash_long((unsigned long)ptr, bits); hash_ptr()
H A Dacpi_pmtmr.h9 /* limit it to 24 bits */
24 /* mask the output to 24 bits */ acpi_pm_read_early()
H A Dnodemask.h23 * void nodes_setall(mask) set all bits
24 * void nodes_clear(mask) clear all bits
37 * int nodes_empty(mask) Is mask empty (no bits sets)?
38 * int nodes_full(mask) Is mask full (all bits sets)?
39 * int nodes_weight(mask) Hamming weight - number of set bits
50 * NODE_MASK_ALL Initializer - all bits set
51 * NODE_MASK_NONE Initializer - no bits set
59 * void nodes_fold(dst, orig, sz) dst bits = orig bits mod sz
95 typedef struct { DECLARE_BITMAP(bits, MAX_NUMNODES); } nodemask_t;
104 #define nodemask_pr_args(maskp) MAX_NUMNODES, (maskp)->bits
118 set_bit(node, dstp->bits); __node_set()
124 clear_bit(node, dstp->bits); __node_clear()
130 bitmap_fill(dstp->bits, nbits); __nodes_setall()
136 bitmap_zero(dstp->bits, nbits); __nodes_clear()
140 #define node_isset(node, nodemask) test_bit((node), (nodemask).bits)
146 return test_and_set_bit(node, addr->bits); __node_test_and_set()
154 bitmap_and(dstp->bits, src1p->bits, src2p->bits, nbits); __nodes_and()
162 bitmap_or(dstp->bits, src1p->bits, src2p->bits, nbits); __nodes_or()
170 bitmap_xor(dstp->bits, src1p->bits, src2p->bits, nbits); __nodes_xor()
178 bitmap_andnot(dstp->bits, src1p->bits, src2p->bits, nbits); __nodes_andnot()
186 bitmap_complement(dstp->bits, srcp->bits, nbits); __nodes_complement()
194 return bitmap_equal(src1p->bits, src2p->bits, nbits); __nodes_equal()
202 return bitmap_intersects(src1p->bits, src2p->bits, nbits); __nodes_intersects()
210 return bitmap_subset(src1p->bits, src2p->bits, nbits); __nodes_subset()
216 return bitmap_empty(srcp->bits, nbits); __nodes_empty()
222 return bitmap_full(srcp->bits, nbits); __nodes_full()
228 return bitmap_weight(srcp->bits, nbits); __nodes_weight()
236 bitmap_shift_right(dstp->bits, srcp->bits, n, nbits); __nodes_shift_right()
244 bitmap_shift_left(dstp->bits, srcp->bits, n, nbits); __nodes_shift_left()
253 return min_t(int, MAX_NUMNODES, find_first_bit(srcp->bits, MAX_NUMNODES)); __first_node()
259 return min_t(int,MAX_NUMNODES,find_next_bit(srcp->bits, MAX_NUMNODES, n+1)); __next_node()
272 m.bits[0] = 1UL << (node); \
283 find_first_zero_bit(maskp->bits, MAX_NUMNODES)); __first_unset_node()
310 #define nodes_addr(src) ((src).bits)
317 return bitmap_parse_user(buf, len, dstp->bits, nbits); __nodemask_parse_user()
323 return bitmap_parselist(buf, dstp->bits, nbits); __nodelist_parse()
331 return bitmap_bitremap(oldbit, oldp->bits, newp->bits, nbits); __node_remap()
339 bitmap_remap(dstp->bits, srcp->bits, oldp->bits, newp->bits, nbits); __nodes_remap()
347 bitmap_onto(dstp->bits, origp->bits, relmapp->bits, nbits); __nodes_onto()
355 bitmap_fold(dstp->bits, origp->bits, sz, nbits); __nodes_fold()
H A Damifdreg.h5 ** CIAAPRA bits (read only)
14 ** CIAAPRB bits (read/write)
27 ** DSKBYTR bits (read only)
34 /* bits 7-0 are data */
37 ** ADKCON/ADKCONR bits
51 ** DSKLEN bits
58 ** INTENA/INTREQ bits
H A Dvia.h19 /* Mask for parallel port IRQ bits (in ISA PnP IRQ routing register 1) */
21 /* Mask for parallel port DMA bits (in ISA PnP DMA routing register) */
H A Dhtirq.h5 u32 address_lo; /* low 32 bits of the ht irq message */
6 u32 address_hi; /* high 32 bits of the it irq message */
H A Dcryptohash.h7 #define SHA_MESSAGE_BYTES (512 /*bits*/ / 8)
H A Dbasic_mmio_gpio.h40 /* Number of bits (GPIOs): <register width> * 8. */
41 int bits; member in struct:bgpio_chip
44 * Some GPIO controllers work with the big-endian bits notation,
45 * e.g. in a 8-bits register, GPIO7 is the least significant bit.
55 /* Shadowed data register to clear/set bits safely. */
/linux-4.1.27/lib/zlib_inflate/
H A Dinffast.c65 state->bits < 8
75 - The maximum input bits used by a length/distance pair is 15 bits for the
76 length code, 5 bits for the length extra, 15 bits for the distance code,
77 and 13 bits for the distance extra. This totals 48 bits, or six bytes.
104 unsigned bits; /* local strm->bits */ inflate_fast() local
110 unsigned op; /* code bits, operation, extra bits, or */ inflate_fast()
131 bits = state->bits; inflate_fast()
140 if (bits < 15) { inflate_fast()
141 hold += (unsigned long)(PUP(in)) << bits; inflate_fast()
142 bits += 8; inflate_fast()
143 hold += (unsigned long)(PUP(in)) << bits; inflate_fast()
144 bits += 8; inflate_fast()
148 op = (unsigned)(this.bits); inflate_fast()
150 bits -= op; inflate_fast()
157 op &= 15; /* number of extra bits */ inflate_fast()
159 if (bits < op) { inflate_fast()
160 hold += (unsigned long)(PUP(in)) << bits; inflate_fast()
161 bits += 8; inflate_fast()
165 bits -= op; inflate_fast()
167 if (bits < 15) { inflate_fast()
168 hold += (unsigned long)(PUP(in)) << bits; inflate_fast()
169 bits += 8; inflate_fast()
170 hold += (unsigned long)(PUP(in)) << bits; inflate_fast()
171 bits += 8; inflate_fast()
175 op = (unsigned)(this.bits); inflate_fast()
177 bits -= op; inflate_fast()
181 op &= 15; /* number of extra bits */ inflate_fast()
182 if (bits < op) { inflate_fast()
183 hold += (unsigned long)(PUP(in)) << bits; inflate_fast()
184 bits += 8; inflate_fast()
185 if (bits < op) { inflate_fast()
186 hold += (unsigned long)(PUP(in)) << bits; inflate_fast()
187 bits += 8; inflate_fast()
199 bits -= op; inflate_fast()
332 /* return unused bytes (on entry, bits < 8, so in won't go too far back) */ inflate_fast()
333 len = bits >> 3; inflate_fast()
335 bits -= len << 3; inflate_fast()
336 hold &= (1U << bits) - 1; inflate_fast()
345 state->bits = bits; inflate_fast()
352 - Different op definition to avoid & for extra bits (do & for table bits)
H A Dinftrees.h17 table that indexes more bits of the code. op indicates whether
20 pointer, the low four bits of op is the number of index bits of
21 that table. For a length or distance, the low four bits of op
22 is the number of extra bits to get after the code. bits is
23 the number of bits in this code or part of the code to drop off
28 unsigned char op; /* operation, extra bits, table bits */
29 unsigned char bits; /* bits in this part of the code */ member in struct:__anon14048
35 0000tttt - table link, tttt != 0 is the number of table index bits
36 0001eeee - length or distance, eeee is the number of extra bits
58 unsigned *bits, unsigned short *work);
H A Dinftrees.c14 whose indices are 0..2^bits-1. work is a writable array of at least
18 on return points to the next available entry's address. bits is the
19 requested root table index bits, and on return it is the actual root
20 table index bits. It will differ if the request is greater than the
24 code **table, unsigned *bits, unsigned short *work) zlib_inflate_table()
26 unsigned len; /* a code's length in bits */ zlib_inflate_table()
29 unsigned root; /* number of index bits for root table */ zlib_inflate_table()
30 unsigned curr; /* number of index bits for current table */ zlib_inflate_table()
31 unsigned drop; /* code bits to drop for sub-table */ zlib_inflate_table()
37 unsigned low; /* low bits for current root entry */ zlib_inflate_table()
38 unsigned mask; /* mask for low root bits */ zlib_inflate_table()
42 const unsigned short *extra; /* extra bits table to use */ zlib_inflate_table()
66 for codes with equal lengths. Then the code starts with all zero bits zlib_inflate_table()
69 increases. For the deflate format, these bits are stored backwards zlib_inflate_table()
99 root = *bits; zlib_inflate_table()
105 this.bits = (unsigned char)1; zlib_inflate_table()
109 *bits = 1; zlib_inflate_table()
137 filled is at next and has curr index bits. The code being used is huff zlib_inflate_table()
139 bits off of the bottom. For codes where len is less than drop + curr, zlib_inflate_table()
140 those top drop + curr - len bits are incremented through all values to zlib_inflate_table()
143 root is the number of index bits for the root table. When len exceeds zlib_inflate_table()
145 of the low root bits of huff. This is saved in low to check for when a zlib_inflate_table()
159 This assumes that when type == LENS, bits == 9. zlib_inflate_table()
191 curr = root; /* current table index bits */ zlib_inflate_table()
192 drop = 0; /* current bits to drop from code for index */ zlib_inflate_table()
204 this.bits = (unsigned char)(len - drop); zlib_inflate_table()
218 /* replicate for those indices with low len bits equal to huff */ zlib_inflate_table()
272 (*table)[low].bits = (unsigned char)root; zlib_inflate_table()
281 through high index bits. When the current sub-table is filled, the loop zlib_inflate_table()
285 this.bits = (unsigned char)(len - drop); zlib_inflate_table()
293 this.bits = (unsigned char)len; zlib_inflate_table()
313 *bits = root; zlib_inflate_table()
23 zlib_inflate_table(codetype type, unsigned short *lens, unsigned codes, code **table, unsigned *bits, unsigned short *work) zlib_inflate_table() argument
/linux-4.1.27/arch/arm/include/asm/
H A Dword-at-a-time.h18 static inline unsigned long has_zero(unsigned long a, unsigned long *bits, has_zero() argument
22 *bits = mask; has_zero()
26 #define prep_zero_mask(a, bits, c) (bits)
28 static inline unsigned long create_zero_mask(unsigned long bits) create_zero_mask() argument
30 bits = (bits - 1) & ~bits; create_zero_mask()
31 return bits >> 7; create_zero_mask()
H A Dsparsemem.h9 * MAX_PHYSMEM_BITS: The number of physical address bits required
12 * SECTION_SIZE_BITS: The number of physical address bits to cover
H A Dsignal.h13 typedef unsigned long old_sigset_t; /* at least 32 bits */
H A Dvfp.h16 /* FPSID bits */
33 /* FPEXC bits */
50 /* FPSCR bits */
76 /* MVFR0 bits */
/linux-4.1.27/drivers/cpufreq/
H A Dpowernow-k7.h23 } bits; member in union:msr_fidvidctl
41 } bits; member in union:msr_fidvidstatus
H A Dpowernow-k7.c65 } bits; member in union:powernow_acpi_control_t
188 powernow_table[j].driver_data = fid; /* lower 8 bits */ get_ranges()
205 powernow_table[j].driver_data |= (vid << 8); /* upper 8 bits */ get_ranges()
225 if (fidvidctl.bits.FID != fid) { change_FID()
226 fidvidctl.bits.SGTC = latency; change_FID()
227 fidvidctl.bits.FID = fid; change_FID()
228 fidvidctl.bits.VIDC = 0; change_FID()
229 fidvidctl.bits.FIDC = 1; change_FID()
240 if (fidvidctl.bits.VID != vid) { change_VID()
241 fidvidctl.bits.SGTC = latency; change_VID()
242 fidvidctl.bits.VID = vid; change_VID()
243 fidvidctl.bits.FIDC = 0; change_VID()
244 fidvidctl.bits.VIDC = 1; change_VID()
257 /* fid are the lower 8 bits of the index we stored into powernow_target()
259 * vid are the upper 8 bits. powernow_target()
266 cfid = fidvidstatus.bits.CFID; powernow_target()
366 pc.bits.sgtc); powernow_acpi_init()
368 vid = pc.bits.vid; powernow_acpi_init()
369 fid = pc.bits.fid; powernow_acpi_init()
372 powernow_table[i].driver_data = fid; /* lower 8 bits */ powernow_acpi_init()
373 powernow_table[i].driver_data |= (vid << 8); /* upper 8 bits */ powernow_acpi_init()
406 if (latency < pc.bits.sgtc) powernow_acpi_init()
407 latency = pc.bits.sgtc; powernow_acpi_init()
569 cfid = fidvidstatus.bits.CFID; powernow_get()
617 fsb = (10 * cpu_khz) / fid_codes[fidvidstatus.bits.CFID]; powernow_cpu_init()
629 result = powernow_decode_bios(fidvidstatus.bits.MFID, powernow_cpu_init()
630 fidvidstatus.bits.SVID); powernow_cpu_init()
/linux-4.1.27/arch/mips/include/asm/
H A Dspinlock_types.h14 * bits 0..15 : serving_now
15 * bits 16..31 : ticket
/linux-4.1.27/arch/arm/mach-ep93xx/
H A DMakefile8 obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o
9 AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
/linux-4.1.27/include/asm-generic/bitops/
H A Dfind.h9 * @size: The bitmap size in bits
12 * If no bits are set, returns @size.
23 * @size: The bitmap size in bits
26 * If no bits are zero, returns @size.
37 * @size: The maximum number of bits to search
40 * If no bits are set, returns @size.
48 * @size: The maximum number of bits to search
51 * If no bits are zero, returns @size.
/linux-4.1.27/drivers/media/rc/img-ir/
H A Dimg-ir-sony.c24 func = raw & 0x7f; /* first 7 bits */ img_ir_sony_scancode()
26 dev = raw & 0x1f; /* next 5 bits */ img_ir_sony_scancode()
33 func = raw & 0x7f; /* first 7 bits */ img_ir_sony_scancode()
35 dev = raw & 0xff; /* next 8 bits */ img_ir_sony_scancode()
42 func = raw & 0x7f; /* first 7 bits */ img_ir_sony_scancode()
44 dev = raw & 0x1f; /* next 5 bits */ img_ir_sony_scancode()
46 subdev = raw & 0xff; /* next 8 bits */ img_ir_sony_scancode()
72 /* can't encode subdev and higher device bits */ img_ir_sony_filter()
75 /* subdevice (extended) bits only in 20 bit encoding */ img_ir_sony_filter()
81 /* upper device bits only in 15 bit encoding */ img_ir_sony_filter()
88 * The hardware mask cannot distinguish high device bits and low img_ir_sony_filter()
89 * extended bits, so logically AND those bits of the masks img_ir_sony_filter()
96 /* ensure there aren't any bits straying between fields */ img_ir_sony_filter()
/linux-4.1.27/arch/x86/include/asm/uv/
H A Duv_bau.h61 test_bit((cpu), (bau_local_cpumask).bits)
105 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
112 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
155 /* 4 bits of software ack period */
191 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
195 * distribution vector. Adjacent bits correspond to consecutive even numbered
201 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)]; member in struct:pnmask
207 * enough bits for max. cpu's per uvhub)
210 unsigned long bits; member in struct:bau_local_cpumask
214 * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
215 * only 12 bytes (96 bits) of the payload area are usable.
216 * An additional 3 bytes (bits 27:4) of the header address are carried
220 * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
223 * [ effective message contents (16 bytes (128 bits) maximum), not counting
233 /* 64 bits */
235 /* 16 bits */
237 /* 16 bits */
243 * UV1 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
248 /* bits 5:0 */
250 /* bits 20:6 */ /* in uvhub map */
252 /* bits 28:21 */
255 /* bits 31:29 */
256 /* int will align on 32 bits */
258 /* bits 40:32 */
261 /* bits 56:41 */ /* becomes bytes 16-17 of msg */
264 (these are address bits
269 /* address bits 27:4 are payload */
270 /* these next 24 (58-81) bits become bytes 12-14 of msg */
271 /* bits 65:58 land in byte 12 */
277 /* bits 61:59 */
284 /* bits 65:64 */
286 /* bits 73:66 land in byte 13 */
288 /* bits 71:66 */
290 /* bits 73:72 */
292 /* bits 81:74 land in byte 14 */
294 /* bits 79:74 */
296 /* bits 81:80 */
299 /* bits 88:82 */
306 /* bits 95:90 */
308 /* bits 100:96 */
313 /* bits 104:102 */
322 /* bits 127:107 */
326 * UV2 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
332 /* bits 14:0 */ /* in uvhub map */
334 /* bits 19:15 */
337 /* Address bits 59:21 */
338 /* bits 25:2 of address (44:21) are payload */
339 /* these next 24 bits become bytes 12-14 of msg */
340 /* bits 28:21 land in byte 12 */
346 /* bits 24:22 */
351 /* bits 28:26 */
353 /* bits 36:29 land in byte 13 */
356 /* bits 36:29 */
358 /* bits 44:37 land in byte 14 */
360 /* bits 44:37 */
363 /* bits 51:45 */
370 /* bits 74:53 */
372 /* bits 77:75 */
375 /* bits 93:78 Suppl_A */
385 /* bits 119:96 */
387 /* bits 127:120 */
409 * bytes 0-11 bits 41-56 bits 58-81
419 * bytes 0-11 bits 70-78 bits 21-44
431 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
432 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
442 /* 64 bits, bytes 0-7 */
444 /* 16 bits, bytes 8-9 */
446 /* 16 bits, bytes 10-11 */
447 /* these next 3 bytes come from bits 58-81 of the message header */
458 /* byte 15 (bits 127:120) */
464 /* 32 bits, bytes 20-23 (aligned) */
710 return constant_test_bit(uvhub, &dstp->bits[0]); bau_uvhub_isset()
714 __set_bit(pnode, &dstp->bits[0]); bau_uvhub_set()
719 bitmap_zero(&dstp->bits[0], nbits); bau_uvhubs_clear()
723 return bitmap_weight((unsigned long *)&dstp->bits[0], bau_uvhub_weight()
729 bitmap_zero(&dstp->bits, nbits); bau_cpubits_clear()
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Dc6xdigio.c80 unsigned int *bits, c6xdigio_get_encoder_bits()
90 *bits = val; c6xdigio_get_encoder_bits()
99 unsigned int bits; c6xdigio_pwm_write() local
106 bits = (val >> 0) & 0x03; c6xdigio_pwm_write()
107 c6xdigio_write_data(dev, cmd | bits | (0 << 2), 0x00); c6xdigio_pwm_write()
108 bits = (val >> 2) & 0x03; c6xdigio_pwm_write()
109 c6xdigio_write_data(dev, cmd | bits | (1 << 2), 0x80); c6xdigio_pwm_write()
110 bits = (val >> 4) & 0x03; c6xdigio_pwm_write()
111 c6xdigio_write_data(dev, cmd | bits | (0 << 2), 0x00); c6xdigio_pwm_write()
112 bits = (val >> 6) & 0x03; c6xdigio_pwm_write()
113 c6xdigio_write_data(dev, cmd | bits | (1 << 2), 0x80); c6xdigio_pwm_write()
114 bits = (val >> 8) & 0x03; c6xdigio_pwm_write()
115 c6xdigio_write_data(dev, cmd | bits | (0 << 2), 0x00); c6xdigio_pwm_write()
125 unsigned int bits; c6xdigio_encoder_read() local
129 c6xdigio_get_encoder_bits(dev, &bits, cmd | (1 << 2), 0x80); c6xdigio_encoder_read()
130 val |= (bits << 0); c6xdigio_encoder_read()
132 c6xdigio_get_encoder_bits(dev, &bits, cmd | (0 << 2), 0x00); c6xdigio_encoder_read()
133 val |= (bits << 3); c6xdigio_encoder_read()
135 c6xdigio_get_encoder_bits(dev, &bits, cmd | (1 << 2), 0x80); c6xdigio_encoder_read()
136 val |= (bits << 6); c6xdigio_encoder_read()
138 c6xdigio_get_encoder_bits(dev, &bits, cmd | (0 << 2), 0x00); c6xdigio_encoder_read()
139 val |= (bits << 9); c6xdigio_encoder_read()
141 c6xdigio_get_encoder_bits(dev, &bits, cmd | (1 << 2), 0x80); c6xdigio_encoder_read()
142 val |= (bits << 12); c6xdigio_encoder_read()
144 c6xdigio_get_encoder_bits(dev, &bits, cmd | (0 << 2), 0x00); c6xdigio_encoder_read()
145 val |= (bits << 15); c6xdigio_encoder_read()
147 c6xdigio_get_encoder_bits(dev, &bits, cmd | (1 << 2), 0x80); c6xdigio_encoder_read()
148 val |= (bits << 18); c6xdigio_encoder_read()
150 c6xdigio_get_encoder_bits(dev, &bits, cmd | (0 << 2), 0x00); c6xdigio_encoder_read()
151 val |= (bits << 21); c6xdigio_encoder_read()
79 c6xdigio_get_encoder_bits(struct comedi_device *dev, unsigned int *bits, unsigned int cmd, unsigned int status) c6xdigio_get_encoder_bits() argument
/linux-4.1.27/arch/mips/math-emu/
H A Ddp_sqrt.c96 /* magic initial approximation to almost 8 sig. bits */ ieee754dp_sqrt()
97 yh = y.bits >> 32; ieee754dp_sqrt()
100 y.bits = ((u64) yh << 32) | (y.bits & 0xffffffff); ieee754dp_sqrt()
102 /* Heron's rule once with correction to improve to ~18 sig. bits */ ieee754dp_sqrt()
106 y.bits -= 0x0010000600000000LL; ieee754dp_sqrt()
107 y.bits &= 0xffffffff00000000LL; ieee754dp_sqrt()
109 /* triple to almost 56 sig. bits: y ~= sqrt(x) to within 1 ulp */ ieee754dp_sqrt()
130 if (ieee754_csr.sx & IEEE754_INEXACT || t.bits != y.bits) { ieee754dp_sqrt()
134 t.bits -= 1; ieee754dp_sqrt()
142 y.bits += 1; ieee754dp_sqrt()
145 t.bits += 1; ieee754dp_sqrt()
/linux-4.1.27/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-jtag.c74 * Write up to 32bits into the QLM jtag chain. Bits are shifted
76 * order bits followed by the high order bits. The JTAG chain is
77 * 4 * 268 bits long, or 1072.
80 * @bits: Number of bits to shift in (1-32).
84 * Returns The low order bits of the JTAG chain that shifted out of the
87 uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data) cvmx_helper_qlm_jtag_shift() argument
92 jtgd.s.shft_cnt = bits - 1; cvmx_helper_qlm_jtag_shift()
100 return jtgd.s.shft_reg >> (32 - bits); cvmx_helper_qlm_jtag_shift()
105 * common to need to shift more than 32 bits of zeros into the
107 * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
111 * @bits:
113 void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits) cvmx_helper_qlm_jtag_shift_zeros() argument
115 while (bits > 0) { cvmx_helper_qlm_jtag_shift_zeros()
116 int n = bits; cvmx_helper_qlm_jtag_shift_zeros()
120 bits -= n; cvmx_helper_qlm_jtag_shift_zeros()
126 * have already shifted in 268*4, or 1072 bits into the JTAG
H A Dcvmx-helper-errata.c53 /* We need to load all four lanes of the QLM, a total of 1072 bits */ __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
56 * Each lane has 268 bits. We need to set __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
58 * 1. All other bits are zero. Bits go in LSB first, __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
59 * so start off with the zeros for bits <63:0>. __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
64 /* Zeros for bits <76:68> */ __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
68 /* Zeros for bits <267:78> */ __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
/linux-4.1.27/fs/btrfs/
H A Dstruct-funcs.c39 * which are wappers of btrfs_set_token_#bits functions and
40 * btrfs_get_token_#bits functions, which are defined in this file.
52 #define DEFINE_BTRFS_SETGET_BITS(bits) \
53 u##bits btrfs_get_token_##bits(struct extent_buffer *eb, void *ptr, \
64 int size = sizeof(u##bits); \
65 u##bits res; \
72 res = get_unaligned_le##bits(p + off); \
78 __le##bits leres; \
81 return le##bits##_to_cpu(leres); \
84 res = get_unaligned_le##bits(p + off); \
92 void btrfs_set_token_##bits(struct extent_buffer *eb, \
93 void *ptr, unsigned long off, u##bits val, \
103 int size = sizeof(u##bits); \
110 put_unaligned_le##bits(val, p + off); \
116 __le##bits val2; \
118 val2 = cpu_to_le##bits(val); \
123 put_unaligned_le##bits(val, p + off); \
/linux-4.1.27/sound/aoa/codecs/
H A Donyx.h59 /* bits 1-5 control channel bits 1-5 */
63 /* controls channel bits 8-15 */
66 /* control channel bits 24-29, high 2 bits reserved */
72 /* lower 4 bits control bits 32-35 of channel control and word length */
/linux-4.1.27/arch/x86/include/asm/
H A Dword-at-a-time.h46 static inline unsigned long has_zero(unsigned long a, unsigned long *bits, const struct word_at_a_time *c) has_zero() argument
49 *bits = mask; has_zero()
53 static inline unsigned long prep_zero_mask(unsigned long a, unsigned long bits, const struct word_at_a_time *c) prep_zero_mask() argument
55 return bits; prep_zero_mask()
58 static inline unsigned long create_zero_mask(unsigned long bits) create_zero_mask() argument
60 bits = (bits - 1) & ~bits; create_zero_mask()
61 return bits >> 7; create_zero_mask()
H A Dkasan.h12 /* 47 bits for kernel address -> (47 - 3) bits for shadow */
H A Dimr.h18 * IMR agent access mask bits
38 * Read/Write access-all bits here include some reserved bits
51 /* IMR alignment bits - only bits 31:10 are checked for IMR validity */
/linux-4.1.27/arch/x86/math-emu/
H A Dround_Xsig.S16 | Each function returns the size of the shift (nr of bits). |
40 orl %edx,%edx /* ms bits */
42 jnz L_shift_1 /* Shift left 1 - 31 bits */
49 /* We need to shift left by 1 - 31 bits */
100 orl %edx,%edx /* ms bits */
102 jnz L_n_shift_1 /* Shift left 1 - 31 bits */
109 orl %edx,%edx /* ms bits */
111 jnz L_n_shift_1 /* Shift left 1 - 31 bits */
120 /* We need to shift left by 1 - 31 bits */
H A Dwm_shrx.S27 | right by the number of bits specified by the second arg (arg2). |
41 cmpl $32,%ecx /* shrd only works for 0..31 bits */
44 /* less than 32 bits */
103 | right by the number of bits specified by the second arg (arg2). |
108 | The lower 8 bits of eax are lost and replaced by a flag which is |
120 cmpl $64,%ecx /* shrd only works for 0..31 bits */
123 cmpl $32,%ecx /* shrd only works for 0..31 bits */
128 /* Shift by [32..63] bits */
136 orl %ebx,%ebx /* test these 32 bits */
138 test $0x7fffffff,%eax /* and 31 bits here */
149 /* Shift by [0..31] bits */
166 /* Shift by [64..95] bits */
193 /* Shift by [96..inf) bits */
H A Dreg_u_sub.S78 cmpw $32,%cx /* shrd only works for 0..31 bits */
81 /* less than 32 bits */
97 jz L_more_31_no_low /* none of the lowest bits is set */
116 /* Shift right by 64 bits */
127 /* Shift right by 65 bits */
177 jnz L_shift_1 /* shift left 1 - 31 bits */
180 jnz L_shift_32 /* shift left 32 - 63 bits */
193 /* Shift left 64 bits */
217 /* We need to shift left by 1 - 31 bits */
/linux-4.1.27/arch/sh/include/cpu-sh5/cpu/
H A Dcache.h17 /* Valid and Dirty bits */
21 /* Unimplemented compat bits.. */
62 * |<--- tag (19 bits) --->|
66 * ^ 2 bits 8 bits 5 bits
69 * Cacheline size is based on offset: 5 bits = 32 bytes per line
83 'synonym' occurs where effective address bits overlap between those used for
87 #define CACHE_OC_N_SYNBITS 1 /* Number of synonym bits */
/linux-4.1.27/arch/arm64/include/asm/
H A Dword-at-a-time.h29 static inline unsigned long has_zero(unsigned long a, unsigned long *bits, has_zero() argument
33 *bits = mask; has_zero()
37 #define prep_zero_mask(a, bits, c) (bits)
39 static inline unsigned long create_zero_mask(unsigned long bits) create_zero_mask() argument
41 bits = (bits - 1) & ~bits; create_zero_mask()
42 return bits >> 7; create_zero_mask()
H A Dirq.h18 * incoming GICv2m|GICv3|ITS bits. acpi_irq_init()
H A Dkvm_arm.h25 /* Hyp Configuration Register (HCR) bits */
63 * The bits we set in HCR:
86 /* Hyp System Control Register (SCTLR_EL2) bits */
97 /* TCR_EL2 Registers bits */
111 /* VTCR_EL2 Registers bits */
129 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
144 * 40bits input (T0SZ = 24)
155 * 40bits input (T0SZ = 24)
179 /* Hyp Debug Configuration Register bits */
/linux-4.1.27/drivers/iio/adc/
H A Dmax1363.c132 * @bits: accuracy of the adc in bits
142 u8 bits; member in struct:max1363_chip_info
389 if (st->chip_info->bits != 8) { max1363_read_single_chan()
397 ((1 << st->chip_info->bits) - 1); max1363_read_single_chan()
431 *val2 = st->chip_info->bits; max1363_read_raw()
461 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \
472 .realbits = bits, \
473 .storagebits = (bits > 8) ? 16 : 8, \
482 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \
495 .realbits = bits, \
496 .storagebits = (bits > 8) ? 16 : 8, \
504 #define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \
505 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \
506 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \
507 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \
508 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \
509 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \
510 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \
511 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \
512 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \
549 #define MAX1363_12X_CHANS(bits) { \
550 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
551 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
552 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
553 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
554 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
555 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
556 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
557 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
558 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \
559 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \
560 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \
561 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \
562 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
563 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
564 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
565 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
566 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \
567 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \
568 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
569 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
570 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
571 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
572 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \
573 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \
598 #define MAX1363_8X_CHANS(bits) { \
599 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
600 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
601 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
602 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
603 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
604 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
605 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
606 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
607 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \
608 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \
609 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \
610 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \
611 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \
612 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \
613 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \
614 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \
625 #define MAX1363_2X_CHANS(bits) { \
626 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
627 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
628 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \
629 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \
743 switch (st->chip_info->bits) { max1363_write_thresh()
1049 .bits = 10,
1059 .bits = 10,
1069 .bits = 12,
1079 .bits = 12,
1089 .bits = 8,
1099 .bits = 8,
1109 .bits = 8,
1119 .bits = 8,
1129 .bits = 10,
1139 .bits = 10,
1149 .bits = 10,
1159 .bits = 10,
1169 .bits = 12,
1179 .bits = 12,
1189 .bits = 12,
1199 .bits = 12,
1209 .bits = 8,
1219 .bits = 8,
1229 .bits = 8,
1239 .bits = 8,
1249 .bits = 8,
1259 .bits = 8,
1269 .bits = 10,
1279 .bits = 10,
1289 .bits = 10,
1299 .bits = 10,
1309 .bits = 10,
1319 .bits = 10,
1329 .bits = 12,
1339 .bits = 12,
1349 .bits = 12,
1359 .bits = 12,
1369 .bits = 12,
1379 .bits = 12,
1389 .bits = 12,
1399 .bits = 12,
1409 .bits = 10,
1419 .bits = 10,
1484 if (st->chip_info->bits != 8) max1363_trigger_handler()
1503 if (st->chip_info->bits != 8) max1363_trigger_handler()
1577 && st->chip_info->bits == 8) { max1363_probe()
/linux-4.1.27/arch/um/include/asm/
H A Dpage.h41 #define pte_get_bits(pte, bits) ((pte).pte_low & (bits))
42 #define pte_set_bits(pte, bits) ((pte).pte_low |= (bits))
43 #define pte_clear_bits(pte, bits) ((pte).pte_low &= ~(bits))
72 #define pte_get_bits(p, bits) ((p).pte & (bits))
73 #define pte_set_bits(p, bits) ((p).pte |= (bits))
74 #define pte_clear_bits(p, bits) ((p).pte &= ~(bits))
/linux-4.1.27/drivers/atm/
H A Dzeprom.h25 #define ZEPROM_CMD_LEN 3 /* commands are three bits */
26 #define ZEPROM_ADDR_LEN 6 /* addresses are six bits */
28 /* Commands (3 bits) */
/linux-4.1.27/include/uapi/linux/
H A Dmpls.h15 * Label: Label Value, 20 bits
16 * TC: Traffic Class field, 3 bits
18 * TTL: Time to Live, 8 bits
/linux-4.1.27/lib/
H A Dbitmap.c20 * bitmaps provide an array of bits, implemented using an an
21 * array of unsigned longs. The number of valid bits in a
25 * The possible unused bits in the last, partially used word
31 * carefully filter out these unused bits from impacting their
36 * unused bits set, then they won't output any set unused bits
46 const unsigned long *bitmap2, unsigned int bits) __bitmap_equal()
48 unsigned int k, lim = bits/BITS_PER_LONG; __bitmap_equal()
53 if (bits % BITS_PER_LONG) __bitmap_equal()
54 if ((bitmap1[k] ^ bitmap2[k]) & BITMAP_LAST_WORD_MASK(bits)) __bitmap_equal()
61 void __bitmap_complement(unsigned long *dst, const unsigned long *src, unsigned int bits) __bitmap_complement() argument
63 unsigned int k, lim = bits/BITS_PER_LONG; __bitmap_complement()
67 if (bits % BITS_PER_LONG) __bitmap_complement()
73 * __bitmap_shift_right - logical right shift of the bits in a bitmap
76 * @shift : shift by this many bits
77 * @nbits : bitmap size, in bits
79 * Shifting right (dividing) means moving bits in the MS -> LS bit
81 * LS bits shifted off the bottom are lost.
93 * If shift is not word aligned, take lower rem bits of __bitmap_shift_right()
94 * word above and make them the top rem bits of result. __bitmap_shift_right()
117 * __bitmap_shift_left - logical left shift of the bits in a bitmap
120 * @shift : shift by this many bits
121 * @nbits : bitmap size, in bits
123 * Shifting left (multiplying) means moving bits in the LS -> MS
125 * and those MS bits shifted off the top are lost.
138 * If shift is not word aligned, take upper rem bits of __bitmap_shift_left()
139 * word below and make them the bottom rem bits of result. __bitmap_shift_left()
154 const unsigned long *bitmap2, unsigned int bits) __bitmap_and()
157 unsigned int lim = bits/BITS_PER_LONG; __bitmap_and()
162 if (bits % BITS_PER_LONG) __bitmap_and()
164 BITMAP_LAST_WORD_MASK(bits)); __bitmap_and()
170 const unsigned long *bitmap2, unsigned int bits) __bitmap_or()
173 unsigned int nr = BITS_TO_LONGS(bits); __bitmap_or()
181 const unsigned long *bitmap2, unsigned int bits) __bitmap_xor()
184 unsigned int nr = BITS_TO_LONGS(bits); __bitmap_xor()
192 const unsigned long *bitmap2, unsigned int bits) __bitmap_andnot()
195 unsigned int lim = bits/BITS_PER_LONG; __bitmap_andnot()
200 if (bits % BITS_PER_LONG) __bitmap_andnot()
202 BITMAP_LAST_WORD_MASK(bits)); __bitmap_andnot()
208 const unsigned long *bitmap2, unsigned int bits) __bitmap_intersects()
210 unsigned int k, lim = bits/BITS_PER_LONG; __bitmap_intersects()
215 if (bits % BITS_PER_LONG) __bitmap_intersects()
216 if ((bitmap1[k] & bitmap2[k]) & BITMAP_LAST_WORD_MASK(bits)) __bitmap_intersects()
223 const unsigned long *bitmap2, unsigned int bits) __bitmap_subset()
225 unsigned int k, lim = bits/BITS_PER_LONG; __bitmap_subset()
230 if (bits % BITS_PER_LONG) __bitmap_subset()
231 if ((bitmap1[k] & ~bitmap2[k]) & BITMAP_LAST_WORD_MASK(bits)) __bitmap_subset()
237 int __bitmap_weight(const unsigned long *bitmap, unsigned int bits) __bitmap_weight() argument
239 unsigned int k, lim = bits/BITS_PER_LONG; __bitmap_weight()
245 if (bits % BITS_PER_LONG) __bitmap_weight()
246 w += hweight_long(bitmap[k] & BITMAP_LAST_WORD_MASK(bits)); __bitmap_weight()
297 * @size: The bitmap size in bits
299 * @nr: The number of zeroed bits we're looking for
349 * @nmaskbits: size of bitmap, in bits.
352 * bits of the resultant bitmask. No chunk may specify a value larger
353 * than 32 bits (%-EOVERFLOW), and if a chunk specifies a smaller value
354 * then leading 0-bits are prepended. %-EINVAL is returned for illegal
401 * Make sure there are at least 4 free bits in 'chunk'. __bitmap_parse()
435 * @nmaskbits: size of bitmap, in bits.
460 * @nmaskbits: size of bitmap, in bits
489 * @nmaskbits: number of bits in mask to be written
492 * ranges. Consecutively set bits are shown as two hyphen-separated
590 * @nmaskbits: size of bitmap, in bits.
620 * If for example, just bits 4 through 7 are set in @buf, then @pos
626 * The bit positions 0 through @bits are valid positions in @buf.
646 * If for example, just bits 4 through 7 are set in @buf, then @ord
672 * @nbits: number of bits in each of these bitmaps
685 * The positions of unset bits in @old are mapped to themselves
689 * @dst, clearing any bits previously set in @dst.
691 * For example, lets say that @old has bits 4 through 7 set, and
692 * @new has bits 12 through 15 set. This defines the mapping of bit
695 * with bits 1, 5 and 7 set, then @dst should leave with bits 1,
725 * @bits: number of bits in each of these bitmaps
734 * The positions of unset bits in @old are mapped to themselves
740 * For example, lets say that @old has bits 4 through 7 set, and
741 * @new has bits 12 through 15 set. This defines the mapping of bit
747 const unsigned long *new, int bits) bitmap_bitremap()
749 int w = bitmap_weight(new, bits); bitmap_bitremap()
750 int n = bitmap_pos_to_ord(old, oldbit, bits); bitmap_bitremap()
754 return bitmap_ord_to_pos(new, n % w, bits); bitmap_bitremap()
763 * @bits: number of bits in each of these bitmaps
775 * Any set bits in @orig above bit number W, where W is the
776 * weight of (number of set bits in) @relmap are mapped nowhere.
777 * In particular, if for all bits m set in @orig, m >= W, then
781 * @orig bitmap over itself so that all its set bits x are in the
786 * Let's say @relmap has bits 30-39 set, and @orig has bits
788 * @dst will have bits 31, 33, 35, 37 and 39 set.
801 * Similarly, we turned on bits 33, 35, 37 and 39 in @dst,
802 * because they were the 4th, 6th, 8th and 10th set bits
803 * set in @relmap, and the 4th, 6th, 8th and 10th bits of
804 * @orig (i.e. bits 3, 5, 7 and 9) were also set.
809 * only ten bits turned on in @relmap (30..39), so that bit
813 * Let's say @relmap has these ten bits set:
822 * unsigned long *tmp; // a temporary bitmap's bits
824 * bitmap_fold(tmp, orig, bitmap_weight(relmap, bits), bits);
825 * bitmap_onto(dst, tmp, relmap, bits);
849 * If either of @orig or @relmap is empty (no set bits), then @dst
852 * If (as explained above) the only set bits in @orig are in positions
856 * All bits in @dst not set by the above rule are cleared.
859 const unsigned long *relmap, unsigned int bits) bitmap_onto()
865 bitmap_zero(dst, bits); bitmap_onto()
870 * for (m = 0; m < bitmap_weight(relmap, bits); m++) { bitmap_onto()
871 * n = bitmap_ord_to_pos(orig, m, bits); bitmap_onto()
878 for_each_set_bit(n, relmap, bits) { for_each_set_bit()
879 /* m == bitmap_pos_to_ord(relmap, n, bits) */ for_each_set_bit()
892 * @nbits: number of bits in each of these bitmaps
895 * Clear all other bits in @dst. See further the comment and
916 * order: region size (log base 2 of number of bits)
919 * Can set, verify and/or release a region of bits in a bitmap,
920 * depending on which combination of REG_OP_* flag bits is set.
922 * A region of a bitmap is a sequence of bits in the bitmap, of
926 * Returns 1 if REG_OP_ISFREE succeeds (region is all zero bits).
931 REG_OP_ISFREE, /* true if region is all zero bits */
932 REG_OP_ALLOC, /* set all bits in region */
933 REG_OP_RELEASE, /* clear all bits in region */
938 int nbits_reg; /* number of bits in region */ __reg_op()
942 int nbitsinlong; /* num bits of region in each spanned long */ __reg_op()
971 ret = 1; /* all bits in region free (zero) */ __reg_op()
991 * @bits: number of bits in the bitmap
992 * @order: region size (log base 2 of number of bits) to find
994 * Find a region of free (zero) bits in a @bitmap of @bits bits and
1002 int bitmap_find_free_region(unsigned long *bitmap, unsigned int bits, int order) bitmap_find_free_region() argument
1006 for (pos = 0 ; (end = pos + (1U << order)) <= bits; pos = end) { bitmap_find_free_region()
1020 * @order: region size (log base 2 of number of bits) to release
1037 * @order: region size (log base 2 of number of bits) to allocate
1039 * Allocate (set bits in) a specified region of a bitmap.
1042 * free (not all bits were zero).
1053 * bitmap_copy_le - copy a bitmap, putting the bits into little-endian order.
1056 * @nbits: number of bits in the bitmap
45 __bitmap_equal(const unsigned long *bitmap1, const unsigned long *bitmap2, unsigned int bits) __bitmap_equal() argument
153 __bitmap_and(unsigned long *dst, const unsigned long *bitmap1, const unsigned long *bitmap2, unsigned int bits) __bitmap_and() argument
169 __bitmap_or(unsigned long *dst, const unsigned long *bitmap1, const unsigned long *bitmap2, unsigned int bits) __bitmap_or() argument
180 __bitmap_xor(unsigned long *dst, const unsigned long *bitmap1, const unsigned long *bitmap2, unsigned int bits) __bitmap_xor() argument
191 __bitmap_andnot(unsigned long *dst, const unsigned long *bitmap1, const unsigned long *bitmap2, unsigned int bits) __bitmap_andnot() argument
207 __bitmap_intersects(const unsigned long *bitmap1, const unsigned long *bitmap2, unsigned int bits) __bitmap_intersects() argument
222 __bitmap_subset(const unsigned long *bitmap1, const unsigned long *bitmap2, unsigned int bits) __bitmap_subset() argument
746 bitmap_bitremap(int oldbit, const unsigned long *old, const unsigned long *new, int bits) bitmap_bitremap() argument
858 bitmap_onto(unsigned long *dst, const unsigned long *orig, const unsigned long *relmap, unsigned int bits) bitmap_onto() argument
/linux-4.1.27/arch/x86/lib/
H A Dcmpxchg8b_emu.S17 * %eax : low 32 bits of old value
18 * %edx : high 32 bits of old value
19 * %ebx : low 32 bits of new value
20 * %ecx : high 32 bits of new value
H A Dcmpxchg16b_emu.S17 * %rax : low 64 bits of old value
18 * %rdx : high 64 bits of old value
19 * %rbx : low 64 bits of new value
20 * %rcx : high 64 bits of new value
/linux-4.1.27/include/net/netns/
H A Dhash.h12 * shift this right to eliminate bits, that are net_hash_mix()
/linux-4.1.27/tools/include/asm-generic/bitops/
H A Dfind.h9 * @size: The bitmap size in bits
12 * If no bits are set, returns @size.
23 * @size: The maximum number of bits to search
26 * If no bits are set, returns @size.
/linux-4.1.27/drivers/media/platform/s5p-tv/
H A Dregs-mixer.h54 /* generates mask for range of bits */
61 /* bits for MXR_STATUS */
67 /* bits for MXR_CFG */
87 /* bits for MXR_GRAPHICn_CFG */
94 /* bits for MXR_GRAPHICn_WH */
100 /* bits for MXR_GRAPHICn_SXY */
104 /* bits for MXR_GRAPHICn_DXY */
108 /* bits for MXR_INT_EN */
/linux-4.1.27/include/net/
H A Dfirewire.h13 __be16 fifo_hi; /* hi 16bits of FIFO addr */
14 __be32 fifo_lo; /* lo 32bits of FIFO addr */
/linux-4.1.27/arch/mips/include/asm/sgi/
H A Dgio.h37 * read with an "ID" value. IDs are either 8 or 32 bits long. IDs less
38 * than 128 are 8 bits long, with the most significant 24 bits read from
42 * bits 0:6 the product ID; ranges from 0x00 to 0x7F.
43 * bit 7 0=GIO Product ID is 8 bits wide
44 * 1=GIO Product ID is 32 bits wide.
45 * bits 8:15 manufacturer version for the product.
50 * bits 18:31 up to manufacturer.
H A Dpi1.h22 #define PI1_STAT_DEVID 0x03 /* bits 0-1 */
33 #define PI1_DMACTRL_STDMODE 0x00 /* bits 2-3 */
34 #define PI1_DMACTRL_SGIMODE 0x04 /* bits 2-3 */
35 #define PI1_DMACTRL_RICOHMODE 0x08 /* bits 2-3 */
36 #define PI1_DMACTRL_HPMODE 0x0c /* bits 2-3 */
/linux-4.1.27/arch/parisc/include/uapi/asm/
H A Dstat.h7 unsigned int st_dev; /* dev_t is 32 bits on parisc */
8 unsigned int st_ino; /* 32 bits */
9 unsigned short st_mode; /* 16 bits */
10 unsigned short st_nlink; /* 16 bits */
40 unsigned int st_dev; /* dev_t is 32 bits on parisc */
41 unsigned int st_ino; /* 32 bits */
42 unsigned short st_mode; /* 16 bits */
43 unsigned short st_nlink; /* 16 bits */
H A Dioctl.h25 /* ioctl command encoding: 32 bits total, command in lower 16 bits,
26 * size of the parameter structure in the lower 14 bits of the
27 * upper 16 bits.
31 * The highest 2 bits are reserved for indicating the ``access mode''.
36 * Direction bits.
/linux-4.1.27/arch/metag/include/asm/
H A Dmetag_isa.h35 * CACHEWD/CACHEWL instructions use the bottom 8 bits of the data presented to
38 /* Use of these two bits should be discouraged since the bits dont have
53 * CACHERD/CACHERL instructions use bits 3:5 of the address presented to
67 * Lower 32-bits corresponds to MMCU_ENTRY_* above.
68 * Upper 32-bits corresponds to CRLINPHY1_* values below (if requested).
70 * Lower 32-bits corresponds to CRLINPHY0_* values below.
71 * Upper 32-bits undefined.
/linux-4.1.27/arch/arm/crypto/
H A Daes_glue.h17 const int bits, struct AES_KEY *key);
19 const int bits, struct AES_KEY *key);
/linux-4.1.27/drivers/gpu/drm/gma500/
H A Doaktrail.h87 u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */
88 /* Bit 0, Frequency, 15 bits,0 - 32767Hz */
91 /*16 bits, Defined as follows: */
93 /* Bit 0, Type, 2 bits, */
98 /* Bit 2, Pixel Format, 4 bits */
103 /* Bit 6, Reserved, 2 bits, 00b */
104 /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
105 /* Bit 14, Reserved, 2 bits, 00b */
116 u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/
117 /*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/
121 /*16 bits, Defined as follows: */
123 /* Bit 0, Type, 2 bits, */
128 /* Bit 2, Pixel Format, 4 bits */
133 /* Bit 6, Reserved, 2 bits, 00b */
134 /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
135 /* Bit 14, Reserved, 2 bits, 00b */
140 u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/
151 u16 Rsvd:5;/*5 bits,00000b */
157 union { /*8 bits,Defined as follows: */
159 u8 PanelType:4; /*4 bits, Bit field for panels*/
161 /*2 bits,Specifies which of the*/
174 union { /*8 bits,Defined as follows: */
176 u8 PanelType:4; /*4 bits, Bit field for panels*/
178 /*2 bits,Specifies which of the*/
/linux-4.1.27/drivers/clocksource/
H A Dmmio.c49 * @bits: Number of valid bits
53 unsigned long hz, int rating, unsigned bits, clocksource_mmio_init()
58 if (bits > 32 || bits < 16) clocksource_mmio_init()
69 cs->clksrc.mask = CLOCKSOURCE_MASK(bits); clocksource_mmio_init()
52 clocksource_mmio_init(void __iomem *base, const char *name, unsigned long hz, int rating, unsigned bits, cycle_t (*read)(struct clocksource *)) clocksource_mmio_init() argument
/linux-4.1.27/arch/mips/include/asm/dec/
H A Dkn02ba.h19 * CPU interrupt bits.
28 * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
49 * Memory Error Register bits.
54 * Memory Size Register bits.
59 * I/O ASIC System Support Register bits.
H A Decc.h19 * Error Address Register bits.
30 * Error Syndrome Register bits.
31 * The register is frozen when EAR.VALID is set, otherwise it records bits
35 #define KN0X_ESR_CHKHI (0x7f<<24) /* check bits read from mem */
39 #define KN0X_ESR_CHKLO (0x7f<<8) /* check bits read from mem */
H A Dkn02ca.h19 * CPU interrupt bits.
28 * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
50 * Memory Error Register bits.
55 * Memory Size Register bits.
64 * I/O ASIC System Support Register bits.
H A Dkn03.h24 * CPU interrupt bits.
33 * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
54 * Memory Control Register bits.
63 #define KN03_MCR_CHECK (0x7f<<0) /* diagnostic check bits */
66 * I/O ASIC System Support Register bits.
H A Dkn02.h33 * System Control & Status Register bits.
40 #define KN02_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */
49 #define KN02_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */
54 * CPU interrupt bits.
63 * CSR interrupt bits.
/linux-4.1.27/arch/mips/lantiq/falcon/
H A Dsysctrl.c88 & clk->bits) != test)); sysctl_wait()
91 clk->module, clk->bits, test, sysctl_wait()
92 sysctl_r32(clk->module, reg) & clk->bits); sysctl_wait()
97 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); sysctl_activate()
98 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); sysctl_activate()
99 sysctl_wait(clk, clk->bits, SYSCTL_ACTS); sysctl_activate()
105 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR); sysctl_deactivate()
106 sysctl_w32(clk->module, clk->bits, SYSCTL_DEACT); sysctl_deactivate()
112 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); sysctl_clken()
113 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); sysctl_clken()
114 sysctl_wait(clk, clk->bits, SYSCTL_CLKS); sysctl_clken()
120 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR); sysctl_clkdis()
127 unsigned int bits; sysctl_reboot() local
130 bits = ~act & clk->bits; sysctl_reboot()
131 if (bits != 0) { sysctl_reboot()
132 sysctl_w32(clk->module, bits, SYSCTL_CLKEN); sysctl_reboot()
133 sysctl_w32(clk->module, bits, SYSCTL_ACT); sysctl_reboot()
134 sysctl_wait(clk, bits, SYSCTL_ACTS); sysctl_reboot()
136 sysctl_w32(clk->module, act & clk->bits, SYSCTL_RBT); sysctl_reboot()
137 sysctl_wait(clk, clk->bits, SYSCTL_ACTS); sysctl_reboot()
168 unsigned int bits) clkdev_add_sys()
176 clk->bits = bits; clkdev_add_sys()
167 clkdev_add_sys(const char *dev, unsigned int module, unsigned int bits) clkdev_add_sys() argument
/linux-4.1.27/arch/cris/include/uapi/arch-v32/arch/
H A Duser.h23 unsigned long bz; /* P0, Constant zero (8-bits). */
24 unsigned long vr; /* P1, Version register (8-bits). */
25 unsigned long pid; /* P2, Process ID (8-bits). */
26 unsigned long srs; /* P3, Support register select (8-bits). */
27 unsigned long wz; /* P4, Constant zero (16-bits). */
31 unsigned long dz; /* P8, Constant zero (32-bits). */
/linux-4.1.27/arch/frv/kernel/
H A Dgdb-io.h48 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
49 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
50 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
51 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
52 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
/linux-4.1.27/arch/m68k/include/asm/
H A Dnettel.h47 * PPIO bits used for DTR/DCD.
56 static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) mcf_setppdata() argument
60 ppdata = (ppdata & ~mask) | bits; mcf_setppdata()
86 * PPIO bits used for DTR/DCD.
93 static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) mcf_setppdata() argument
95 write((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT); mcf_setppdata()
/linux-4.1.27/arch/mips/include/asm/txx9/
H A Dtx4927pcic.h77 /* bits for PCICMD */
80 /* bits for PCISTAT */
83 /* bits for IOBA/MBA */
86 /* bits for G2PSTATUS/G2PMASK */
91 /* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
94 /* bits for PBACFG */
100 /* bits for PBASTATUS/PBAMASK */
104 /* bits for G2PMnGBASE */
108 /* bits for G2PIOGBASE */
112 /* bits for PCICSTATUS/PCICMASK */
124 /* bits for PCICCFG */
137 /* bits for P2GMnGBASE */
142 /* bits for P2GIOGBASE */
150 /* bits for PDMCFG */
175 /* bits for PDMSTS */
/linux-4.1.27/arch/powerpc/include/asm/
H A Dword-at-a-time.h54 static inline unsigned long has_zero(unsigned long a, unsigned long *bits, const struct word_at_a_time *c) has_zero() argument
60 *bits = ret; has_zero()
65 static inline unsigned long prep_zero_mask(unsigned long a, unsigned long bits, const struct word_at_a_time *c) prep_zero_mask() argument
67 return bits; prep_zero_mask()
71 static inline unsigned long create_zero_mask(unsigned long bits) create_zero_mask() argument
80 : "b" (bits)); create_zero_mask()
121 static inline unsigned long create_zero_mask(unsigned long bits) create_zero_mask() argument
123 bits = (bits - 1) & ~bits; create_zero_mask()
124 return bits >> 7; create_zero_mask()
133 static inline unsigned long has_zero(unsigned long a, unsigned long *bits, const struct word_at_a_time *c) has_zero() argument
136 *bits = mask; has_zero()
140 static inline unsigned long prep_zero_mask(unsigned long a, unsigned long bits, const struct word_at_a_time *c) prep_zero_mask() argument
142 return bits; prep_zero_mask()
H A Dpte-40x.h20 * Where possible we make the Linux PTE bits match up with this
22 * - bits 20 and 21 must be cleared, because we use 4k pages (40x can
29 * - PRESENT *must* be in the bottom two bits because swap cache
30 * entries use the top 30 bits. Because 40x doesn't support SMP
33 * - All other bits of the PTE are loaded into TLBLO without
34 * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
35 * software PTE bits. We actually use use bits 21, 24, 25, and
36 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
44 #define _PAGE_USER 0x010 /* matches one of the zone permission bits */
H A Dpte-hash64.h6 * Common bits between 4K and 64K pages in a linux-style PTE.
7 * These match the bits in the (hardware-defined) PowerPC PTE as closely
8 * as possible. Additional bits may be defined in pgtable-hash64-*.h
14 * We could create separate kernel read-only if we used the 3 PP bits
18 #define _PAGE_USER 0x0002 /* matches one of the PP bits */
H A Dkvm_book3s_64.h58 /* These bits are reserved in the guest view of the HPTE */
61 static inline long try_lock_hpte(__be64 *hpte, unsigned long bits) try_lock_hpte() argument
72 be_bits = cpu_to_be64(bits); try_lock_hpte()
114 * encoding bits per actual page size __hpte_actual_psize()
153 * Ignore the top 14 bits of va compute_tlbie_rb()
154 * v have top two bits covering segment size, hence move compute_tlbie_rb()
155 * by 16 bits, Also clear the lower HPTE_V_AVPN_SHIFT (7) bits. compute_tlbie_rb()
156 * AVA field in v also have the lower 23 bits ignored. compute_tlbie_rb()
157 * For base page size 4K we need 14 .. 65 bits (so need to compute_tlbie_rb()
158 * collect extra 11 bits) compute_tlbie_rb()
161 /* This covers 14..54 bits of va*/ compute_tlbie_rb()
166 * AVA in v had cleared lower 23 bits. We need to derive compute_tlbie_rb()
173 * get the vpn bits from va_low using reverse of hashing. compute_tlbie_rb()
174 * In v we have va with 23 bits dropped and then left shifted compute_tlbie_rb()
175 * HPTE_V_AVPN_SHIFT (7) bits. Now to find vsid we need compute_tlbie_rb()
189 rb |= (va_low & 0x7ff) << 12; /* remaining 11 bits of AVA */ compute_tlbie_rb()
195 * remaining bits of AVA/LP fields compute_tlbie_rb()
196 * Also contain the rr bits of LP compute_tlbie_rb()
200 * Now clear not needed LP bits based on actual psize compute_tlbie_rb()
204 * AVAL field 58..77 - base_page_shift bits of va compute_tlbie_rb()
205 * we have space for 58..64 bits, Missing bits should compute_tlbie_rb()
297 * If it's present and writable, atomically set dirty and referenced bits and
334 /* Return HPTE cache control bits corresponding to Linux pte bits */ hpte_cache_bits()
H A Dpte-hash64-64k.h3 /* Additional PTE bits (don't change without checking asm in hash_low.S) */
5 #define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
11 * we set that to be the whole sub-bits mask. The C code will only
14 * all the sub bits. For real 64k pages, we now have the assembly set
15 * _PAGE_HPTE_SUB0 in addition to setting the HIDX bits which overlap
16 * that mask. This is fine as long as the HIDX bits are never set on
24 /* Note the full page bits must be in the same location as for normal
28 #define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
29 #define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
36 * That gives us a max RPN of 34 bits, which means a max of 50 bits
37 * of addressable physical space, or 46 bits for the special 4k PFNs.
H A Dpte-8xx.h7 * We also use the two level tables, but we can put the real bits in them
14 * two bits in the software pte that are supposed to be set to zero in
16 * descriptor contains the guarded and writethrough/copyback bits, we can
37 /* These 4 software bits must be masked out when the entry is loaded
44 /* Setting any bits in the nibble with the follow two controls will
45 * require a TLB exception handler change. It is assumed unused bits
48 #define _PAGE_RO 0x0400 /* lsb PP bits */
49 #define _PAGE_USER 0x0800 /* msb PP bits */
H A Dpte-44x.h12 * upper word of the PTE and the attribute bits below are packed
17 * This isn't entirely true anymore, at least some bits are now
20 * Note that these bits preclude future use of a page size
41 * There are some constrains and options, to decide mapping software bits
44 * - PRESENT *must* be in the bottom three bits because swap cache
45 * entries use the top 29 bits for TLB2.
55 * above bits. Note that the bit values are CPU specific, not architecture
60 * the PTE bits are used as a swp_entry. In the PPC implementation, the
62 * hold protection values. That means the three protection bits are
66 * There are three protection bits available for SWAP entry:
70 * So those three bits have to be inside of 0-2nd LSB of PTE.
H A Ddisassemble.h96 /* bits 6:15 --> 22:31 */ make_dsisr()
100 /* bits 29:30 --> 15:16 */ make_dsisr()
104 /* bits 21:24 --> 18:21 */ make_dsisr()
109 /* bits 1: 4 --> 18:21 */ make_dsisr()
111 /* bits 30:31 --> 12:13 */ make_dsisr()
/linux-4.1.27/tools/testing/selftests/powerpc/primitives/
H A Dword-at-a-time.h54 static inline unsigned long has_zero(unsigned long a, unsigned long *bits, const struct word_at_a_time *c) has_zero() argument
60 *bits = ret; has_zero()
65 static inline unsigned long prep_zero_mask(unsigned long a, unsigned long bits, const struct word_at_a_time *c) prep_zero_mask() argument
67 return bits; prep_zero_mask()
71 static inline unsigned long create_zero_mask(unsigned long bits) create_zero_mask() argument
80 : "b" (bits)); create_zero_mask()
121 static inline unsigned long create_zero_mask(unsigned long bits) create_zero_mask() argument
123 bits = (bits - 1) & ~bits; create_zero_mask()
124 return bits >> 7; create_zero_mask()
133 static inline unsigned long has_zero(unsigned long a, unsigned long *bits, const struct word_at_a_time *c) has_zero() argument
136 *bits = mask; has_zero()
140 static inline unsigned long prep_zero_mask(unsigned long a, unsigned long bits, const struct word_at_a_time *c) prep_zero_mask() argument
142 return bits; prep_zero_mask()
/linux-4.1.27/fs/ocfs2/cluster/
H A Dmasklog.h32 * maintained with help from /proc. If any of the bits match the message is
40 * one of the longs. This leads to having infrequently given bits that are
41 * frequently matched in the high bits.
53 * indication of which bits are allowed (allow) or denied (off/deny).
67 * Echoing allow/deny/off string into the logmask files can flip the bits
75 * The debugfs.ocfs2 tool can also flip the bits with the -l option:
83 /* bits that are frequently given and infrequently matched in the low word */
103 /* bits that are infrequently given and frequently matched in the high word */
134 #define __mlog_test_u64(mask, bits) \
135 ( (u32)(mask & 0xffffffff) & bits.words[0] || \
136 ((u64)(mask) >> 32) & bits.words[1] )
137 #define __mlog_set_u64(mask, bits) do { \
138 bits.words[0] |= (u32)(mask & 0xffffffff); \
139 bits.words[1] |= (u64)(mask) >> 32; \
141 #define __mlog_clear_u64(mask, bits) do { \
142 bits.words[0] &= ~((u32)(mask & 0xffffffff)); \
143 bits.words[1] &= ~((u64)(mask) >> 32); \
154 #define __mlog_test_u64(mask, bits) ((mask) & bits.words[0])
155 #define __mlog_set_u64(mask, bits) do { \
156 bits.words[0] |= (mask); \
158 #define __mlog_clear_u64(mask, bits) do { \
159 bits.words[0] &= ~(mask); \
/linux-4.1.27/drivers/spi/
H A Dspi-bitbang-txrx.h48 u32 word, u8 bits) bitbang_txrx_be_cpha0()
52 u32 oldbit = (!(word & (1<<(bits-1)))) << 31; bitbang_txrx_be_cpha0()
54 for (word <<= (32 - bits); likely(bits); bits--) { bitbang_txrx_be_cpha0()
80 u32 word, u8 bits) bitbang_txrx_be_cpha1()
84 u32 oldbit = (!(word & (1<<(bits-1)))) << 31; bitbang_txrx_be_cpha1()
86 for (word <<= (32 - bits); likely(bits); bits--) { bitbang_txrx_be_cpha1()
46 bitbang_txrx_be_cpha0(struct spi_device *spi, unsigned nsecs, unsigned cpol, unsigned flags, u32 word, u8 bits) bitbang_txrx_be_cpha0() argument
78 bitbang_txrx_be_cpha1(struct spi_device *spi, unsigned nsecs, unsigned cpol, unsigned flags, u32 word, u8 bits) bitbang_txrx_be_cpha1() argument
H A Dspi-sh-sci.c43 static inline void setbits(struct sh_sci_spi *sp, int bits, int on) setbits() argument
48 * Writing the same bits sets the output value. setbits()
54 sp->val |= bits; setbits()
56 sp->val &= ~bits; setbits()
83 unsigned nsecs, u32 word, u8 bits) sh_sci_spi_txrx_mode0()
85 return bitbang_txrx_be_cpha0(spi, nsecs, 0, 0, word, bits); sh_sci_spi_txrx_mode0()
89 unsigned nsecs, u32 word, u8 bits) sh_sci_spi_txrx_mode1()
91 return bitbang_txrx_be_cpha1(spi, nsecs, 0, 0, word, bits); sh_sci_spi_txrx_mode1()
95 unsigned nsecs, u32 word, u8 bits) sh_sci_spi_txrx_mode2()
97 return bitbang_txrx_be_cpha0(spi, nsecs, 1, 0, word, bits); sh_sci_spi_txrx_mode2()
101 unsigned nsecs, u32 word, u8 bits) sh_sci_spi_txrx_mode3()
103 return bitbang_txrx_be_cpha1(spi, nsecs, 1, 0, word, bits); sh_sci_spi_txrx_mode3()
82 sh_sci_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits) sh_sci_spi_txrx_mode0() argument
88 sh_sci_spi_txrx_mode1(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits) sh_sci_spi_txrx_mode1() argument
94 sh_sci_spi_txrx_mode2(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits) sh_sci_spi_txrx_mode2() argument
100 sh_sci_spi_txrx_mode3(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits) sh_sci_spi_txrx_mode3() argument
/linux-4.1.27/scripts/dtc/
H A Ddtc-parser.y36 static unsigned long long eval_literal(const char *s, int base, int bits);
50 int bits;
278 $$.bits = eval_literal($2, 0, 7);
280 if (($$.bits != 8) &&
281 ($$.bits != 16) &&
282 ($$.bits != 32) &&
283 ($$.bits != 64))
287 $$.bits = 32;
293 $$.bits = 32;
297 if ($1.bits < 64) {
298 uint64_t mask = (1ULL << $1.bits) - 1;
303 * condition is true if when we set all bits
305 * mask), all bits are one.
310 "%016lx (%d bits)", $1.bits);
313 $$.data = data_append_integer($1.data, $2, $1.bits);
317 uint64_t val = ~0ULL >> (64 - $1.bits);
319 if ($1.bits == 32)
327 $$.data = data_append_integer($1.data, val, $1.bits);
488 static unsigned long long eval_literal(const char *s, int base, int bits)
501 || ((bits < 64) && (val >= (1ULL << bits))))
/linux-4.1.27/drivers/media/rc/
H A Dir-rc5-decoder.c95 data->bits <<= 1; ir_rc5_decode()
97 data->bits |= 1; ir_rc5_decode()
134 xdata = (data->bits & 0x0003F) >> 0; ir_rc5_decode()
135 command = (data->bits & 0x00FC0) >> 6; ir_rc5_decode()
136 system = (data->bits & 0x1F000) >> 12; ir_rc5_decode()
137 toggle = (data->bits & 0x20000) ? 1 : 0; ir_rc5_decode()
138 command += (data->bits & 0x01000) ? 0 : 0x40; ir_rc5_decode()
149 command = (data->bits & 0x0003F) >> 0; ir_rc5_decode()
150 system = (data->bits & 0x007C0) >> 6; ir_rc5_decode()
151 toggle = (data->bits & 0x00800) ? 1 : 0; ir_rc5_decode()
152 command += (data->bits & 0x01000) ? 0 : 0x40; ir_rc5_decode()
163 command = (data->bits & 0x0003F) >> 0; ir_rc5_decode()
164 system = (data->bits & 0x02FC0) >> 6; ir_rc5_decode()
165 toggle = (data->bits & 0x01000) ? 1 : 0; ir_rc5_decode()
H A Dir-sanyo-decoder.c15 * 13 bits Custom Code
16 * 13 bits NOT(Custom Code)
17 * 8 bits Key data
18 * 8 bits NOT(Key data)
125 data->bits <<= 1; ir_sanyo_decode()
127 data->bits |= 1; ir_sanyo_decode()
156 address = bitrev16((data->bits >> 29) & 0x1fff) >> 3; ir_sanyo_decode()
157 /* not_address = bitrev16((data->bits >> 16) & 0x1fff) >> 3; */ ir_sanyo_decode()
158 command = bitrev8((data->bits >> 8) & 0xff); ir_sanyo_decode()
159 not_command = bitrev8((data->bits >> 0) & 0xff); ir_sanyo_decode()
163 data->bits); ir_sanyo_decode()
H A Dir-sony-decoder.c92 data->bits <<= 1; ir_sony_decode()
94 data->bits |= 1; ir_sony_decode()
132 device = bitrev8((data->bits << 3) & 0xF8); ir_sony_decode()
134 function = bitrev8((data->bits >> 4) & 0xFE); ir_sony_decode()
142 device = bitrev8((data->bits >> 0) & 0xFF); ir_sony_decode()
144 function = bitrev8((data->bits >> 7) & 0xFE); ir_sony_decode()
152 device = bitrev8((data->bits >> 5) & 0xF8); ir_sony_decode()
153 subdevice = bitrev8((data->bits >> 0) & 0xFF); ir_sony_decode()
154 function = bitrev8((data->bits >> 12) & 0xFE); ir_sony_decode()
/linux-4.1.27/drivers/net/ppp/
H A Dppp_mppe.h4 /* option bits for ccp_options.mppe */
17 * And unfortunately, we cannot share the same bits for the option
45 /* S,L bits */ \
51 /* M,D,C bits not supported */ \
65 /* S,L bits */ \
71 /* M,D,C bits */ \
79 /* Other bits */ \
/linux-4.1.27/drivers/misc/altera-stapl/
H A Daltera-comp.c53 static u32 altera_read_packed(u8 *buffer, u32 bits, u32 *bits_avail, altera_read_packed() argument
60 while (bits > 0) { altera_read_packed()
65 if (bits <= *bits_avail) { altera_read_packed()
66 result &= (0xffff >> (SHORT_BITS - (bits + shift))); altera_read_packed()
67 *bits_avail -= bits; altera_read_packed()
68 bits = 0; altera_read_packed()
72 bits -= *bits_avail; altera_read_packed()
/linux-4.1.27/drivers/net/ethernet/brocade/bna/
H A Dbna_hw_defs.h40 #define BFI_VLAN_WORD_SHIFT 5 /* 32 bits */
42 #define BFI_VLAN_BLOCK_SHIFT 9 /* 512 bits */
96 (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 | \
98 (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 | \
100 (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK); \
101 (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK); \
102 (_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT; \
103 (_bna)->bits.halt_mask_bits = __HFN_INT_LL_HALT; \
116 (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 | \
118 (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 | \
120 (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK_CT2); \
121 (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK_CT2); \
122 (_bna)->bits.halt_status_bits = __HFN_INT_CPQ_HALT_CT2; \
123 (_bna)->bits.halt_mask_bits = __HFN_INT_CPQ_HALT_CT2; \
142 /* Interrupt related bits, flags and macros */
147 ((_intr_status) & (_bna)->bits.mbox_status_bits)
150 ((_intr_status) & (_bna)->bits.halt_status_bits)
153 ((_intr_status) & (_bna)->bits.error_status_bits)
183 writel((mask | (bna)->bits.mbox_mask_bits | \
184 (bna)->bits.error_mask_bits), (bna)->regs.fn_int_mask); \
192 writel((mask & ~((bna)->bits.mbox_mask_bits | \
193 (bna)->bits.error_mask_bits)), (bna)->regs.fn_int_mask);\
201 writel(((_status) & ~(_bna)->bits.mbox_status_bits), \
208 * before acking to h/w. The no. of bits is 16 in the doorbell register,
209 * however we keep this limited to 15 bits.
210 * This is because around the edge of 64K boundary (16 bits), one
213 * 15 bits (32K) should be large enough to accumulate, anyways, and the max.
277 /* TxQ, RxQ, CQ related bits, offsets, macros */
/linux-4.1.27/arch/powerpc/platforms/cell/
H A Dinterrupt.h5 * Mapping of IIC pending bits into per-node interrupt numbers.
10 * higher level bits
12 * The bottom 8 bits are split into 2 type bits and 6 data bits that
24 * (that is the node field is expected to never extend to move than 23 bits)
73 /* Which bits in IIC_ISR are edge sensitive */
/linux-4.1.27/arch/alpha/lib/
H A Dstrchr.S28 cmpbge zero, t0, t2 # .. e1 : bits set iff byte == zero
32 cmpbge zero, t4, t4 # .. e1 : bits set iff byte is garbage
35 cmpbge zero, t1, t3 # e0 : bits set iff byte == c
36 or t2, t3, t0 # e1 : bits set iff char match or zero match
37 andnot t0, t4, t0 # e0 : clear garbage bits
44 cmpbge zero, t0, t2 # e0 : bits set iff byte == 0
45 cmpbge zero, t1, t3 # .. e1 : bits set iff byte == c
H A Dev67-strchr.S48 cmpbge zero, t0, t2 # E : bits set iff byte == zero
49 cmpbge zero, t4, t4 # E : bits set iff byte is garbage
54 cmpbge zero, t1, t3 # E : bits set iff byte == c
55 or t2, t3, t0 # E : bits set iff char match or zero match
57 andnot t0, t4, t0 # E : clear garbage bits
71 cmpbge zero, t0, t2 # E : bits set iff byte == 0
73 cmpbge zero, t1, t3 # E : bits set iff byte == c
/linux-4.1.27/include/linux/ceph/
H A Dceph_frag.h10 * 8 upper bits = "bits"
11 * 24 lower bits = "value"
12 * (We could go to 5+27 bits, but who cares.)
14 * We use the _most_ significant bits of the 24 bit value. This makes
17 * Unfortunately, because the "bits" field is still in the high bits, we
/linux-4.1.27/lib/xz/
H A Dxz_lzma2.h24 * number of bits of the current uncompressed offset. In some places there
114 /* Match length is encoded with 4, 5, or 10 bits.
117 * 2-9 4 = Choice=0 + 3 bits
118 * 10-17 5 = Choice=1 + Choice2=0 + 3 bits
119 * 18-273 10 = Choice=1 + Choice2=1 + 8 bits
154 * The highest two bits of a 32-bit match distance are encoded using six bits.
156 * value takes 6-36 bits, larger values taking more bits.
162 * the highest two bits (distance slot) are always encoded using six bits,
163 * the distances 0-3 don't need any additional bits to encode, since the
172 * - distance slot: the highest two bits
173 * - direct bits: 2-26 bits below the highest two bits
174 * - alignment bits: four lowest bits
176 * Direct bits don't use any probabilities.
187 * For match distances greater than 127, only the highest two bits and the
188 * lowest four bits (alignment) is encoded using probabilities.
/linux-4.1.27/net/irda/
H A Dqos.c71 * (2 bytes), and CRC (32 bits at 4 Mb/s). So, for the I field (LAP
285 qos->baud_rate.bits &= new->baud_rate.bits; irda_qos_compute_intersection()
286 qos->window_size.bits &= new->window_size.bits; irda_qos_compute_intersection()
287 qos->min_turn_time.bits &= new->min_turn_time.bits; irda_qos_compute_intersection()
288 qos->max_turn_time.bits &= new->max_turn_time.bits; irda_qos_compute_intersection()
289 qos->data_size.bits &= new->data_size.bits; irda_qos_compute_intersection()
290 qos->link_disc_time.bits &= new->link_disc_time.bits; irda_qos_compute_intersection()
291 qos->additional_bofs.bits &= new->additional_bofs.bits; irda_qos_compute_intersection()
314 &qos->baud_rate.bits); irda_init_max_qos_capabilies()
319 &qos->link_disc_time.bits); irda_init_max_qos_capabilies()
323 qos->baud_rate.bits &= 0x03ff; irda_init_max_qos_capabilies()
325 qos->window_size.bits = 0x7f; irda_init_max_qos_capabilies()
326 qos->min_turn_time.bits = 0xff; irda_init_max_qos_capabilies()
327 qos->max_turn_time.bits = 0x0f; irda_init_max_qos_capabilies()
328 qos->data_size.bits = 0x3f; irda_init_max_qos_capabilies()
329 qos->link_disc_time.bits &= 0xff; irda_init_max_qos_capabilies()
330 qos->additional_bofs.bits = 0xff; irda_init_max_qos_capabilies()
355 /* We don't really need bits, but easier this way */ irlap_adjust_qos_settings()
357 8, &qos->min_turn_time.bits); irlap_adjust_qos_settings()
434 /* Convert the negotiated bits to values */ irlap_qos_negotiate()
536 param->pv.i = self->qos_rx.baud_rate.bits; irlap_param_baud_rate()
545 final = (__u16) param->pv.i & self->qos_rx.baud_rate.bits; irlap_param_baud_rate()
548 self->qos_tx.baud_rate.bits = final; irlap_param_baud_rate()
549 self->qos_rx.baud_rate.bits = final; irlap_param_baud_rate()
572 param->pv.i = self->qos_rx.link_disc_time.bits; irlap_param_link_disconnect()
579 final = (__u8) param->pv.i & self->qos_rx.link_disc_time.bits; irlap_param_link_disconnect()
582 self->qos_tx.link_disc_time.bits = final; irlap_param_link_disconnect()
583 self->qos_rx.link_disc_time.bits = final; irlap_param_link_disconnect()
604 param->pv.i = self->qos_rx.max_turn_time.bits; irlap_param_max_turn_time()
606 self->qos_tx.max_turn_time.bits = (__u8) param->pv.i; irlap_param_max_turn_time()
626 param->pv.i = self->qos_rx.data_size.bits; irlap_param_data_size()
628 self->qos_tx.data_size.bits = (__u8) param->pv.i; irlap_param_data_size()
649 param->pv.i = self->qos_rx.window_size.bits; irlap_param_window_size()
651 self->qos_tx.window_size.bits = (__u8) param->pv.i; irlap_param_window_size()
670 param->pv.i = self->qos_rx.additional_bofs.bits; irlap_param_additional_bofs()
672 self->qos_tx.additional_bofs.bits = (__u8) param->pv.i; irlap_param_additional_bofs()
692 param->pv.i = self->qos_rx.min_turn_time.bits; irlap_param_min_turn_time()
694 self->qos_tx.min_turn_time.bits = (__u8) param->pv.i; irlap_param_min_turn_time()
750 index = msb_index(qos->baud_rate.bits); irda_qos_bits_to_value()
753 index = msb_index(qos->data_size.bits); irda_qos_bits_to_value()
756 index = msb_index(qos->window_size.bits); irda_qos_bits_to_value()
759 index = msb_index(qos->min_turn_time.bits); irda_qos_bits_to_value()
762 index = msb_index(qos->max_turn_time.bits); irda_qos_bits_to_value()
765 index = msb_index(qos->link_disc_time.bits); irda_qos_bits_to_value()
768 index = msb_index(qos->additional_bofs.bits); irda_qos_bits_to_value()
/linux-4.1.27/drivers/gpu/drm/exynos/
H A Dregs-mixer.h67 /* generates mask for range of bits */
74 /* bits for MXR_STATUS */
84 /* bits for MXR_CFG */
111 /* bits for MXR_GRAPHICn_CFG */
120 /* bits for MXR_GRAPHICn_WH */
126 /* bits for MXR_RESOLUTION */
130 /* bits for MXR_GRAPHICn_SXY */
134 /* bits for MXR_GRAPHICn_DXY */
138 /* bits for MXR_INT_EN */
/linux-4.1.27/arch/x86/include/uapi/asm/
H A Ddebugreg.h14 which debugging register was responsible for the trap. The other bits
17 /* Define reserved bits in DR6 which are always set to 1 */
31 bits - each field corresponds to one of the four debug registers,
35 #define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
36 #define DR_CONTROL_SIZE 4 /* 4 control bits per register */
48 enabled. There are 4 fields of two bits. One bit is "local", meaning
58 #define DR_ENABLE_SIZE 2 /* 2 enable bits per register */
60 #define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */
61 #define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
/linux-4.1.27/drivers/rtc/
H A Drtc-s3c.h31 * TICNT[6:0] contains upper 7 bits
32 * TICNT1[7:0] contains lower 8 bits
39 * TICNT[6:0] contains bits [14:8]
40 * TICNT1[7:0] contains lower 8 bits
41 * TICNT2[16:0] contains upper 17 bits
/linux-4.1.27/arch/xtensa/include/uapi/asm/
H A Dswab.h38 * we cannot assume that the upper 16-bits of the register are __arch_swab16()
44 * to ensure that it uses only the least-significant 16 bits of __arch_swab16()
46 * __asm__ macro follows convention that the upper 16 bits of an __arch_swab16()
49 * bits of the register. __arch_swab16()
54 * (or equivalent) to mask off the upper 16 bits. */ __arch_swab16()
/linux-4.1.27/arch/tile/include/asm/
H A Dpmc.h29 #define TILE_SEL_MASK 0x7f /* 7 bits for event SEL,
31 #define TILE_PLM_MASK 0x780 /* 4 bits priv level msks,
41 #define TILE_SEL_MASK 0x3f /* 6 bits for event SEL,
43 #define TILE_BOX_MASK 0x1c0 /* 3 bits box msks,
45 #define TILE_PLM_MASK 0x3c00 /* 4 bits priv level msks,
/linux-4.1.27/arch/cris/include/uapi/arch-v10/arch/
H A Duser.h5 sensible we let all registers be 32 bits. The csr registers are included
24 unsigned long p0; /* Constant zero (only 8 bits). */
25 unsigned long vr; /* Version register (only 8 bits). */
28 unsigned long p4; /* Constant zero (only 16 bits). */
29 unsigned long ccr; /* Condition code register (only 16 bits). */
/linux-4.1.27/drivers/leds/
H A Dleds-pca955x.c40 * bits the chip supports.
67 int bits; member in struct:pca955x_chipdef
69 int slv_addr_shift; /* Number of bits to ignore */
74 .bits = 2,
79 .bits = 8,
84 .bits = 16,
89 .bits = 4,
120 /* 8 bits per input register */ pca95xx_num_input_regs()
121 static inline int pca95xx_num_input_regs(int bits) pca95xx_num_input_regs() argument
123 return (bits + 7) / 8; pca95xx_num_input_regs()
126 /* 4 bits per LED selector register */ pca95xx_num_led_regs()
127 static inline int pca95xx_num_led_regs(int bits) pca95xx_num_led_regs() argument
129 return (bits + 3) / 4; pca95xx_num_led_regs()
151 pca95xx_num_input_regs(pca955x->chipdef->bits) + 2*n, pca955x_write_psc()
167 pca95xx_num_input_regs(pca955x->chipdef->bits) + 1 + 2*n, pca955x_write_pwm()
180 pca95xx_num_input_regs(pca955x->chipdef->bits) + 4 + n, pca955x_write_ls()
193 pca95xx_num_input_regs(pca955x->chipdef->bits) + 4 + n); pca955x_read_ls()
202 int ls_led; /* which set of bits within LSx to use (0-3) */ pca955x_led_work()
282 id->name, chip->bits, client->addr); pca955x_probe()
288 if (pdata->num_leds != chip->bits) { pca955x_probe()
291 pdata->num_leds, chip->bits); pca955x_probe()
301 sizeof(*pca955x_led) * chip->bits, GFP_KERNEL); pca955x_probe()
311 for (i = 0; i < chip->bits; i++) { pca955x_probe()
342 for (i = 0; i < pca95xx_num_led_regs(chip->bits); i++) pca955x_probe()
371 for (i = 0; i < pca955x->chipdef->bits; i++) { pca955x_remove()
/linux-4.1.27/drivers/s390/cio/
H A Dairq.c116 * @bits: number of bits in the interrupt vector
121 struct airq_iv *airq_iv_create(unsigned long bits, unsigned long flags) airq_iv_create() argument
129 iv->bits = bits; airq_iv_create()
130 size = BITS_TO_LONGS(bits) * sizeof(unsigned long); airq_iv_create()
141 iv->end = bits; airq_iv_create()
148 size = bits * sizeof(unsigned long); airq_iv_create()
154 size = bits * sizeof(unsigned int); airq_iv_create()
189 * airq_iv_alloc - allocate irq bits from an interrupt vector
191 * @num: number of consecutive irq bits to allocate
204 bit = find_first_bit_inv(iv->avail, iv->bits); airq_iv_alloc()
205 while (bit + num <= iv->bits) { airq_iv_alloc()
217 bit = find_next_bit_inv(iv->avail, iv->bits, bit + i + 1); airq_iv_alloc()
219 if (bit + num > iv->bits) airq_iv_alloc()
227 * airq_iv_free - free irq bits of an interrupt vector
230 * @num: number of consecutive irq bits to free
255 * airq_iv_scan - scan interrupt vector for non-zero bits
261 * -1UL if the scan completed without finding any more any non-zero bits.
/linux-4.1.27/arch/tile/lib/
H A Dstrlen_32.c30 uint32_t bits; strlen() local
31 while ((bits = __insn_seqb(v, 0)) == 0) strlen()
34 return ((const char *)p) + (__insn_ctz(bits) >> 3) - s; strlen()
H A Dstrlen_64.c29 uint64_t bits; strlen() local
30 while ((bits = __insn_v1cmpeqi(v, 0)) == 0) strlen()
33 return ((const char *)p) + (CFZ(bits) >> 3) - s; strlen()
/linux-4.1.27/arch/mips/include/uapi/asm/
H A Dkvm.h26 * stored in the lower 32-bits of the struct kvm_regs fields and sign
27 * extended to 64-bits.
48 * bits[63..52] - As per linux/kvm.h
49 * bits[51..32] - Must be zero.
50 * bits[31..16] - Register set.
55 * bits[15..8] - Must be zero.
56 * bits[7..3] - Register 'rd' index.
57 * bits[2..0] - Register 'sel' index.
64 * have its own identifier in bits[31..16].
153 * bits[15..8] - Register subset (see definitions below).
154 * bits[7..5] - Must be zero.
155 * bits[4..0] - Register number within register subset.
/linux-4.1.27/arch/ia64/hp/sim/boot/
H A Dboot_head.S122 st8 [r18]=r0,16 /* clear remaining bits */
124 st8 [r29]=r0,16 /* clear remaining bits */
125 st8 [r18]=r0,16 /* clear remaining bits */
128 st8 [r18]=r0,16 /* clear remaining bits */
131 st8 [r29]=r0,16 /* clear remaining bits */
132 st8 [r18]=r0,16 /* clear remaining bits */
136 st8 [r18]=r0,16 /* clear remaining bits */
138 st8 [r29]=r0,16 /* clear remaining bits */
139 st8 [r18]=r0,16 /* clear remaining bits */
142 st8 [r18]=r0,16 /* clear remaining bits */
144 st8 [r29]=r0,16 /* clear remaining bits */
145 st8 [r18]=r0,16 /* clear remaining bits */
/linux-4.1.27/sound/oss/
H A Dsb_audio.c80 /* setting the appropriate bits of the output control register 4ch to */ sb_audio_open()
82 /* used anywhere else and therefore the DSP bits are *always* ON for */ sb_audio_open()
133 if (!devc->fullduplex || devc->bits == AFMT_S16_LE) sb_set_output_parms()
153 if (!devc->fullduplex || devc->bits != AFMT_S16_LE) sb_set_input_parms()
230 static void sb1_audio_trigger(int dev, int bits) sb1_audio_trigger() argument
234 bits &= devc->irq_mode; sb1_audio_trigger()
236 if (!bits) sb1_audio_trigger()
253 devc->trigger_bits = bits; sb1_audio_trigger()
317 static unsigned int sb1_audio_set_bits(int dev, unsigned int bits) sb1_audio_set_bits() argument
320 return devc->bits = 8; sb1_audio_set_bits()
412 static void sb20_audio_trigger(int dev, int bits) sb20_audio_trigger() argument
415 bits &= devc->irq_mode; sb20_audio_trigger()
417 if (!bits) sb20_audio_trigger()
434 devc->trigger_bits = bits; sb20_audio_trigger()
473 unsigned char bits = 0; sbpro_audio_prepare_for_input() local
477 devc->bits == 16 ? devc->dma16 : devc->dma8; sbpro_audio_prepare_for_input()
480 if (devc->bits == AFMT_S16_LE) sbpro_audio_prepare_for_input()
481 bits = 0x04; /* 16 bit mode */ sbpro_audio_prepare_for_input()
488 sb_dsp_command(devc, 0xa0 | bits); /* Mono input */ sbpro_audio_prepare_for_input()
490 sb_dsp_command(devc, 0xa8 | bits); /* Stereo input */ sbpro_audio_prepare_for_input()
502 unsigned char bits = 0; sbpro_audio_prepare_for_output() local
505 audio_devs[dev]->dmap_out->dma = audio_devs[dev]->dmap_in->dma = devc->bits == 16 ? devc->dma16 : devc->dma8; sbpro_audio_prepare_for_output()
516 if (devc->bits == AFMT_S16_LE) sbpro_audio_prepare_for_output()
517 bits = 0x04; /* 16 bit mode */ sbpro_audio_prepare_for_output()
520 sb_dsp_command(devc, 0xa0 | bits); /* Mono output */ sbpro_audio_prepare_for_output()
522 sb_dsp_command(devc, 0xa8 | bits); /* Stereo output */ sbpro_audio_prepare_for_output()
620 static unsigned int sb16_audio_set_bits(int dev, unsigned int bits) sb16_audio_set_bits() argument
624 if (bits != 0) sb16_audio_set_bits()
626 if (bits == AFMT_U8 || bits == AFMT_S16_LE) sb16_audio_set_bits()
627 devc->bits = bits; sb16_audio_set_bits()
629 devc->bits = AFMT_U8; sb16_audio_set_bits()
632 return devc->bits; sb16_audio_set_bits()
643 devc->bits == AFMT_S16_LE ? sb16_audio_prepare_for_input()
646 else if (devc->bits == AFMT_S16_LE) sb16_audio_prepare_for_input()
669 devc->bits == AFMT_S16_LE ? sb16_audio_prepare_for_output()
672 else if (devc->bits == AFMT_S16_LE) sb16_audio_prepare_for_output()
692 unsigned long bits; sb16_audio_output_block() local
694 if (!devc->fullduplex || devc->bits == AFMT_S16_LE) sb16_audio_output_block()
707 bits = devc->bits; sb16_audio_output_block()
709 devc->bits = (devc->bits == AFMT_S16_LE) ? sb16_audio_output_block()
714 if (devc->bits == AFMT_S16_LE) sb16_audio_output_block()
726 sb_dsp_command(devc, (devc->bits == AFMT_S16_LE ? 0xb6 : 0xc6)); sb16_audio_output_block()
728 (devc->bits == AFMT_S16_LE ? 0x10 : 0))); sb16_audio_output_block()
733 devc->bits = bits; sb16_audio_output_block()
750 if (!devc->fullduplex || devc->bits != AFMT_S16_LE) sb16_audio_start_input()
762 if (devc->bits == AFMT_S16_LE) sb16_audio_start_input()
774 sb_dsp_command(devc, (devc->bits == AFMT_S16_LE ? 0xbe : 0xce)); sb16_audio_start_input()
776 (devc->bits == AFMT_S16_LE ? 0x10 : 0))); sb16_audio_start_input()
783 static void sb16_audio_trigger(int dev, int bits) sb16_audio_trigger() argument
787 int bits_16 = bits & devc->irq_mode_16; sb16_audio_trigger()
788 bits &= devc->irq_mode; sb16_audio_trigger()
790 if (!bits && !bits_16) sb16_audio_trigger()
794 if (bits) sb16_audio_trigger()
834 devc->trigger_bits = bits | bits_16; sb16_audio_trigger()
862 else if (devc->bits == AFMT_S16_LE) sb16_copy_from_user()
865 /* max_in >> 1, max number of samples in ( 16 bits ) */ sb16_copy_from_user()
866 /* max_out, max number of samples out ( 8 bits ) */ sb16_copy_from_user()
867 /* len, number of samples that will be taken ( 16 bits )*/ sb16_copy_from_user()
868 /* c, count of samples remaining in buffer ( 16 bits )*/ sb16_copy_from_user()
869 /* p, count of samples already processed ( 16 bits )*/ sb16_copy_from_user()
888 /* used = ( samples * 16 bits size ) */ sb16_copy_from_user()
890 /* returned = ( samples * 8 bits size ) */ sb16_copy_from_user()
896 /* max_in, max number of samples in ( 8 bits ) */ sb16_copy_from_user()
897 /* max_out >> 1, max number of samples out ( 16 bits ) */ sb16_copy_from_user()
898 /* len, number of samples that will be taken ( 8 bits )*/ sb16_copy_from_user()
899 /* c, count of samples remaining in buffer ( 8 bits )*/ sb16_copy_from_user()
900 /* p, count of samples already processed ( 8 bits )*/ sb16_copy_from_user()
918 /* used = ( samples * 8 bits size ) */ sb16_copy_from_user()
920 /* returned = ( samples * 16 bits size ) */ sb16_copy_from_user()
/linux-4.1.27/drivers/net/ethernet/neterion/vxge/
H A Dvxge-reg.h23 * vxge_vBIT(val, loc, sz) - set bits at offset
29 * vxge_bVALn(bits, loc, n) - Get the value of n bits at location
31 #define vxge_bVALn(bits, loc, n) \
32 ((((u64)bits) >> (64-(loc+n))) & ((0x1ULL << n) - 1))
34 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits) \
35 vxge_bVALn(bits, 0, 16)
36 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits) \
37 vxge_bVALn(bits, 48, 8)
38 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits) \
39 vxge_bVALn(bits, 56, 8)
41 #define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(bits) \
42 vxge_bVALn(bits, 3, 5)
43 #define VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(bits) \
44 vxge_bVALn(bits, 5, 3)
89 #define VXGE_HW_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(bits) vxge_bVALn(bits, 3, 1)
91 #define VXGE_HW_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(bits) \
92 vxge_bVALn(bits, 0, 32)
94 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(bits) \
95 vxge_bVALn(bits, 50, 14)
97 #define VXGE_HW_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(bits) \
98 vxge_bVALn(bits, 0, 17)
100 #define VXGE_HW_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER(bits) \
101 vxge_bVALn(bits, 3, 5)
103 #define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(bits) \
104 vxge_bVALn(bits, 17, 15)
122 #define VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(bits) bits
123 #define VXGE_HW_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(bits) bits
125 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR0(bits) \
126 vxge_bVALn(bits, 1, 15)
127 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR1(bits) \
128 vxge_bVALn(bits, 17, 15)
129 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR2(bits) \
130 vxge_bVALn(bits, 33, 15)
163 #define VXGE_HW_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(bits) \
164 vxge_bVALn(bits, 0, 48)
167 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \
168 vxge_bVALn(bits, 0, 48)
172 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits) \
173 vxge_bVALn(bits, 55, 5)
176 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits) \
177 vxge_bVALn(bits, 62, 2)
204 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) \
205 vxge_bVALn(bits, 0, 48)
208 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(bits) vxge_bVALn(bits, 0, 12)
211 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_ETYPE(bits) vxge_bVALn(bits, 0, 11)
214 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(bits) \
215 vxge_bVALn(bits, 3, 1)
217 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(bits) \
218 vxge_bVALn(bits, 7, 1)
220 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(bits) \
221 vxge_bVALn(bits, 8, 16)
224 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_EN(bits) \
225 vxge_bVALn(bits, 3, 1)
227 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(bits) \
228 vxge_bVALn(bits, 4, 4)
231 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(bits) \
232 vxge_bVALn(bits, 10, 2)
238 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(bits) \
239 vxge_bVALn(bits, 15, 1)
241 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(bits) \
242 vxge_bVALn(bits, 19, 1)
244 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(bits) \
245 vxge_bVALn(bits, 23, 1)
247 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(bits) \
248 vxge_bVALn(bits, 27, 1)
250 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(bits) \
251 vxge_bVALn(bits, 31, 1)
253 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(bits) \
254 vxge_bVALn(bits, 35, 1)
256 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(bits) \
257 vxge_bVALn(bits, 39, 1)
259 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_REPL_ENTRY_EN(bits) \
260 vxge_bVALn(bits, 43, 1)
263 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(bits) \
264 vxge_bVALn(bits, 3, 1)
266 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_BUCKET_DATA(bits) \
267 vxge_bVALn(bits, 9, 7)
271 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_NUM(bits) \
272 vxge_bVALn(bits, 0, 8)
275 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(bits) \
276 vxge_bVALn(bits, 8, 1)
278 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_DATA(bits) \
279 vxge_bVALn(bits, 9, 7)
282 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_NUM(bits) \
283 vxge_bVALn(bits, 16, 8)
286 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(bits) \
287 vxge_bVALn(bits, 24, 1)
289 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_DATA(bits) \
290 vxge_bVALn(bits, 25, 7)
293 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_NUM(bits) \
294 vxge_bVALn(bits, 0, 8)
297 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(bits) \
298 vxge_bVALn(bits, 8, 1)
300 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_DATA(bits) \
301 vxge_bVALn(bits, 9, 7)
304 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_NUM(bits) \
305 vxge_bVALn(bits, 16, 8)
308 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(bits) \
309 vxge_bVALn(bits, 24, 1)
311 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_DATA(bits) \
312 vxge_bVALn(bits, 25, 7)
316 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(bits) \
317 vxge_bVALn(bits, 0, 32)
320 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(bits) \
321 vxge_bVALn(bits, 32, 32)
325 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(bits) \
326 vxge_bVALn(bits, 0, 16)
329 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_DA_MASK(bits) \
330 vxge_bVALn(bits, 16, 16)
333 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_SA_MASK(bits) \
334 vxge_bVALn(bits, 32, 4)
337 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_DA_MASK(bits) \
338 vxge_bVALn(bits, 36, 4)
341 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4SP_MASK(bits) \
342 vxge_bVALn(bits, 40, 2)
345 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4DP_MASK(bits) \
346 vxge_bVALn(bits, 42, 2)
350 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_KEY_KEY(bits) \
351 vxge_bVALn(bits, 0, 64)
354 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_QOS_ENTRY_EN(bits) \
355 vxge_bVALn(bits, 3, 1)
358 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DS_ENTRY_EN(bits) \
359 vxge_bVALn(bits, 3, 1)
362 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \
363 vxge_bVALn(bits, 0, 48)
369 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_NUM(bits) \
370 vxge_bVALn(bits, 0, 8)
373 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_ENTRY_EN(bits) \
374 vxge_bVALn(bits, 8, 1)
376 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_DATA(bits) \
377 vxge_bVALn(bits, 9, 7)
380 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_NUM(bits) \
381 vxge_bVALn(bits, 16, 8)
384 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_ENTRY_EN(bits) \
385 vxge_bVALn(bits, 24, 1)
387 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_DATA(bits) \
388 vxge_bVALn(bits, 25, 7)
391 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_NUM(bits) \
392 vxge_bVALn(bits, 32, 8)
395 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_ENTRY_EN(bits) \
396 vxge_bVALn(bits, 40, 1)
398 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_DATA(bits) \
399 vxge_bVALn(bits, 41, 7)
402 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_NUM(bits) \
403 vxge_bVALn(bits, 48, 8)
406 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_ENTRY_EN(bits) \
407 vxge_bVALn(bits, 56, 1)
409 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_DATA(bits) \
410 vxge_bVALn(bits, 57, 7)
426 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(bits) \
427 vxge_bVALn(bits, 0, 8)
429 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(bits) \
430 vxge_bVALn(bits, 8, 8)
432 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(bits) \
433 vxge_bVALn(bits, 16, 16)
437 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(bits) \
438 vxge_bVALn(bits, 32, 8)
440 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(bits) \
441 vxge_bVALn(bits, 40, 8)
443 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(bits) \
444 vxge_bVALn(bits, 48, 16)
447 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(bits) \
448 vxge_bVALn(bits, 0, 8)
450 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(bits) \
451 vxge_bVALn(bits, 8, 8)
453 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(bits) \
454 vxge_bVALn(bits, 16, 16)
458 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(bits) \
459 vxge_bVALn(bits, 32, 8)
461 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(bits) \
462 vxge_bVALn(bits, 40, 8)
464 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(bits) \
465 vxge_bVALn(bits, 48, 16)
467 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(bits) vxge_bVALn(bits, 0, 8)
469 #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_GET_PPIF_SRPCIM_TO_VPATH_ALARM(bits)\
470 vxge_bVALn(bits, 0, 18)
472 #define VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(bits) \
473 vxge_bVALn(bits, 48, 16)
474 #define VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(bits) \
475 vxge_bVALn(bits, 32, 32)
476 #define VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(bits) vxge_bVALn(bits, 48, 16)
477 #define VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(bits) \
478 vxge_bVALn(bits, 0, 32)
479 #define VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(bits) \
480 vxge_bVALn(bits, 0, 32)
481 #define VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(bits) \
482 vxge_bVALn(bits, 0, 32)
483 #define VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(bits) (bits)
484 #define VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(bits) (bits)
485 #define VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(bits) \
486 vxge_bVALn(bits, 32, 32)
487 #define VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(bits) \
488 vxge_bVALn(bits, 32, 32)
489 #define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(bits) \
490 vxge_bVALn(bits, 0, 32)
491 #define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(bits) \
492 vxge_bVALn(bits, 32, 32)
493 #define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(bits) \
494 vxge_bVALn(bits, 0, 32)
495 #define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(bits) \
496 vxge_bVALn(bits, 32, 32)
497 #define VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(bits) \
498 vxge_bVALn(bits, 0, 32)
499 #define VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(bits) \
500 vxge_bVALn(bits, 32, 32)
501 #define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(bits\
502 ) vxge_bVALn(bits, 48, 16)
503 #define VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(bits) vxge_bVALn(bits, 0, 16)
504 #define VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(bits) \
505 vxge_bVALn(bits, 16, 16)
506 #define VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(bits) \
507 vxge_bVALn(bits, 32, 16)
508 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(bits) vxge_bVALn(bits, 0, 16)
509 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(bits) \
510 vxge_bVALn(bits, 16, 16)
511 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(bits) \
512 vxge_bVALn(bits, 32, 16)
514 #define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(bits) \
515 vxge_bVALn(bits, 0, 32)
516 #define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(bits) \
517 vxge_bVALn(bits, 32, 32)
518 #define VXGE_HW_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(bits\
519 ) vxge_bVALn(bits, 32, 32)
520 #define VXGE_HW_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(bits\
521 ) vxge_bVALn(bits, 32, 32)
523 VXGE_HW_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(bits) \
524 vxge_bVALn(bits, 32, 32)
525 #define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(bits) \
526 vxge_bVALn(bits, 0, 32)
527 #define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(bits) \
528 vxge_bVALn(bits, 32, 32)
529 #define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(bits) \
530 vxge_bVALn(bits, 0, 32)
531 #define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(bits) \
532 vxge_bVALn(bits, 32, 32)
533 #define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(bits) \
534 vxge_bVALn(bits, 0, 32)
535 #define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(bits) \
536 vxge_bVALn(bits, 32, 32)
537 #define VXGE_HW_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(bits) \
538 vxge_bVALn(bits, 32, 32)
539 #define VXGE_HW_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(bits) \
540 vxge_bVALn(bits, 32, 32)
542 #define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_MSG(bits) vxge_bVALn(bits, 0, 32)
543 #define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_CPL(bits) vxge_bVALn(bits, 32, 32)
544 #define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT0(bits) vxge_bVALn(bits, 0, 32)
545 #define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT1(bits) vxge_bVALn(bits, 32, 32)
546 #define VXGE_HW_DEBUG_STATS2_GET_RSTDROP_CLIENT2(bits) vxge_bVALn(bits, 0, 32)
547 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_PH(bits) vxge_bVALn(bits, 0, 16)
548 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(bits) vxge_bVALn(bits, 16, 16)
549 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(bits) vxge_bVALn(bits, 32, 16)
550 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_PD(bits) vxge_bVALn(bits, 0, 16)
551 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(bits) bVAL(bits, 16, 16)
552 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(bits) vxge_bVALn(bits, 32, 16)
554 #define VXGE_HW_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(bits) \
555 vxge_bVALn(bits, 32, 32)
557 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(bits) \
558 vxge_bVALn(bits, 0, 8)
559 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(bits) \
560 vxge_bVALn(bits, 8, 8)
561 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(bits) \
562 vxge_bVALn(bits, 16, 8)
564 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(bits) \
565 vxge_bVALn(bits, 0, 8)
566 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(bits) \
567 vxge_bVALn(bits, 8, 8)
568 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(bits) \
569 vxge_bVALn(bits, 16, 8)
/linux-4.1.27/drivers/net/wan/lmc/
H A Dlmc.h18 void lmc_gpio_mkinput(lmc_softc_t * const sc, u32 bits);
19 void lmc_gpio_mkoutput(lmc_softc_t * const sc, u32 bits);
/linux-4.1.27/drivers/crypto/vmx/
H A Daesp8-ppc.h11 int aes_p8_set_encrypt_key(const u8 *userKey, const int bits,
13 int aes_p8_set_decrypt_key(const u8 *userKey, const int bits,
/linux-4.1.27/include/uapi/asm-generic/
H A Dioctl.h4 /* ioctl command encoding: 32 bits total, command in lower 16 bits,
5 * size of the parameter structure in the lower 14 bits of the
6 * upper 16 bits.
10 * The highest 2 bits are reserved for indicating the ``access mode''.
17 * a type field. De facto, however, the top 8 bits of the lower 16
18 * bits are indeed used as a type field, so we might just as well make
49 * Direction bits, which any architecture can choose to override
/linux-4.1.27/include/media/
H A Dsoc_mediabus.h21 * @SOC_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
22 * possibly incomplete byte high bits are padding
23 * @SOC_MBUS_PACKING_2X8_PADLO: as above, but low bits are padding
24 * @SOC_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
25 * to 16 bits
29 * @SOC_MBUS_PACKING_EXTEND32: sample width (e.g., 24 bits) has to be extended
30 * to 32 bits
77 * @bits_per_sample: How many bits the bridge has to sample
/linux-4.1.27/include/uapi/linux/netfilter_ipv4/
H A Dipt_ECN.h17 #define IPT_ECN_OP_SET_IP 0x01 /* set ECN bits of IPv4 header */
28 __u8 ece:1, cwr:1; /* TCP ECT bits */
/linux-4.1.27/arch/nios2/include/asm/
H A Dpgtable-bits.h14 * These are actual hardware defined protection bits in the tlbacc register
27 * Software defined bits. They are ignored by the hardware and always read back
/linux-4.1.27/arch/m32r/include/asm/
H A Dflat.h30 return relval & 0x00ffffff; /* Mask out top 8-bits */ flat_get_relocate_addr()
37 #define FLAT_M32R_32 0x00 /* 32bits reloc */
38 #define FLAT_M32R_24 0x01 /* unsigned 24bits reloc */
39 #define FLAT_M32R_16 0x02 /* 16bits reloc */
40 #define FLAT_M32R_LO16 0x03 /* signed low 16bits reloc (low()) */
41 #define FLAT_M32R_LO16_DATA 0x04 /* signed low 16bits reloc (low())
43 /* High 16bits of an address used
50 /* High 16bits of an address used
H A Dsignal.h13 typedef unsigned long old_sigset_t; /* at least 32 bits */
/linux-4.1.27/arch/arm/mach-omap2/
H A Dcm2xxx_3xxx.h64 static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, omap2_cm_rmw_mod_reg_bits() argument
71 v |= bits; omap2_cm_rmw_mod_reg_bits()
89 static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) omap2_cm_set_mod_reg_bits() argument
91 return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx); omap2_cm_set_mod_reg_bits()
94 static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) omap2_cm_clear_mod_reg_bits() argument
96 return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); omap2_cm_clear_mod_reg_bits()
106 /* CM register bits shared between 24XX and 3430 */
H A Dprcm-common.h63 /* 24XX register bits shared between CM & PRM registers */
65 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
105 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
119 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
127 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
167 /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
185 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
191 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
199 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
204 /* 3430 register bits shared between CM & PRM registers */
206 /* CM_REVISION, PRM_REVISION shared bits */
210 /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
213 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
253 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
257 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
301 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
309 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
315 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
319 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
336 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
341 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
374 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
375 /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
376 * be ST_* bits instead? */
384 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
416 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
459 * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
477 * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
/linux-4.1.27/arch/arm/mach-iop32x/include/mach/
H A Dhardware.h28 * Generic chipset bits
33 * Board specific bits
/linux-4.1.27/arch/arm/mach-iop33x/include/mach/
H A Dhardware.h31 * Generic chipset bits
37 * Board specific bits
/linux-4.1.27/arch/alpha/include/uapi/asm/
H A Dfpu.h35 * bits are stored in the "ieee_state" field of "struct thread_info".
36 * Thus, the bits are defined so as not to conflict with the
38 * we want to make these bits compatible with OSF/1 so
59 /* status bits coming from fpcr: */
82 * Convert the software IEEE trap enable and status bits into the
86 * software bits identical to the hardware bits. The chip designers
87 * receive my thanks for making all the not-implemented fpcr bits
H A Dposix_types.h13 typedef unsigned long __kernel_sigset_t; /* at least 32 bits */
/linux-4.1.27/scripts/gdb/linux/
H A Dcpus.py70 mask = gdb.parse_and_eval(mask_name + ".bits")
79 bits = 0
82 while bits == 0:
86 bits = mask[entry]
87 if bits != 0:
91 while bits & 1 == 0:
92 bits >>= 1
97 bits >>= 1
/linux-4.1.27/include/linux/iio/imu/
H A Dadis.h160 #define ADIS_VOLTAGE_CHAN(addr, si, chan, name, info_all, bits) { \
172 .realbits = (bits), \
178 #define ADIS_SUPPLY_CHAN(addr, si, info_all, bits) \
179 ADIS_VOLTAGE_CHAN(addr, si, 0, "supply", info_all, bits)
181 #define ADIS_AUX_ADC_CHAN(addr, si, info_all, bits) \
182 ADIS_VOLTAGE_CHAN(addr, si, 1, NULL, info_all, bits)
184 #define ADIS_TEMP_CHAN(addr, si, info_all, bits) { \
196 .realbits = (bits), \
202 #define ADIS_MOD_CHAN(_type, mod, addr, si, info_sep, info_all, bits) { \
214 .realbits = (bits), \
220 #define ADIS_ACCEL_CHAN(mod, addr, si, info_sep, info_all, bits) \
221 ADIS_MOD_CHAN(IIO_ACCEL, mod, addr, si, info_sep, info_all, bits)
223 #define ADIS_GYRO_CHAN(mod, addr, si, info_sep, info_all, bits) \
224 ADIS_MOD_CHAN(IIO_ANGL_VEL, mod, addr, si, info_sep, info_all, bits)
226 #define ADIS_INCLI_CHAN(mod, addr, si, info_sep, info_all, bits) \
227 ADIS_MOD_CHAN(IIO_INCLI, mod, addr, si, info_sep, info_all, bits)
229 #define ADIS_ROT_CHAN(mod, addr, si, info_sep, info_all, bits) \
230 ADIS_MOD_CHAN(IIO_ROT, mod, addr, si, info_sep, info_all, bits)
/linux-4.1.27/drivers/isdn/hisax/
H A Dhfc_pci.h92 /* bits in status register (READ) */
100 /* bits in CTMT (Write) */
111 /* bits in CIRM (Write) */
117 /* bits in INT_M1 and INT_S1 */
127 /* bits in INT_M2 */
134 /* bits in STATES */
141 /* bits in HFCD_MST_MODE */
144 /* remaining bits are for codecs control */
146 /* bits in HFCD_SCTRL */
157 /* bits in SCTRL_E */
164 /* bits in FIFO_EN register */
H A Dhfc_sx.h98 /* bits in status register (READ) */
106 /* bits in CTMT (Write) */
117 /* bits in CIRM (Write) */
124 /* bits in INT_M1 and INT_S1 */
134 /* bits in INT_M2 */
140 /* bits in STATES */
147 /* bits in HFCD_MST_MODE */
150 /* remaining bits are for codecs control */
152 /* bits in HFCD_SCTRL */
163 /* bits in SCTRL_E */
/linux-4.1.27/include/uapi/sound/
H A Dasound_fm.h49 unsigned char harmonic; /* 4 bits: harmonic and multiplier */
50 unsigned char scale_level; /* 2 bits: decrease output freq rises */
51 unsigned char volume; /* 6 bits: volume */
53 unsigned char attack; /* 4 bits: attack rate */
54 unsigned char decay; /* 4 bits: decay rate */
55 unsigned char sustain; /* 4 bits: sustain level */
56 unsigned char release; /* 4 bits: release rate */
58 unsigned char feedback; /* 3 bits: feedback for op0 */
62 unsigned char waveform; /* 3 bits: waveform shape */
72 unsigned char octave; /* 3 bits: what octave to play */
73 unsigned int fnum; /* 10 bits: frequency number */
/linux-4.1.27/arch/mips/lantiq/xway/
H A Dgptu.c98 int ret = request_irq(irqres[clk->bits].start, timer_irq_handler, gptu_enable()
106 GPTU_CON(clk->bits)); gptu_enable()
107 gptu_w32(1, GPTU_RLD(clk->bits)); gptu_enable()
108 gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN); gptu_enable()
109 gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits)); gptu_enable()
115 gptu_w32(0, GPTU_RUN(clk->bits)); gptu_disable()
116 gptu_w32(0, GPTU_CON(clk->bits)); gptu_disable()
117 gptu_w32(0, GPTU_RLD(clk->bits)); gptu_disable()
118 gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN); gptu_disable()
119 free_irq(irqres[clk->bits].start, NULL); gptu_disable()
132 clk->bits = timer; clkdev_add_gptu()
/linux-4.1.27/drivers/net/wireless/brcm80211/brcmsmac/phy/
H A Dphy_qmath.c21 * To fit the output into 16 bits the 32 bit multiplication result is right
22 * shifted by 16 bits.
31 * in 16 bits. To fit the multiplication result into 16 bits the multiplication
32 * result is right shifted by 15 bits. Right shifting 15 bits instead of 16 bits
50 * result. If the result overflow 32 bits, the output will be saturated to
51 * 32bits.
67 * result. If the result overflow 16 bits, the output will be saturated to
68 * 16bits.
86 * result. If the result overflow 16 bits, the output will be saturated to
87 * 16bits.
164 * Description: This function return the number of redundant sign bits in a
260 /* take the table index as the LOG2_OF_LOG_TABLE_SIZE bits right of the qm_log10()
294 /* bring all the important bits into lower 16 bits */ qm_log10()
/linux-4.1.27/fs/hfs/
H A Dbitmap.c11 * search/set/clear bits.
20 * Given a block of memory, its length in bits, and a starting bit number,
21 * determine the number of the first zero bits (in left-to-right ordering)
24 * Returns >= 'size' if no zero bits are found in the range.
26 * Accesses memory in 32-bit aligned chunks of 32-bits and thus
43 /* scan the first partial u32 for zero bits */ hfs_find_set_zero_bits()
116 * Search for 'num_bits' consecutive cleared bits in the bitmap blocks of
123 * u16 *num_bits: Pointer to the number of cleared bits
126 * u16 *num_bits: The number of consecutive clear bits of the
130 * The number of the first bit of the range of cleared bits which has been
135 * the number of cleared bits to find.
174 * Clear the requested bits in the volume bitmap of the hfs filesystem
178 * u16 count: The number of bits
183 * -1: One of the bits was already clear. This is a strange
185 * -2: One or more of the bits are out of range of the bitmap.
189 * Starting with bit number 'start', 'count' bits in the volume bitmap
204 /* are all of the bits in range? */ hfs_clear_vbm_bits()
/linux-4.1.27/lib/zlib_deflate/
H A Ddeftree.c49 /* Bit length codes must not exceed MAX_BL_BITS bits */
55 /* repeat previous bit length 3-6 times (2 bits of repeat count) */
58 /* repeat a zero length 3-10 times (3 bits of repeat count) */
61 /* repeat a zero length 11-138 times (7 bits of repeat count) */
63 static const int extra_lbits[LENGTH_CODES] /* extra bits for each length code */
66 static const int extra_dbits[D_CODES] /* extra bits for each distance code */
69 static const int extra_blbits[BL_CODES]/* extra bits for each bit length code */
79 /* Number of bits used within bi_buf. (bi_buf might be implemented on
80 * more than 16 bits on some systems.)
96 * 5 bits.)
101 * 3 .. 258, the last 256 values correspond to the top 8 bits of
116 const int *extra_bits; /* extra bits for each code or NULL */
173 * Send a value on a given number of bits.
174 * IN assertion: length <= 16 and value fits in length bits.
182 int length /* number of bits */ send_bits()
189 /* If not enough room in bi_buf, use (valid) bits from bi_buf and send_bits()
190 * (16 - bi_valid) bits from value, leaving (width - (16-bi_valid)) send_bits()
191 * unused bits in value. send_bits()
229 int bits; /* bit counter */ tr_static_init() local
248 * in two different ways: code 284 + 5 bits or code 285, so we tr_static_init()
272 for (bits = 0; bits <= MAX_BITS; bits++) bl_count[bits] = 0; tr_static_init()
420 int bits; /* bit length */ gen_bitlen() local
421 int xbits; /* extra bits */ gen_bitlen()
425 for (bits = 0; bits <= MAX_BITS; bits++) s->bl_count[bits] = 0; gen_bitlen()
434 bits = tree[tree[n].Dad].Len + 1; gen_bitlen()
435 if (bits > max_length) bits = max_length, overflow++; gen_bitlen()
436 tree[n].Len = (ush)bits; gen_bitlen()
441 s->bl_count[bits]++; gen_bitlen()
445 s->opt_len += (ulg)f * (bits + xbits); gen_bitlen()
455 bits = max_length-1; gen_bitlen()
456 while (s->bl_count[bits] == 0) bits--; gen_bitlen()
457 s->bl_count[bits]--; /* move one leaf down the tree */ gen_bitlen()
458 s->bl_count[bits+1] += 2; /* move one overflow item as its brother */ gen_bitlen()
471 for (bits = max_length; bits != 0; bits--) { gen_bitlen()
472 n = s->bl_count[bits]; gen_bitlen()
476 if (tree[m].Len != (unsigned) bits) { gen_bitlen()
477 Trace((stderr,"code %d bits %d->%d\n", m, tree[m].Len, bits)); gen_bitlen()
478 s->opt_len += ((long)bits - (long)tree[m].Len) gen_bitlen()
480 tree[m].Len = (ush)bits; gen_bitlen()
503 int bits; /* bit index */ gen_codes() local
509 for (bits = 1; bits <= MAX_BITS; bits++) { gen_codes()
510 next_code[bits] = code = (code + bl_count[bits-1]) << 1; gen_codes()
522 /* Now reverse the bits */ gen_codes()
575 /* node is 0 or 1 so it does not have extra bits */ build_tree()
737 * the lengths of the bit lengths codes and the 5+5+4 bits for the counts. build_bl_tree()
820 * This takes 10 bits, of which 7 may remain in the bit buffer.
821 * The current inflate code requires 9 bits of lookahead. If the
823 * on 5 bits or less, inflate may have only 5+3 bits of lookahead to decode
837 /* Of the 10 bits for the empty block, we have already sent zlib_tr_align()
838 * (10 - bi_valid) bits. The lookahead for the last real code (before zlib_tr_align()
1028 int extra; /* number of extra bits to send */ compress_block()
1043 send_bits(s, lc, extra); /* send the extra length bits */ compress_block()
1053 send_bits(s, dist, extra); /* send the extra distance bits */ compress_block()
/linux-4.1.27/sound/arm/
H A Daaci.h22 #define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */
23 #define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */
24 #define AACI_SR 0x008 /* 12 bits Status */
25 #define AACI_ISR 0x00c /* 7 bits Int Status */
26 #define AACI_IE 0x010 /* 7 bits Int Enable */
56 #define CR_SZ16 (0 << 13) /* 16 bits */
57 #define CR_SZ18 (1 << 13) /* 18 bits */
58 #define CR_SZ20 (2 << 13) /* 20 bits */
59 #define CR_SZ12 (3 << 13) /* 12 bits */
75 * status register bits. P49
91 * interrupt status register bits.
102 * interrupt enable register bits.
135 * slot flag register bits. P56
170 * Main control register bits. P62
185 * Reset register bits. P65
190 * Sync register bits. P65
195 * Main flag register bits. P66
/linux-4.1.27/drivers/net/ethernet/emulex/benet/
H A Dbe_hw.h21 * it writes the register with hi=1 and the upper bits of the physical address
24 * bits in the address. It must poll the ready bit until the command is
86 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
123 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
124 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
125 #define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */
132 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
138 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
139 #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
140 #define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14
144 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
150 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
152 #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
153 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
157 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
159 #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
163 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
165 #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
186 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
199 __le32 frag_len; /* dword 3: bits 0 - 15 */
228 #define TX_HDR_WRB_NUM_SHIFT 13 /* word 2: bits 13:17 */
229 #define TX_HDR_WRB_NUM_MASK 0x1F /* word 2: bits 13:17 */
/linux-4.1.27/arch/ia64/include/asm/sn/
H A Dtioca.h74 * macro declaration to mask the bit. Fields consisting of multiple bits
75 * have two declarations: one to mask the proper bits in a register, and
94 /* bits 15:14 unused */
98 /* bits 23:20 unused */
101 /* bits 35:32 unused */
108 /* bits 63:52 unused */
117 /* bits 27:26 unused */
127 /* bits 39:37 unused */
130 /* bits 55:53 unused */
133 /* bits 59:58 unused */
151 /* bits 63:24 unused */
173 /* bits 63:58 unused */
179 /* bits 11:3 unused */
188 /* bits 2:0 unused */
191 /* bits 55:54 unused */
202 /* bits 3:1 unused */
221 /* bits 63:22 unused */
238 /* bits 15:13 unused */
252 /* bits 63:29 unused */
271 /* bits 62:36 unused */
275 /* bits 2:0 unused */
278 /* bits 63:56 unused */
284 /* bits 63:9 unused */
289 /* bits 3:2 unused */
292 /* bits 63:40 unused */
318 /* bits 63:50 unused */
323 /* bits 7:6 unused */
326 /* bits 11:10 unused */
329 /* bits 27:26 unused */
331 /* bits 63:29 unused */
335 /* bits 19:0 unused */
338 /* bits 27:26 unused */
340 /* bits 63:29 unused */
373 /* bits 63:60 unused */
430 /* bits 63:2 unused */
434 /* bits 11:1 unused */
437 /* bits 63:56 unused */
442 /* bits 62:56 unused */
568 * DMA's, all 32 bits of the bus address are used to form the lower 32 bits
569 * of the coretalk address, and coretalk bits 38:32 come from a register.
572 * such that their lower 32 bits fall in the 0xC0000000-0xffffffff range
/linux-4.1.27/drivers/misc/eeprom/
H A Deeprom_93xx46.c45 int bits, ret; eeprom_93xx46_bin_read() local
62 bits = 10; eeprom_93xx46_bin_read()
65 bits = 9; eeprom_93xx46_bin_read()
76 t[0].bits_per_word = bits; eeprom_93xx46_bin_read()
108 int bits, ret; eeprom_93xx46_ew() local
114 bits = 10; eeprom_93xx46_ew()
117 bits = 9; eeprom_93xx46_ew()
127 t.bits_per_word = bits; eeprom_93xx46_ew()
155 int bits, data_len, ret; eeprom_93xx46_write_word() local
162 bits = 10; eeprom_93xx46_write_word()
166 bits = 9; eeprom_93xx46_write_word()
177 t[0].bits_per_word = bits; eeprom_93xx46_write_word()
250 int bits, ret; eeprom_93xx46_eral() local
256 bits = 10; eeprom_93xx46_eral()
259 bits = 9; eeprom_93xx46_eral()
267 t.bits_per_word = bits; eeprom_93xx46_eral()
/linux-4.1.27/drivers/staging/media/lirc/
H A Dlirc_bt829.c229 unsigned char bits; do_i2c_stop() local
231 bits = do_get_bits() & 0xFD; do_i2c_stop()
232 do_set_bits(bits); do_i2c_stop()
235 bits |= 1; do_i2c_stop()
236 do_set_bits(bits); do_i2c_stop()
239 bits |= 2; do_i2c_stop()
240 do_set_bits(bits); do_i2c_stop()
241 bits = 3; do_i2c_stop()
242 do_set_bits(bits); do_i2c_stop()
359 unsigned char bits; do_get_bits() local
368 bits = 0; do_get_bits()
370 bits |= 2; do_get_bits()
372 bits &= 0xFD; do_get_bits()
376 bits |= 1; do_get_bits()
378 bits &= 0xFE; do_get_bits()
380 return bits; do_get_bits()
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dramht.h7 int bits; member in struct:nvkm_ramht
/linux-4.1.27/drivers/clk/mmp/
H A Dreset.h11 u32 bits; member in struct:mmp_clk_reset_cell
/linux-4.1.27/drivers/usb/serial/
H A Dcp210x.c361 * Values less than 16 bits wide are sent directly
493 * Reads the baud rate, data bits, parity, stop bits and flow control mode
523 unsigned int bits; cp210x_get_termios_port() local
532 cp210x_get_config(port, CP210X_GET_LINE_CTL, &bits, 2); cp210x_get_termios_port()
534 switch (bits & BITS_DATA_MASK) { cp210x_get_termios_port()
536 dev_dbg(dev, "%s - data bits = 5\n", __func__); cp210x_get_termios_port()
540 dev_dbg(dev, "%s - data bits = 6\n", __func__); cp210x_get_termios_port()
544 dev_dbg(dev, "%s - data bits = 7\n", __func__); cp210x_get_termios_port()
548 dev_dbg(dev, "%s - data bits = 8\n", __func__); cp210x_get_termios_port()
552 dev_dbg(dev, "%s - data bits = 9 (not supported, using 8 data bits)\n", __func__); cp210x_get_termios_port()
554 bits &= ~BITS_DATA_MASK; cp210x_get_termios_port()
555 bits |= BITS_DATA_8; cp210x_get_termios_port()
556 cp210x_set_config(port, CP210X_SET_LINE_CTL, &bits, 2); cp210x_get_termios_port()
559 dev_dbg(dev, "%s - Unknown number of data bits, using 8\n", __func__); cp210x_get_termios_port()
561 bits &= ~BITS_DATA_MASK; cp210x_get_termios_port()
562 bits |= BITS_DATA_8; cp210x_get_termios_port()
563 cp210x_set_config(port, CP210X_SET_LINE_CTL, &bits, 2); cp210x_get_termios_port()
567 switch (bits & BITS_PARITY_MASK) { cp210x_get_termios_port()
593 bits &= ~BITS_PARITY_MASK; cp210x_get_termios_port()
594 cp210x_set_config(port, CP210X_SET_LINE_CTL, &bits, 2); cp210x_get_termios_port()
599 switch (bits & BITS_STOP_MASK) { cp210x_get_termios_port()
601 dev_dbg(dev, "%s - stop bits = 1\n", __func__); cp210x_get_termios_port()
604 dev_dbg(dev, "%s - stop bits = 1.5 (not supported, using 1 stop bit)\n", __func__); cp210x_get_termios_port()
605 bits &= ~BITS_STOP_MASK; cp210x_get_termios_port()
606 cp210x_set_config(port, CP210X_SET_LINE_CTL, &bits, 2); cp210x_get_termios_port()
609 dev_dbg(dev, "%s - stop bits = 2\n", __func__); cp210x_get_termios_port()
613 dev_dbg(dev, "%s - Unknown number of stop bits, using 1 stop bit\n", __func__); cp210x_get_termios_port()
614 bits &= ~BITS_STOP_MASK; cp210x_get_termios_port()
615 cp210x_set_config(port, CP210X_SET_LINE_CTL, &bits, 2); cp210x_get_termios_port()
689 unsigned int bits; cp210x_set_termios() local
698 /* If the number of data bits is to be updated */ cp210x_set_termios()
700 cp210x_get_config(port, CP210X_GET_LINE_CTL, &bits, 2); cp210x_set_termios()
701 bits &= ~BITS_DATA_MASK; cp210x_set_termios()
704 bits |= BITS_DATA_5; cp210x_set_termios()
705 dev_dbg(dev, "%s - data bits = 5\n", __func__); cp210x_set_termios()
708 bits |= BITS_DATA_6; cp210x_set_termios()
709 dev_dbg(dev, "%s - data bits = 6\n", __func__); cp210x_set_termios()
712 bits |= BITS_DATA_7; cp210x_set_termios()
713 dev_dbg(dev, "%s - data bits = 7\n", __func__); cp210x_set_termios()
716 bits |= BITS_DATA_8; cp210x_set_termios()
717 dev_dbg(dev, "%s - data bits = 8\n", __func__); cp210x_set_termios()
720 bits |= BITS_DATA_9; cp210x_set_termios()
721 dev_dbg(dev, "%s - data bits = 9\n", __func__); cp210x_set_termios()
724 dev_dbg(dev, "cp210x driver does not support the number of bits requested, using 8 bit mode\n"); cp210x_set_termios()
725 bits |= BITS_DATA_8; cp210x_set_termios()
728 if (cp210x_set_config(port, CP210X_SET_LINE_CTL, &bits, 2)) cp210x_set_termios()
729 dev_dbg(dev, "Number of data bits requested not supported by device\n"); cp210x_set_termios()
734 cp210x_get_config(port, CP210X_GET_LINE_CTL, &bits, 2); cp210x_set_termios()
735 bits &= ~BITS_PARITY_MASK; cp210x_set_termios()
739 bits |= BITS_PARITY_MARK; cp210x_set_termios()
742 bits |= BITS_PARITY_SPACE; cp210x_set_termios()
747 bits |= BITS_PARITY_ODD; cp210x_set_termios()
750 bits |= BITS_PARITY_EVEN; cp210x_set_termios()
755 if (cp210x_set_config(port, CP210X_SET_LINE_CTL, &bits, 2)) cp210x_set_termios()
760 cp210x_get_config(port, CP210X_GET_LINE_CTL, &bits, 2); cp210x_set_termios()
761 bits &= ~BITS_STOP_MASK; cp210x_set_termios()
763 bits |= BITS_STOP_2; cp210x_set_termios()
764 dev_dbg(dev, "%s - stop bits = 2\n", __func__); cp210x_set_termios()
766 bits |= BITS_STOP_1; cp210x_set_termios()
767 dev_dbg(dev, "%s - stop bits = 1\n", __func__); cp210x_set_termios()
769 if (cp210x_set_config(port, CP210X_SET_LINE_CTL, &bits, 2)) cp210x_set_termios()
770 dev_dbg(dev, "Number of stop bits requested not supported by device\n"); cp210x_set_termios()
/linux-4.1.27/include/linux/platform_data/
H A Dkeypad-omap.h33 * keypresses. Two free bits, not used by neither row/col nor keynum,
34 * must be available for use as group bits. The below GROUP_SHIFT
45 #error Group bits in conflict with keynum bits
/linux-4.1.27/arch/s390/include/asm/
H A Dsignal.h18 typedef unsigned long old_sigset_t; /* at least 32 bits */
/linux-4.1.27/arch/s390/lib/
H A Dfind.c4 * On s390x the bits are numbered:
9 * The reason for this bit numbering is the fact that the hardware sets bits
33 if (!tmp) /* Are any bits set? */ find_first_bit_inv()
72 if (!tmp) /* Are any bits set? */ find_next_bit_inv()
/linux-4.1.27/arch/mips/kernel/
H A Dearly_printk_8250.c49 int status, bits; prom_putchar() local
55 bits = UART_LSR_TEMT | UART_LSR_THRE; prom_putchar()
62 } while ((status & bits) != bits); prom_putchar()
/linux-4.1.27/arch/powerpc/mm/
H A Dvphn.c44 /* Let's concatenate the 16 bits of this field to the vphn_unpack_associativity()
45 * 15 lower bits of the previous field vphn_unpack_associativity()
54 /* Data is in the lower 15 bits of this field */ vphn_unpack_associativity()
58 /* Data is in the lower 15 bits of this field vphn_unpack_associativity()
/linux-4.1.27/arch/arm64/include/uapi/asm/
H A Dptrace.h28 * PSR bits
39 /* AArch32 CPSR bits */
42 /* AArch64 SPSR bits */
54 * Groups of PSR bits
/linux-4.1.27/arch/avr32/mach-at32ap/
H A Dhmatrix.c57 * hmatrix_sfr_set_bits - set bits in a slave's Special Function Register
59 * @mask: mask of bits to be set in the SFR
74 * hmatrix_sfr_set_bits - clear bits in a slave's Special Function Register
76 * @mask: mask of bits to be cleared in the SFR
/linux-4.1.27/arch/cris/include/asm/
H A Dsignal.h13 typedef unsigned long old_sigset_t; /* at least 32 bits */
/linux-4.1.27/arch/ia64/include/asm/
H A Dfpswa.h13 /* 4 * 128 bits */
18 /* 10 * 128 bits */
23 /* 16 * 128 bits */
28 /* 96 * 128 bits */
/linux-4.1.27/arch/arm/mach-davinci/include/mach/
H A Dcputype.h22 u8 variant; /* JTAG ID bits 31:28 */
23 u16 part_no; /* JTAG ID bits 27:12 */
24 u16 manufacturer; /* JTAG ID bits 11:1 */
29 /* Can use lower 16 bits of cpu id for a variant when required */
/linux-4.1.27/sound/hda/
H A Dlocal.h11 /* get the widget type from widget capability bits */ get_wcaps_type()
/linux-4.1.27/tools/perf/util/include/linux/
H A Dbitmap.h7 #define DECLARE_BITMAP(name,bits) \
8 unsigned long name[BITS_TO_LONGS(bits)]
10 int __bitmap_weight(const unsigned long *bitmap, int bits);
12 const unsigned long *bitmap2, int bits);
/linux-4.1.27/tools/testing/selftests/powerpc/vphn/
H A Dvphn.c44 /* Let's concatenate the 16 bits of this field to the vphn_unpack_associativity()
45 * 15 lower bits of the previous field vphn_unpack_associativity()
54 /* Data is in the lower 15 bits of this field */ vphn_unpack_associativity()
58 /* Data is in the lower 15 bits of this field vphn_unpack_associativity()
/linux-4.1.27/drivers/media/radio/
H A Dradio-aztech.c65 /* bits 0 and 2 are volume control, bits 3..5 are not connected */
71 u8 bits = az->curvol; aztech_set_pins() local
74 bits |= AZTECH_BIT_TUN_DATA; aztech_set_pins()
76 bits |= AZTECH_BIT_TUN_CLK; aztech_set_pins()
78 bits |= AZTECH_BIT_TUN_CE; aztech_set_pins()
80 outb_p(bits, az->isa.io); aztech_set_pins()
H A Dradio-maxiradio.c86 u8 bits = 0; maxiradio_tea575x_set_pins() local
88 bits |= (pins & TEA575X_DATA) ? data : 0; maxiradio_tea575x_set_pins()
89 bits |= (pins & TEA575X_CLK) ? clk : 0; maxiradio_tea575x_set_pins()
90 bits |= (pins & TEA575X_WREN) ? wren : 0; maxiradio_tea575x_set_pins()
91 bits |= power; maxiradio_tea575x_set_pins()
93 outb(bits, dev->io); maxiradio_tea575x_set_pins()
101 u8 bits = inb(dev->io); maxiradio_tea575x_get_pins() local
103 return ((bits & data) ? TEA575X_DATA : 0) | maxiradio_tea575x_get_pins()
104 ((bits & mo_st) ? TEA575X_MOST : 0); maxiradio_tea575x_get_pins()
/linux-4.1.27/drivers/staging/iio/accel/
H A Dadis16201_core.c39 int bits; adis16201_read_raw() local
80 bits = 12; adis16201_read_raw()
83 bits = 9; adis16201_read_raw()
95 val16 &= (1 << bits) - 1; adis16201_read_raw()
96 val16 = (s16)(val16 << (16 - bits)) >> (16 - bits); adis16201_read_raw()
111 int bits; adis16201_write_raw() local
119 bits = 12; adis16201_write_raw()
122 bits = 9; adis16201_write_raw()
127 val16 = val & ((1 << bits) - 1); adis16201_write_raw()
H A Dadis16204_core.c43 int bits; adis16204_read_raw() local
90 bits = 12; adis16204_read_raw()
93 bits = 14; adis16204_read_raw()
103 val16 &= (1 << bits) - 1; adis16204_read_raw()
104 val16 = (s16)(val16 << (16 - bits)) >> (16 - bits); adis16204_read_raw()
119 int bits; adis16204_write_raw() local
127 bits = 12; adis16204_write_raw()
132 val16 = val & ((1 << bits) - 1); adis16204_write_raw()
/linux-4.1.27/drivers/infiniband/hw/qib/
H A Dqib_wc_x86_64.c57 unsigned bits; qib_enable_wc() local
69 * register has both offsets, 2K in low 32 bits, 4K in high 32 bits. qib_enable_wc()
94 for (bits = 0; !(piolen & (1ULL << bits)); bits++) qib_enable_wc()
97 if (piolen != (1ULL << bits)) { qib_enable_wc()
98 piolen >>= bits; qib_enable_wc() local
100 bits++; qib_enable_wc()
101 piolen = 1ULL << (bits + 1); qib_enable_wc()
/linux-4.1.27/fs/ntfs/
H A Dbitmap.h36 * ntfs_bitmap_set_bits_in_run - set a run of bits in a bitmap to a value
39 * @count: number of bits to set
40 * @value: value to set the bits to (i.e. 0 or 1)
42 * Set @count bits starting at bit @start_bit in the bitmap described by the
55 * ntfs_bitmap_set_run - set a run of bits in a bitmap
58 * @count: number of bits to set
60 * Set @count bits starting at bit @start_bit in the bitmap described by the
72 * ntfs_bitmap_clear_run - clear a run of bits in a bitmap
75 * @count: number of bits to clear
77 * Clear @count bits starting at bit @start_bit in the bitmap described by the
/linux-4.1.27/arch/powerpc/platforms/83xx/
H A Dkm83xx.c77 * write 0b01 to UCC1 bits 18:19 quirk_mpc8360e_qe_enet10()
78 * write 0b01 to UCC2 option 1 bits 4:5 quirk_mpc8360e_qe_enet10()
79 * write 0b01 to UCC2 option 2 bits 16:17 quirk_mpc8360e_qe_enet10()
87 * write 0b01 to UCC2 option 2 bits 16:17 quirk_mpc8360e_qe_enet10()
88 * write 0b0101 to UCC1 bits 20:23 quirk_mpc8360e_qe_enet10()
89 * write 0b0101 to UCC2 option 1 bits 24:27 quirk_mpc8360e_qe_enet10()
95 * UCC2 option 1: write 0b1010 to bits 24:27 quirk_mpc8360e_qe_enet10()
101 * UCC1: write 0b11 to bits 18:19 quirk_mpc8360e_qe_enet10()
107 * UCC2 option 1: write 0b11 to bits 4:5 quirk_mpc8360e_qe_enet10()
113 * UCC2 option 2: write 0b11 to bits 16:17 quirk_mpc8360e_qe_enet10()
/linux-4.1.27/drivers/staging/lustre/lustre/ldlm/
H A Dldlm_inodebits.c46 * object. The meanings of specific bits are specific to the caller and are
66 lpolicy->l_inodebits.bits = wpolicy->l_inodebits.bits; ldlm_ibits_policy_wire_to_local()
73 wpolicy->l_inodebits.bits = lpolicy->l_inodebits.bits; ldlm_ibits_policy_local_to_wire()
/linux-4.1.27/drivers/staging/rtl8188eu/include/
H A Dpwrseqcmd.h25 /* The value of cmd: 4 bits */
32 /* The value of base: 4 bits */
39 /* The value of interface_msk: 4 bits */
45 /* The value of fab_msk: 4 bits */
50 /* The value of cut_msk: 8 bits */
/linux-4.1.27/arch/sh/mm/
H A Dtlb-sh4.c39 * EPR bits need to be written out to PTEA, with the remainder of __update_tlb()
40 * the protection bits (with the exception of the compat-mode SZ __update_tlb()
41 * and PR bits, which are cleared) being written out in PTEL. __update_tlb()
46 /* The last 3 bits and the first one of pteval contains __update_tlb()
47 * the PTEA timing control and space attribute bits __update_tlb()
/linux-4.1.27/arch/tile/mm/
H A Dmmap.c64 * 8 bits of randomness in 32bit mmaps, 24 address space bits arch_pick_mmap_layout()
65 * 12 bits of randomness in 64bit mmaps, 28 address space bits arch_pick_mmap_layout()
78 * or we are running native 64 bits. arch_pick_mmap_layout()
/linux-4.1.27/arch/ia64/lib/
H A Dchecksum.c21 /* add up 32-bit words for 33 bits */ from64to16()
23 /* add up 16-bit and 17-bit words for 17+c bits */ from64to16()
56 /* Fold down to 32-bits so we don't lose in the typedef-less network stack. */ csum_tcpudp_nofold()
85 /* 32+c bits -> 32 bits */ csum_partial()
/linux-4.1.27/net/netfilter/
H A Dnf_conntrack_labels.c2 * test/set flag bits stored in conntrack extension area.
30 return bit < label_bits(labels) && test_bit(bit, labels->bits); nf_connlabel_match()
41 if (test_bit(bit, labels->bits)) nf_connlabel_set()
44 if (!test_and_set_bit(bit, labels->bits)) nf_connlabel_set()
78 dst = (u32 *) labels->bits; nf_connlabels_replace()
/linux-4.1.27/drivers/xen/
H A Dacpi.c42 unsigned int bits = extended ? 8 : 16; xen_acpi_notify_hypervisor_state() local
55 if (WARN((val_a & (~0 << bits)) || (val_b & (~0 << bits)), xen_acpi_notify_hypervisor_state()
56 "Using more than %u bits of sleep control values %#x/%#x!" xen_acpi_notify_hypervisor_state()
58 bits, val_a, val_b)) xen_acpi_notify_hypervisor_state()
/linux-4.1.27/drivers/parport/
H A Dparport_sunbpp.c88 unsigned char bits = 0; status_sunbpp_to_pc() local
93 bits |= PARPORT_STATUS_ERROR; status_sunbpp_to_pc()
95 bits |= PARPORT_STATUS_SELECT; status_sunbpp_to_pc()
97 bits |= PARPORT_STATUS_PAPEROUT; status_sunbpp_to_pc()
99 bits |= PARPORT_STATUS_ACK; status_sunbpp_to_pc()
101 bits |= PARPORT_STATUS_BUSY; status_sunbpp_to_pc()
104 dprintk((KERN_DEBUG "read status 0x%x\n", bits)); status_sunbpp_to_pc()
105 return bits; status_sunbpp_to_pc()
111 unsigned char bits = 0; control_sunbpp_to_pc() local
116 bits |= PARPORT_CONTROL_STROBE; control_sunbpp_to_pc()
118 bits |= PARPORT_CONTROL_AUTOFD; control_sunbpp_to_pc()
120 bits |= PARPORT_CONTROL_INIT; control_sunbpp_to_pc()
122 bits |= PARPORT_CONTROL_SELECT; control_sunbpp_to_pc()
125 dprintk((KERN_DEBUG "read control 0x%x\n", bits)); control_sunbpp_to_pc()
126 return bits; control_sunbpp_to_pc()
/linux-4.1.27/arch/arm64/mm/
H A Ddump.c144 const struct prot_bits *bits; member in struct:pg_level
152 .bits = pte_bits,
155 .bits = pte_bits,
158 .bits = pte_bits,
161 .bits = pte_bits,
166 static void dump_prot(struct pg_state *st, const struct prot_bits *bits, dump_prot() argument
171 for (i = 0; i < num; i++, bits++) { dump_prot()
174 if ((st->current_prot & bits->mask) == bits->val) dump_prot()
175 s = bits->set; dump_prot()
177 s = bits->clear; dump_prot()
210 if (pg_level[st->level].bits) note_page()
211 dump_prot(st, pg_level[st->level].bits, note_page()
327 if (pg_level[i].bits) ptdump_init()
329 pg_level[i].mask |= pg_level[i].bits[j].mask; ptdump_init()
/linux-4.1.27/drivers/input/touchscreen/
H A Dsun4i-ts.c62 /* TP_CTRL0 bits */
63 #define ADC_FIRST_DLY(x) ((x) << 24) /* 8 bits */
66 #define ADC_CLK_DIV(x) ((x) << 20) /* 3 bits */
67 #define FS_DIV(x) ((x) << 16) /* 4 bits */
68 #define T_ACQ(x) ((x) << 0) /* 16 bits */
70 /* TP_CTRL1 bits */
71 #define STYLUS_UP_DEBOUN(x) ((x) << 12) /* 8 bits */
77 #define ADC_CHAN_SELECT(x) ((x) << 0) /* 3 bits */
79 /* on sun6i, bits 3~6 are left shifted by 1 to 4~7 */
82 /* TP_CTRL2 bits */
83 #define TP_SENSITIVE_ADJUST(x) ((x) << 28) /* 4 bits */
84 #define TP_MODE_SELECT(x) ((x) << 26) /* 2 bits */
86 #define PRE_MEA_THRE_CNT(x) ((x) << 0) /* 24 bits */
88 /* TP_CTRL3 bits */
90 #define FILTER_TYPE(x) ((x) << 0) /* 2 bits */
92 /* TP_INT_FIFOC irq and fifo mask / control bits */
97 #define FIFO_TRIG(x) ((x) << 8) /* 5 bits */
103 /* TP_INT_FIFOS irq and fifo status bits */
111 /* TP_TPR bits */
/linux-4.1.27/drivers/net/ethernet/ti/
H A Dcpsw_ale.c28 #define BITMASK(bits) (BIT(bits) - 1)
54 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) cpsw_ale_get_field() argument
61 return (ale_entry[idx] >> start) & BITMASK(bits); cpsw_ale_get_field()
64 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, cpsw_ale_set_field() argument
69 value &= BITMASK(bits); cpsw_ale_set_field()
73 ale_entry[idx] &= ~(BITMASK(bits) << start); cpsw_ale_set_field()
77 #define DEFINE_ALE_FIELD(name, start, bits) \
80 return cpsw_ale_get_field(ale_entry, start, bits); \
84 cpsw_ale_set_field(ale_entry, start, bits, value); \
497 int bits; member in struct:ale_control_info
507 .bits = 1,
515 .bits = 1,
523 .bits = 1,
531 .bits = 1,
539 .bits = 1,
547 .bits = 1,
555 .bits = 1,
563 .bits = 1,
571 .bits = 1,
579 .bits = 1,
587 .bits = 1,
595 .bits = 1,
603 .bits = 2,
611 .bits = 1,
619 .bits = 1,
627 .bits = 1,
635 .bits = 1,
643 .bits = 8,
651 .bits = 8,
659 .bits = 6,
667 .bits = 6,
675 .bits = 6,
683 .bits = 6,
704 mask = BITMASK(info->bits); cpsw_ale_control_set()
739 return tmp & BITMASK(info->bits); cpsw_ale_control_get()
/linux-4.1.27/drivers/thermal/ti-soc-thermal/
H A Domap4xxx-bandgap.h49 * All the macros bellow define the required bits for
54 /* OMAP4430.TEMP_SENSOR bits */
119 * All the macros bellow define the required bits for
123 /* OMAP4460.TEMP_SENSOR bits */
129 /* OMAP4460.BANDGAP_CTRL bits */
134 /* OMAP4460.BANDGAP_COUNTER bits */
137 /* OMAP4460.BANDGAP_THRESHOLD bits */
141 /* OMAP4460.TSHUT_THRESHOLD bits */
145 /* OMAP4460.BANDGAP_STATUS bits */
/linux-4.1.27/drivers/tty/serial/
H A Dm32r_sio_reg.h108 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
109 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
116 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
117 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
118 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
119 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
120 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
/linux-4.1.27/arch/x86/vdso/
H A Dvdso2c.c123 #define GLE(x, bits, ifnot) \
125 (sizeof(*(x)) == bits/8), \
126 (__typeof__(*(x)))get_unaligned_le##bits(x), ifnot)
135 #define PLE(x, val, bits, ifnot) \
137 (sizeof(*(x)) == bits/8), \
138 put_unaligned_le##bits((val), (x)), ifnot)
150 #define BITSFUNC3(name, bits, suffix) name##bits##suffix
151 #define BITSFUNC2(name, bits, suffix) BITSFUNC3(name, bits, suffix)
156 #define ELF_BITS_XFORM2(bits, x) Elf##bits##_##x
157 #define ELF_BITS_XFORM(bits, x) ELF_BITS_XFORM2(bits, x)
/linux-4.1.27/include/math-emu/
H A Dop-1.h71 * Unpack the raw bits of a native fp value. Do not classify or
79 X##_f = _flo.bits.frac; \
80 X##_e = _flo.bits.exp; \
81 X##_s = _flo.bits.sign; \
89 X##_f = _flo->bits.frac; \
90 X##_e = _flo->bits.exp; \
91 X##_s = _flo->bits.sign; \
95 * Repack the raw bits of a native fp value.
102 _flo.bits.frac = X##_f; \
103 _flo.bits.exp = X##_e; \
104 _flo.bits.sign = X##_s; \
114 _flo->bits.frac = X##_f; \
115 _flo->bits.exp = X##_e; \
116 _flo->bits.sign = X##_s; \

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