Home
last modified time | relevance | path

Searched refs:TxINT_ENAB (Results 1 – 13 of 13) sorted by relevance

/linux-4.1.27/drivers/net/wan/
Dz85230.c230 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
255 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
808 c->regs[R1]|=TxINT_ENAB; in z8530_sync_open()
914 c->regs[R1]&= ~TxINT_ENAB; in z8530_sync_dma_open()
924 c->regs[R1]&= ~TxINT_ENAB; in z8530_sync_dma_open()
1110 c->regs[R1]&= ~TxINT_ENAB; in z8530_sync_txdma_open()
Dz85230.h60 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
/linux-4.1.27/drivers/net/hamradio/
Dz8530.h39 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
Dscc.c876 or(scc,R1,INT_ALL_Rx|TxINT_ENAB|EXT_INT_ENAB); /* enable interrupts */ in init_channel()
914 or(scc, R1, TxINT_ENAB); /* t_maxkeyup may have reset these */ in scc_key_trx()
1249 cl(scc, R1, TxINT_ENAB); /* force an ABORT, but don't */ in t_maxkeyup()
Ddmascc.c1009 EXT_INT_ENAB | WT_FN_RDYFN | TxINT_ENAB); in tx_on()
/linux-4.1.27/drivers/tty/serial/
Dzs.c462 zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB); in zs_stop_rx()
789 zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB; in zs_startup()
1161 if (txint & TxINT_ENAB) { in zs_console_write()
1162 zport->regs[1] = txint & ~TxINT_ENAB; in zs_console_write()
1181 if (txint & TxINT_ENAB) { in zs_console_write()
1182 zport->regs[1] |= TxINT_ENAB; in zs_console_write()
Dzs.h91 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
Dip22zilog.h71 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
Dsunzilog.h63 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
Dip22zilog.c181 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); in __load_zsregs()
731 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in __ip22zilog_startup()
792 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); in ip22zilog_shutdown()
1140 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in ip22zilog_prepare()
Dsunzilog.c200 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); in __load_zsregs()
796 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in __sunzilog_startup()
857 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); in sunzilog_shutdown()
1350 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in sunzilog_init_hw()
1366 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in sunzilog_init_hw()
Dpmac_zilog.h160 #define TxINT_ENAB 0x2 /* Tx Int Enable */ macro
Dpmac_zilog.c149 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); in pmz_load_zsregs()
223 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB; in pmz_interrupt_control()
227 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); in pmz_interrupt_control()
1979 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); in pmz_console_write()