Searched refs:SCLK (Results 1 – 13 of 13) sorted by relevance
| /linux-4.1.27/drivers/spi/ |
| D | spi-lm70llp.c | 75 #define SCLK 0x40 macro
125 parport_write_data(pp->port, data | SCLK); in clkHigh()
131 parport_write_data(pp->port, data & ~SCLK); in clkLow()
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| /linux-4.1.27/Documentation/devicetree/bindings/sound/ |
| D | pcm512x.txt | 19 - clocks : A clock specifier for the clock connected as SCLK. If this
27 external connection from the pll-out pin to the SCLK pin is assumed.
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| /linux-4.1.27/Documentation/devicetree/bindings/spi/ |
| D | spi_oc_tiny.txt | 9 the input clock to SCLK.
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| D | spi-rockchip.txt | 27 - rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling
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| /linux-4.1.27/Documentation/hwmon/ |
| D | lm70 | 28 the driver accesses the LM70 using SPI communication: 16 SCLK cycles
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| /linux-4.1.27/Documentation/spi/ |
| D | spi-lm70llp | 41 D6 8 --> SCLK 3
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| D | spi-summary | 182 physical SPI bus segment, with SCLK, MOSI, and MISO.
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| /linux-4.1.27/Documentation/input/ |
| D | amijoy.txt | 68 the rising edge of SCLK. MLD output is used to parallel load
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| /linux-4.1.27/drivers/scsi/sym53c8xx_2/ |
| D | sym_defs.h | 281 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ macro
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| D | sym_hipd.c | 459 OUTB(np, nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */
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| /linux-4.1.27/arch/blackfin/ |
| D | Kconfig | 568 bool "Provide accurate Timings based on target SCLK"
1265 The PLL and system clock (SCLK) continue to operate at a very low
1270 normal during Sleep Deeper, due to the reduced SCLK frequency.
1280 The PLL and system clock (SCLK), however, continue to operate in
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| /linux-4.1.27/drivers/scsi/ |
| D | ncr53c8xx.h | 803 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ macro
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| /linux-4.1.27/Documentation/watchdog/ |
| D | watchdog-parameters.txt | 64 timeout: Watchdog timeout in seconds. (1<=timeout<=((2^32)/SCLK), default=20)
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