Searched refs:LPC (Results 1 - 62 of 62) sorted by relevance

/linux-4.1.27/include/linux/
H A Ddtlk.h20 (that is, all but LPC) */
42 /* LPC speak commands */
48 /* LPC Port Status Flags (valid only after one of the LPC
51 indicates the LPC synthesizer is
54 indicates that the hardware LPC
59 indicates that the LPC data buffer
/linux-4.1.27/drivers/mfd/
H A Dlpc_sch.c2 * lpc_sch.c - LPC interface for Intel Poulsbo SCH
4 * LPC bridge function of the Intel SCH contains many other
6 * Power Management, System Management, GPIO, RTC, and LPC
215 MODULE_DESCRIPTION("LPC interface for Intel Poulsbo SCH");
H A Dlpc_ich.c2 * lpc_ich.c - LPC interface for Intel ICH
4 * LPC bridge function of the Intel ICH contains many other
6 * Power Management, System Management, GPIO, RTC, and LPC
857 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3")) lpc_ich_check_conflict_gpio()
860 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2")) lpc_ich_check_conflict_gpio()
863 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1"); lpc_ich_check_conflict_gpio()
1090 MODULE_DESCRIPTION("LPC interface for Intel ICH");
/linux-4.1.27/arch/x86/kernel/
H A Di8237.c19 * 8237A DMA controller (used for ISA and LPC).
H A Dquirks.c457 /* LPC bridges */
522 * Corrupted LPC DMA Data) in AMD Publication #46837,
H A Dpmc_atom.c135 * - LPC clock run pmc_hw_reg_setup()
/linux-4.1.27/arch/mips/loongson/common/
H A Duart_base.c43 /* The CPU provided serial port (LPC) */ prom_init_loongson_uart_base()
/linux-4.1.27/drivers/char/
H A Ddtlk.c20 (TTS), linear predictive coding (LPC), PCM/ADPCM, and CVSD. It
21 also has a tone generator. Output data for LPC are written to the
22 LPC port, and output data for the other modes are written to the
28 of the speech) are read from the LPC port. Not all models of the
29 DoubleTalk PC implement index markers. Both the TTS and LPC ports
40 synthesizer. If LPC output is needed some day, other minor device
43 "read" gets index markers from the LPC port. If the device does
420 /* put LPC port into known state, so dtlk_dev_probe()
436 /* This macro records ten samples read from the LPC port, for later display */ dtlk_dev_probe()
604 ch = inb_p(dtlk_port_lpc); /* input from LPC port */ dtlk_read_lpc()
H A Dsonypi.c610 /* Initialization of PCI config space of the LPC interface bridge. */ sonypi_type3_srs()
/linux-4.1.27/arch/sh/include/cpu-sh4/cpu/
H A Dsh7757.h144 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
149 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
196 /* PTQ (mobule: LPC) */
216 /* PTU (mobule: LPC, APM) */
/linux-4.1.27/drivers/gpu/drm/gma500/
H A Doaktrail_lvds_i2c.c42 * LPC GPIO based I2C bus for LVDS of Atom E6xx
46 * LPC Register Offsets. Used for LVDS GPIO Bit Bashing. Registers are part
146 strncpy(chan->adapter.name, "gma500 LPC", I2C_NAME_SIZE - 1); oaktrail_lvds_i2c_init()
H A Dpsb_drv.c296 DRM_DEBUG_KMS("Found LPC GPIO at 0x%04x\n", psb_driver_load()
/linux-4.1.27/arch/powerpc/include/asm/
H A Dmpc5121.h49 * LPC Module
H A Dopal-api.h336 * Address cycle types for LPC accesses. These also correspond
338 * device nodes on the LPC bus
/linux-4.1.27/arch/powerpc/platforms/powernv/
H A Dopal-lpc.c2 * PowerNV LPC bus handling.
229 * respective positions (ie, LPC position). lpc_debug_read()
234 * IE. If the LPC transaction has bytes B0, B1, B2 and B3 in that lpc_debug_read()
394 * Look for a Power8 LPC bus tagged as "primary", opal_lpc_init()
413 pr_info("OPAL: Power8 LPC bus found, chip ID %d\n", opal_lpc_chip_id); opal_lpc_init()
H A Dopal-xscom.c2 * PowerNV LPC bus handling.
H A Dsetup.c68 * Initialize the LPC bus now so that legacy serial pnv_init_early()
/linux-4.1.27/drivers/staging/speakup/
H A Dspeakup_dtlk.h12 (that is, all but LPC) */
/linux-4.1.27/arch/mips/loongson/loongson-3/
H A Dirq.c105 /* route LPC int to cpu core0 int 0 */ irq_router_init()
/linux-4.1.27/arch/arm/include/asm/hardware/
H A Dit8152.h84 /* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
/linux-4.1.27/drivers/leds/
H A Dleds-ss4200.c39 * ICH7 LPC/GPIO PCI Config register offsets
64 * PCI ID of the Intel ICH7 LPC Device within which the GPIO block lives.
340 * The OS has determined that the LPC of the Intel ICH7 Southbridge is present
366 "ERROR: The LPC GPIO Block has not been enabled.\n"); ich7_lpc_probe()
/linux-4.1.27/drivers/mtd/chips/
H A Dfwh_lock.h24 * hub parts cannot be interleaved as they are on the LPC bus
/linux-4.1.27/drivers/net/irda/
H A Dsmsc-ircc2.c2161 type = "LPC"; smsc_ircc_look_for_chips()
2377 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") || smsc_superio_lpc()
2378 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC")) smsc_superio_lpc()
2391 * for ISA bridges with an LPC (Low Pin Count) controller which
2392 * handles the communication with the SMSC device. After the LPC
2410 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2423 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2437 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2450 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2464 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2475 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2491 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2502 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2617 /* LPC-specific registers */
2623 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2624 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2710 tmpword &= 0xfffd; /* disable LPC COMB */ preconfigure_through_82801()
2711 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */ preconfigure_through_82801()
2716 * Configure LPC DMA channel preconfigure_through_82801()
2729 * 11 = LPC I/F DMA preconfigure_through_82801()
2764 * Bit 0: enable GEN2 range on LPC I/F preconfigure_through_82801()
/linux-4.1.27/drivers/media/rc/
H A Dfintek-cir.h2 * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
31 #define FINTEK_DESCRIPTION "Fintek LPC SuperIO Consumer IR Transceiver"
H A Dfintek-cir.c2 * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
H A Dite-cir.h215 * (EC - LPC I/O)
/linux-4.1.27/drivers/platform/chrome/
H A Dcros_ec_lpc.c2 * cros_ec_lpc - LPC access to the Chrome OS Embedded Controller
319 MODULE_DESCRIPTION("ChromeOS EC LPC driver");
/linux-4.1.27/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7757.c808 LPC, LPC5, LPC6, LPC7, LPC8, enumerator in enum:__anon2659
873 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
874 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
875 INTC_VECT(LPC, 0xb20),
971 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
1071 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
/linux-4.1.27/include/linux/mfd/
H A Dcros_ec.h25 * Command interface between EC and AP, for LPC, I2C and SPI interfaces.
147 * only SPI uses it. Once LPC uses the same protocol it can start using it.
H A Dcros_ec_commands.h173 /* Host command interface supports LPC args (LPC interface only) */
200 /* LPC command status byte masks */
293 * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is
444 /* Parameter length was limited by the LPC interface */
2308 * This command will work even when the EC LPC interface is busy, because the
2317 * Resend last response (not supported on LPC).
/linux-4.1.27/drivers/hwmon/
H A Dit87.c5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
13 * Supports: IT8603E Super I/O chip w/LPC interface
14 * IT8620E Super I/O chip w/LPC interface
15 * IT8623E Super I/O chip w/LPC interface
16 * IT8705F Super I/O chip w/LPC interface
17 * IT8712F Super I/O chip w/LPC interface
18 * IT8716F Super I/O chip w/LPC interface
19 * IT8718F Super I/O chip w/LPC interface
20 * IT8720F Super I/O chip w/LPC interface
21 * IT8721F Super I/O chip w/LPC interface
22 * IT8726F Super I/O chip w/LPC interface
23 * IT8728F Super I/O chip w/LPC interface
24 * IT8758E Super I/O chip w/LPC interface
25 * IT8771E Super I/O chip w/LPC interface
26 * IT8772E Super I/O chip w/LPC interface
27 * IT8781F Super I/O chip w/LPC interface
28 * IT8782F Super I/O chip w/LPC interface
29 * IT8783E/F Super I/O chip w/LPC interface
30 * IT8786E Super I/O chip w/LPC interface
31 * IT8790E Super I/O chip w/LPC interface
H A Dw83627hf.c29 * w83627hf 9 3 2 3 0x20 0x5ca3 no yes(LPC)
30 * w83627thf 7 3 3 3 0x90 0x5ca3 no yes(LPC)
31 * w83637hf 7 3 3 3 0x80 0x5ca3 no yes(LPC)
32 * w83687thf 7 3 3 3 0x90 0x5ca3 no yes(LPC)
33 * w83697hf 8 2 2 2 0x60 0x5ca3 no yes(LPC)
H A Ddme1737.c59 "Include probing of non-standard LPC addresses");
2291 * registers through the Super-IO LPC interface. Try both dme1737_init_device()
H A Df71805f.c6 * The F71805F/FG is a LPC Super-I/O chip made by Fintek. It integrates
/linux-4.1.27/drivers/edac/
H A Damd8111_edac.c245 /* device-specific methods for amd8111 LPC Bridge device */ amd8111_lpc_bridge_init()
277 /* Second clear error flags on LPC bridge */ amd8111_lpc_bridge_init()
300 printk(KERN_INFO "LPC ERR: %d, PW2LPC: %d\n", amd8111_lpc_bridge_check()
/linux-4.1.27/drivers/tty/serial/8250/
H A D8250_fintek.c2 * Probe for F81216A LPC to 4 UART
/linux-4.1.27/drivers/watchdog/
H A Dit8712f_wdt.c10 * IT8712F EC-LPC I/O Preliminary Specification 0.8.2
11 * IT8712F EC-LPC I/O Preliminary Specification 0.9.3
H A Dit87_wdt.c796 MODULE_DESCRIPTION("Hardware Watchdog Device Driver for IT87xx EC-LPC I/O");
/linux-4.1.27/drivers/pinctrl/sh-pfc/
H A Dpfc-sh7757.c382 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
387 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
430 /* PTQ (mobule: LPC) */
450 /* PTU (mobule: LPC, APM) */
1416 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
1428 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
1538 /* PTQ (mobule: LPC) */
1587 /* PTU (mobule: LPC, APM) */
/linux-4.1.27/drivers/mtd/nand/
H A Dlpc32xx_mlc.c253 /* Compute clock setup values, see LPC and NAND manual */ lpc32xx_nand_setup()
533 /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */ lpc32xx_write_page_lowlevel()
556 /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */ lpc32xx_write_oob()
/linux-4.1.27/drivers/gpio/
H A Dgpio-cs5535.c27 * 22-16 : LPC
/linux-4.1.27/drivers/cpufreq/
H A Dspeedstep-ich.c178 * the LPC bridge / PM module which contains all power-management
/linux-4.1.27/drivers/char/tpm/
H A Dtpm_i2c_atmel.c14 * TGC status/locality/etc functions seen in the LPC implementation do not
/linux-4.1.27/drivers/video/backlight/
H A Dcr_bllcd.c185 pr_err("INTEL CARILLO RANCH LPC not found.\n"); cr_backlight_probe()
/linux-4.1.27/net/irda/
H A Dirda_device.c297 * Setup the DMA channel. Commonly used by LPC FIR drivers
/linux-4.1.27/drivers/pci/
H A Dquirks.c103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); quirk_tigerpoint_bm_sts()
641 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); quirk_ich6_lpc()
642 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); quirk_ich6_lpc()
670 /* ICH7-10 has the same common LPC generic IO decode registers */ quirk_ich7_lpc()
677 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); quirk_ich7_lpc()
678 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); quirk_ich7_lpc()
679 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); quirk_ich7_lpc()
680 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); quirk_ich7_lpc()
1175 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
3720 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3953 * Read the RCBA register from the LPC (D31:F0). PCH root ports pci_quirk_enable_intel_lpc_acs()
3954 * are D28:F* and therefore get probed before LPC, thus we can't pci_quirk_enable_intel_lpc_acs()
/linux-4.1.27/drivers/misc/
H A Dcs5535-mfgpt.c129 /* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */ cs5535_mfgpt_set_irq()
/linux-4.1.27/drivers/char/hw_random/
H A Dintel-rng.c56 * LPC bridge PCI config space registers
/linux-4.1.27/arch/sh/boards/
H A Dboard-sh7757lcr.c418 /* LPC (PTG, PTH, PTQ, PTU) */ sh7757lcr_devices_setup()
/linux-4.1.27/drivers/net/ethernet/nxp/
H A Dlpc_eth.c1223 /* Suspended PHY makes LPC ethernet core block, so resume now */ lpc_eth_open()
1474 netdev_info(ndev, "LPC mac at 0x%08x irq %d\n", lpc_eth_drv_probe()
1608 MODULE_DESCRIPTION("LPC Ethernet Driver");
/linux-4.1.27/drivers/net/wireless/
H A Dadm8211.h31 __le32 LPC; /* 0x40 CSR8 */ member in struct:adm8211_csr
H A Dadm8211.c452 /* TODO: check LPC and update stats? */ adm8211_interrupt_rci()
1204 ADM8211_CSR_READ(LPC); adm8211_hw_init()
/linux-4.1.27/arch/x86/pci/
H A Dfixup.c546 * Match off the LPC and svid/sdid (older kernels lose the bridge subvendor)
/linux-4.1.27/include/acpi/
H A Dactbl.h291 #define ACPI_FADT_LEGACY_DEVICES (1) /* 00: [V2] System has LPC or ISA bus devices */
/linux-4.1.27/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hw.c204 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
/linux-4.1.27/drivers/rtc/
H A Drtc-cmos.c19 * are also clones that connect using the LPC bus.
/linux-4.1.27/arch/x86/kernel/acpi/
H A Dboot.c1395 * for LPC bridge, which is needed for the PCI
/linux-4.1.27/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_hw.c237 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
/linux-4.1.27/drivers/net/ethernet/smsc/
H A Dsmc91c92_cs.c2030 PCMCIA_DEVICE_PROD_ID12("MELCO/SMC", "LPC-TX", 0xa2cd8e6d, 0x42da662a),
/linux-4.1.27/drivers/scsi/qla4xxx/
H A Dql4_nx.c265 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
/linux-4.1.27/net/ipv4/
H A Dfib_trie.c15 * This work is based on the LPC-trie which is originally described in:
/linux-4.1.27/drivers/iommu/
H A Dintel-iommu.c2431 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n"); iommu_prepare_isa()

Completed in 3511 milliseconds