1/*
2 *  lpc_ich.c - LPC interface for Intel ICH
3 *
4 *  LPC bridge function of the Intel ICH contains many other
5 *  functional units, such as Interrupt controllers, Timers,
6 *  Power Management, System Management, GPIO, RTC, and LPC
7 *  Configuration Registers.
8 *
9 *  This driver is derived from lpc_sch.
10
11 *  Copyright (c) 2011 Extreme Engineering Solution, Inc.
12 *  Author: Aaron Sierra <asierra@xes-inc.com>
13 *
14 *  This program is free software; you can redistribute it and/or modify
15 *  it under the terms of the GNU General Public License 2 as published
16 *  by the Free Software Foundation.
17 *
18 *  This program is distributed in the hope that it will be useful,
19 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
20 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21 *  GNU General Public License for more details.
22 *
23 *  You should have received a copy of the GNU General Public License
24 *  along with this program; see the file COPYING.  If not, write to
25 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 *  This driver supports the following I/O Controller hubs:
28 *	(See the intel documentation on http://developer.intel.com.)
29 *	document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
30 *	document number 290687-002, 298242-027: 82801BA (ICH2)
31 *	document number 290733-003, 290739-013: 82801CA (ICH3-S)
32 *	document number 290716-001, 290718-007: 82801CAM (ICH3-M)
33 *	document number 290744-001, 290745-025: 82801DB (ICH4)
34 *	document number 252337-001, 252663-008: 82801DBM (ICH4-M)
35 *	document number 273599-001, 273645-002: 82801E (C-ICH)
36 *	document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
37 *	document number 300641-004, 300884-013: 6300ESB
38 *	document number 301473-002, 301474-026: 82801F (ICH6)
39 *	document number 313082-001, 313075-006: 631xESB, 632xESB
40 *	document number 307013-003, 307014-024: 82801G (ICH7)
41 *	document number 322896-001, 322897-001: NM10
42 *	document number 313056-003, 313057-017: 82801H (ICH8)
43 *	document number 316972-004, 316973-012: 82801I (ICH9)
44 *	document number 319973-002, 319974-002: 82801J (ICH10)
45 *	document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
46 *	document number 320066-003, 320257-008: EP80597 (IICH)
47 *	document number 324645-001, 324646-001: Cougar Point (CPT)
48 *	document number TBD : Patsburg (PBG)
49 *	document number TBD : DH89xxCC
50 *	document number TBD : Panther Point
51 *	document number TBD : Lynx Point
52 *	document number TBD : Lynx Point-LP
53 *	document number TBD : Wellsburg
54 *	document number TBD : Avoton SoC
55 *	document number TBD : Coleto Creek
56 *	document number TBD : Wildcat Point-LP
57 *	document number TBD : 9 Series
58 */
59
60#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
61
62#include <linux/kernel.h>
63#include <linux/module.h>
64#include <linux/errno.h>
65#include <linux/acpi.h>
66#include <linux/pci.h>
67#include <linux/mfd/core.h>
68#include <linux/mfd/lpc_ich.h>
69
70#define ACPIBASE		0x40
71#define ACPIBASE_GPE_OFF	0x28
72#define ACPIBASE_GPE_END	0x2f
73#define ACPIBASE_SMI_OFF	0x30
74#define ACPIBASE_SMI_END	0x33
75#define ACPIBASE_PMC_OFF	0x08
76#define ACPIBASE_PMC_END	0x0c
77#define ACPIBASE_TCO_OFF	0x60
78#define ACPIBASE_TCO_END	0x7f
79#define ACPICTRL_PMCBASE	0x44
80
81#define ACPIBASE_GCS_OFF	0x3410
82#define ACPIBASE_GCS_END	0x3414
83
84#define GPIOBASE_ICH0		0x58
85#define GPIOCTRL_ICH0		0x5C
86#define GPIOBASE_ICH6		0x48
87#define GPIOCTRL_ICH6		0x4C
88
89#define RCBABASE		0xf0
90
91#define wdt_io_res(i) wdt_res(0, i)
92#define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
93#define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
94
95struct lpc_ich_priv {
96	int chipset;
97
98	int abase;		/* ACPI base */
99	int actrl_pbase;	/* ACPI control or PMC base */
100	int gbase;		/* GPIO base */
101	int gctrl;		/* GPIO control */
102
103	int abase_save;		/* Cached ACPI base value */
104	int actrl_pbase_save;		/* Cached ACPI control or PMC base value */
105	int gctrl_save;		/* Cached GPIO control value */
106};
107
108static struct resource wdt_ich_res[] = {
109	/* ACPI - TCO */
110	{
111		.flags = IORESOURCE_IO,
112	},
113	/* ACPI - SMI */
114	{
115		.flags = IORESOURCE_IO,
116	},
117	/* GCS or PMC */
118	{
119		.flags = IORESOURCE_MEM,
120	},
121};
122
123static struct resource gpio_ich_res[] = {
124	/* GPIO */
125	{
126		.flags = IORESOURCE_IO,
127	},
128	/* ACPI - GPE0 */
129	{
130		.flags = IORESOURCE_IO,
131	},
132};
133
134enum lpc_cells {
135	LPC_WDT = 0,
136	LPC_GPIO,
137};
138
139static struct mfd_cell lpc_ich_cells[] = {
140	[LPC_WDT] = {
141		.name = "iTCO_wdt",
142		.num_resources = ARRAY_SIZE(wdt_ich_res),
143		.resources = wdt_ich_res,
144		.ignore_resource_conflicts = true,
145	},
146	[LPC_GPIO] = {
147		.name = "gpio_ich",
148		.num_resources = ARRAY_SIZE(gpio_ich_res),
149		.resources = gpio_ich_res,
150		.ignore_resource_conflicts = true,
151	},
152};
153
154/* chipset related info */
155enum lpc_chipsets {
156	LPC_ICH = 0,	/* ICH */
157	LPC_ICH0,	/* ICH0 */
158	LPC_ICH2,	/* ICH2 */
159	LPC_ICH2M,	/* ICH2-M */
160	LPC_ICH3,	/* ICH3-S */
161	LPC_ICH3M,	/* ICH3-M */
162	LPC_ICH4,	/* ICH4 */
163	LPC_ICH4M,	/* ICH4-M */
164	LPC_CICH,	/* C-ICH */
165	LPC_ICH5,	/* ICH5 & ICH5R */
166	LPC_6300ESB,	/* 6300ESB */
167	LPC_ICH6,	/* ICH6 & ICH6R */
168	LPC_ICH6M,	/* ICH6-M */
169	LPC_ICH6W,	/* ICH6W & ICH6RW */
170	LPC_631XESB,	/* 631xESB/632xESB */
171	LPC_ICH7,	/* ICH7 & ICH7R */
172	LPC_ICH7DH,	/* ICH7DH */
173	LPC_ICH7M,	/* ICH7-M & ICH7-U */
174	LPC_ICH7MDH,	/* ICH7-M DH */
175	LPC_NM10,	/* NM10 */
176	LPC_ICH8,	/* ICH8 & ICH8R */
177	LPC_ICH8DH,	/* ICH8DH */
178	LPC_ICH8DO,	/* ICH8DO */
179	LPC_ICH8M,	/* ICH8M */
180	LPC_ICH8ME,	/* ICH8M-E */
181	LPC_ICH9,	/* ICH9 */
182	LPC_ICH9R,	/* ICH9R */
183	LPC_ICH9DH,	/* ICH9DH */
184	LPC_ICH9DO,	/* ICH9DO */
185	LPC_ICH9M,	/* ICH9M */
186	LPC_ICH9ME,	/* ICH9M-E */
187	LPC_ICH10,	/* ICH10 */
188	LPC_ICH10R,	/* ICH10R */
189	LPC_ICH10D,	/* ICH10D */
190	LPC_ICH10DO,	/* ICH10DO */
191	LPC_PCH,	/* PCH Desktop Full Featured */
192	LPC_PCHM,	/* PCH Mobile Full Featured */
193	LPC_P55,	/* P55 */
194	LPC_PM55,	/* PM55 */
195	LPC_H55,	/* H55 */
196	LPC_QM57,	/* QM57 */
197	LPC_H57,	/* H57 */
198	LPC_HM55,	/* HM55 */
199	LPC_Q57,	/* Q57 */
200	LPC_HM57,	/* HM57 */
201	LPC_PCHMSFF,	/* PCH Mobile SFF Full Featured */
202	LPC_QS57,	/* QS57 */
203	LPC_3400,	/* 3400 */
204	LPC_3420,	/* 3420 */
205	LPC_3450,	/* 3450 */
206	LPC_EP80579,	/* EP80579 */
207	LPC_CPT,	/* Cougar Point */
208	LPC_CPTD,	/* Cougar Point Desktop */
209	LPC_CPTM,	/* Cougar Point Mobile */
210	LPC_PBG,	/* Patsburg */
211	LPC_DH89XXCC,	/* DH89xxCC */
212	LPC_PPT,	/* Panther Point */
213	LPC_LPT,	/* Lynx Point */
214	LPC_LPT_LP,	/* Lynx Point-LP */
215	LPC_WBG,	/* Wellsburg */
216	LPC_AVN,	/* Avoton SoC */
217	LPC_BAYTRAIL,   /* Bay Trail SoC */
218	LPC_COLETO,	/* Coleto Creek */
219	LPC_WPT_LP,	/* Wildcat Point-LP */
220	LPC_BRASWELL,	/* Braswell SoC */
221	LPC_9S,		/* 9 Series */
222};
223
224static struct lpc_ich_info lpc_chipset_info[] = {
225	[LPC_ICH] = {
226		.name = "ICH",
227		.iTCO_version = 1,
228	},
229	[LPC_ICH0] = {
230		.name = "ICH0",
231		.iTCO_version = 1,
232	},
233	[LPC_ICH2] = {
234		.name = "ICH2",
235		.iTCO_version = 1,
236	},
237	[LPC_ICH2M] = {
238		.name = "ICH2-M",
239		.iTCO_version = 1,
240	},
241	[LPC_ICH3] = {
242		.name = "ICH3-S",
243		.iTCO_version = 1,
244	},
245	[LPC_ICH3M] = {
246		.name = "ICH3-M",
247		.iTCO_version = 1,
248	},
249	[LPC_ICH4] = {
250		.name = "ICH4",
251		.iTCO_version = 1,
252	},
253	[LPC_ICH4M] = {
254		.name = "ICH4-M",
255		.iTCO_version = 1,
256	},
257	[LPC_CICH] = {
258		.name = "C-ICH",
259		.iTCO_version = 1,
260	},
261	[LPC_ICH5] = {
262		.name = "ICH5 or ICH5R",
263		.iTCO_version = 1,
264	},
265	[LPC_6300ESB] = {
266		.name = "6300ESB",
267		.iTCO_version = 1,
268	},
269	[LPC_ICH6] = {
270		.name = "ICH6 or ICH6R",
271		.iTCO_version = 2,
272		.gpio_version = ICH_V6_GPIO,
273	},
274	[LPC_ICH6M] = {
275		.name = "ICH6-M",
276		.iTCO_version = 2,
277		.gpio_version = ICH_V6_GPIO,
278	},
279	[LPC_ICH6W] = {
280		.name = "ICH6W or ICH6RW",
281		.iTCO_version = 2,
282		.gpio_version = ICH_V6_GPIO,
283	},
284	[LPC_631XESB] = {
285		.name = "631xESB/632xESB",
286		.iTCO_version = 2,
287		.gpio_version = ICH_V6_GPIO,
288	},
289	[LPC_ICH7] = {
290		.name = "ICH7 or ICH7R",
291		.iTCO_version = 2,
292		.gpio_version = ICH_V7_GPIO,
293	},
294	[LPC_ICH7DH] = {
295		.name = "ICH7DH",
296		.iTCO_version = 2,
297		.gpio_version = ICH_V7_GPIO,
298	},
299	[LPC_ICH7M] = {
300		.name = "ICH7-M or ICH7-U",
301		.iTCO_version = 2,
302		.gpio_version = ICH_V7_GPIO,
303	},
304	[LPC_ICH7MDH] = {
305		.name = "ICH7-M DH",
306		.iTCO_version = 2,
307		.gpio_version = ICH_V7_GPIO,
308	},
309	[LPC_NM10] = {
310		.name = "NM10",
311		.iTCO_version = 2,
312		.gpio_version = ICH_V7_GPIO,
313	},
314	[LPC_ICH8] = {
315		.name = "ICH8 or ICH8R",
316		.iTCO_version = 2,
317		.gpio_version = ICH_V7_GPIO,
318	},
319	[LPC_ICH8DH] = {
320		.name = "ICH8DH",
321		.iTCO_version = 2,
322		.gpio_version = ICH_V7_GPIO,
323	},
324	[LPC_ICH8DO] = {
325		.name = "ICH8DO",
326		.iTCO_version = 2,
327		.gpio_version = ICH_V7_GPIO,
328	},
329	[LPC_ICH8M] = {
330		.name = "ICH8M",
331		.iTCO_version = 2,
332		.gpio_version = ICH_V7_GPIO,
333	},
334	[LPC_ICH8ME] = {
335		.name = "ICH8M-E",
336		.iTCO_version = 2,
337		.gpio_version = ICH_V7_GPIO,
338	},
339	[LPC_ICH9] = {
340		.name = "ICH9",
341		.iTCO_version = 2,
342		.gpio_version = ICH_V9_GPIO,
343	},
344	[LPC_ICH9R] = {
345		.name = "ICH9R",
346		.iTCO_version = 2,
347		.gpio_version = ICH_V9_GPIO,
348	},
349	[LPC_ICH9DH] = {
350		.name = "ICH9DH",
351		.iTCO_version = 2,
352		.gpio_version = ICH_V9_GPIO,
353	},
354	[LPC_ICH9DO] = {
355		.name = "ICH9DO",
356		.iTCO_version = 2,
357		.gpio_version = ICH_V9_GPIO,
358	},
359	[LPC_ICH9M] = {
360		.name = "ICH9M",
361		.iTCO_version = 2,
362		.gpio_version = ICH_V9_GPIO,
363	},
364	[LPC_ICH9ME] = {
365		.name = "ICH9M-E",
366		.iTCO_version = 2,
367		.gpio_version = ICH_V9_GPIO,
368	},
369	[LPC_ICH10] = {
370		.name = "ICH10",
371		.iTCO_version = 2,
372		.gpio_version = ICH_V10CONS_GPIO,
373	},
374	[LPC_ICH10R] = {
375		.name = "ICH10R",
376		.iTCO_version = 2,
377		.gpio_version = ICH_V10CONS_GPIO,
378	},
379	[LPC_ICH10D] = {
380		.name = "ICH10D",
381		.iTCO_version = 2,
382		.gpio_version = ICH_V10CORP_GPIO,
383	},
384	[LPC_ICH10DO] = {
385		.name = "ICH10DO",
386		.iTCO_version = 2,
387		.gpio_version = ICH_V10CORP_GPIO,
388	},
389	[LPC_PCH] = {
390		.name = "PCH Desktop Full Featured",
391		.iTCO_version = 2,
392		.gpio_version = ICH_V5_GPIO,
393	},
394	[LPC_PCHM] = {
395		.name = "PCH Mobile Full Featured",
396		.iTCO_version = 2,
397		.gpio_version = ICH_V5_GPIO,
398	},
399	[LPC_P55] = {
400		.name = "P55",
401		.iTCO_version = 2,
402		.gpio_version = ICH_V5_GPIO,
403	},
404	[LPC_PM55] = {
405		.name = "PM55",
406		.iTCO_version = 2,
407		.gpio_version = ICH_V5_GPIO,
408	},
409	[LPC_H55] = {
410		.name = "H55",
411		.iTCO_version = 2,
412		.gpio_version = ICH_V5_GPIO,
413	},
414	[LPC_QM57] = {
415		.name = "QM57",
416		.iTCO_version = 2,
417		.gpio_version = ICH_V5_GPIO,
418	},
419	[LPC_H57] = {
420		.name = "H57",
421		.iTCO_version = 2,
422		.gpio_version = ICH_V5_GPIO,
423	},
424	[LPC_HM55] = {
425		.name = "HM55",
426		.iTCO_version = 2,
427		.gpio_version = ICH_V5_GPIO,
428	},
429	[LPC_Q57] = {
430		.name = "Q57",
431		.iTCO_version = 2,
432		.gpio_version = ICH_V5_GPIO,
433	},
434	[LPC_HM57] = {
435		.name = "HM57",
436		.iTCO_version = 2,
437		.gpio_version = ICH_V5_GPIO,
438	},
439	[LPC_PCHMSFF] = {
440		.name = "PCH Mobile SFF Full Featured",
441		.iTCO_version = 2,
442		.gpio_version = ICH_V5_GPIO,
443	},
444	[LPC_QS57] = {
445		.name = "QS57",
446		.iTCO_version = 2,
447		.gpio_version = ICH_V5_GPIO,
448	},
449	[LPC_3400] = {
450		.name = "3400",
451		.iTCO_version = 2,
452		.gpio_version = ICH_V5_GPIO,
453	},
454	[LPC_3420] = {
455		.name = "3420",
456		.iTCO_version = 2,
457		.gpio_version = ICH_V5_GPIO,
458	},
459	[LPC_3450] = {
460		.name = "3450",
461		.iTCO_version = 2,
462		.gpio_version = ICH_V5_GPIO,
463	},
464	[LPC_EP80579] = {
465		.name = "EP80579",
466		.iTCO_version = 2,
467	},
468	[LPC_CPT] = {
469		.name = "Cougar Point",
470		.iTCO_version = 2,
471		.gpio_version = ICH_V5_GPIO,
472	},
473	[LPC_CPTD] = {
474		.name = "Cougar Point Desktop",
475		.iTCO_version = 2,
476		.gpio_version = ICH_V5_GPIO,
477	},
478	[LPC_CPTM] = {
479		.name = "Cougar Point Mobile",
480		.iTCO_version = 2,
481		.gpio_version = ICH_V5_GPIO,
482	},
483	[LPC_PBG] = {
484		.name = "Patsburg",
485		.iTCO_version = 2,
486	},
487	[LPC_DH89XXCC] = {
488		.name = "DH89xxCC",
489		.iTCO_version = 2,
490	},
491	[LPC_PPT] = {
492		.name = "Panther Point",
493		.iTCO_version = 2,
494		.gpio_version = ICH_V5_GPIO,
495	},
496	[LPC_LPT] = {
497		.name = "Lynx Point",
498		.iTCO_version = 2,
499	},
500	[LPC_LPT_LP] = {
501		.name = "Lynx Point_LP",
502		.iTCO_version = 2,
503	},
504	[LPC_WBG] = {
505		.name = "Wellsburg",
506		.iTCO_version = 2,
507	},
508	[LPC_AVN] = {
509		.name = "Avoton SoC",
510		.iTCO_version = 3,
511		.gpio_version = AVOTON_GPIO,
512	},
513	[LPC_BAYTRAIL] = {
514		.name = "Bay Trail SoC",
515		.iTCO_version = 3,
516	},
517	[LPC_COLETO] = {
518		.name = "Coleto Creek",
519		.iTCO_version = 2,
520	},
521	[LPC_WPT_LP] = {
522		.name = "Wildcat Point_LP",
523		.iTCO_version = 2,
524	},
525	[LPC_BRASWELL] = {
526		.name = "Braswell SoC",
527		.iTCO_version = 3,
528	},
529	[LPC_9S] = {
530		.name = "9 Series",
531		.iTCO_version = 2,
532	},
533};
534
535/*
536 * This data only exists for exporting the supported PCI ids
537 * via MODULE_DEVICE_TABLE.  We do not actually register a
538 * pci_driver, because the I/O Controller Hub has also other
539 * functions that probably will be registered by other drivers.
540 */
541static const struct pci_device_id lpc_ich_ids[] = {
542	{ PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
543	{ PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
544	{ PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
545	{ PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
546	{ PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
547	{ PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
548	{ PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
549	{ PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
550	{ PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
551	{ PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
552	{ PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
553	{ PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
554	{ PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
555	{ PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
556	{ PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
557	{ PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
558	{ PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
559	{ PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
560	{ PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
561	{ PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
562	{ PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
563	{ PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
564	{ PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
565	{ PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
566	{ PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
567	{ PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
568	{ PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
569	{ PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
570	{ PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
571	{ PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
572	{ PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
573	{ PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
574	{ PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
575	{ PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
576	{ PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
577	{ PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
578	{ PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
579	{ PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
580	{ PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
581	{ PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
582	{ PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
583	{ PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
584	{ PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
585	{ PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
586	{ PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
587	{ PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
588	{ PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
589	{ PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
590	{ PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
591	{ PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
592	{ PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
593	{ PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
594	{ PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
595	{ PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
596	{ PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
597	{ PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
598	{ PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
599	{ PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
600	{ PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
601	{ PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
602	{ PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
603	{ PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
604	{ PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
605	{ PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
606	{ PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
607	{ PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
608	{ PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
609	{ PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
610	{ PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
611	{ PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
612	{ PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
613	{ PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
614	{ PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
615	{ PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
616	{ PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
617	{ PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
618	{ PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
619	{ PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
620	{ PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
621	{ PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
622	{ PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
623	{ PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
624	{ PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
625	{ PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
626	{ PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
627	{ PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
628	{ PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
629	{ PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
630	{ PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
631	{ PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
632	{ PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
633	{ PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
634	{ PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
635	{ PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
636	{ PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
637	{ PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
638	{ PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
639	{ PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
640	{ PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
641	{ PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
642	{ PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
643	{ PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
644	{ PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
645	{ PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
646	{ PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
647	{ PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
648	{ PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
649	{ PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
650	{ PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
651	{ PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
652	{ PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
653	{ PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
654	{ PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
655	{ PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
656	{ PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
657	{ PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
658	{ PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
659	{ PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
660	{ PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
661	{ PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
662	{ PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
663	{ PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
664	{ PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
665	{ PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
666	{ PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
667	{ PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
668	{ PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
669	{ PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
670	{ PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
671	{ PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
672	{ PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
673	{ PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
674	{ PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
675	{ PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
676	{ PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
677	{ PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
678	{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
679	{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
680	{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
681	{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
682	{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
683	{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
684	{ PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
685	{ PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
686	{ PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
687	{ PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
688	{ PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
689	{ PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
690	{ PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
691	{ PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
692	{ PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
693	{ PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
694	{ PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
695	{ PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
696	{ PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
697	{ PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
698	{ PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
699	{ PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
700	{ PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
701	{ PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
702	{ PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
703	{ PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
704	{ PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
705	{ PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
706	{ PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
707	{ PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
708	{ PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
709	{ PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
710	{ PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
711	{ PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
712	{ PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
713	{ PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
714	{ PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
715	{ PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
716	{ PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
717	{ PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
718	{ PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
719	{ PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
720	{ PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
721	{ PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
722	{ PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
723	{ PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
724	{ PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
725	{ PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
726	{ PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
727	{ PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
728	{ PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
729	{ PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
730	{ PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
731	{ PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
732	{ PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
733	{ PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
734	{ PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
735	{ PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
736	{ PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
737	{ PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
738	{ PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
739	{ PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
740	{ PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
741	{ PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
742	{ PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
743	{ PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
744	{ PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
745	{ PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
746	{ PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
747	{ PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
748	{ PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
749	{ PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
750	{ PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
751	{ PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
752	{ PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
753	{ PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
754	{ PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
755	{ PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
756	{ PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
757	{ PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
758	{ PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
759	{ PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
760	{ PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
761	{ PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
762	{ PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
763	{ PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
764	{ PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
765	{ 0, },			/* End of list */
766};
767MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
768
769static void lpc_ich_restore_config_space(struct pci_dev *dev)
770{
771	struct lpc_ich_priv *priv = pci_get_drvdata(dev);
772
773	if (priv->abase_save >= 0) {
774		pci_write_config_byte(dev, priv->abase, priv->abase_save);
775		priv->abase_save = -1;
776	}
777
778	if (priv->actrl_pbase_save >= 0) {
779		pci_write_config_byte(dev, priv->actrl_pbase,
780			priv->actrl_pbase_save);
781		priv->actrl_pbase_save = -1;
782	}
783
784	if (priv->gctrl_save >= 0) {
785		pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
786		priv->gctrl_save = -1;
787	}
788}
789
790static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
791{
792	struct lpc_ich_priv *priv = pci_get_drvdata(dev);
793	u8 reg_save;
794
795	switch (lpc_chipset_info[priv->chipset].iTCO_version) {
796	case 3:
797		/*
798		 * Some chipsets (eg Avoton) enable the ACPI space in the
799		 * ACPI BASE register.
800		 */
801		pci_read_config_byte(dev, priv->abase, &reg_save);
802		pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
803		priv->abase_save = reg_save;
804		break;
805	default:
806		/*
807		 * Most chipsets enable the ACPI space in the ACPI control
808		 * register.
809		 */
810		pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
811		pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
812		priv->actrl_pbase_save = reg_save;
813		break;
814	}
815}
816
817static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
818{
819	struct lpc_ich_priv *priv = pci_get_drvdata(dev);
820	u8 reg_save;
821
822	pci_read_config_byte(dev, priv->gctrl, &reg_save);
823	pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
824	priv->gctrl_save = reg_save;
825}
826
827static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
828{
829	struct lpc_ich_priv *priv = pci_get_drvdata(dev);
830	u8 reg_save;
831
832	pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
833	pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
834
835	priv->actrl_pbase_save = reg_save;
836}
837
838static void lpc_ich_finalize_cell(struct pci_dev *dev, struct mfd_cell *cell)
839{
840	struct lpc_ich_priv *priv = pci_get_drvdata(dev);
841
842	cell->platform_data = &lpc_chipset_info[priv->chipset];
843	cell->pdata_size = sizeof(struct lpc_ich_info);
844}
845
846/*
847 * We don't check for resource conflict globally. There are 2 or 3 independent
848 * GPIO groups and it's enough to have access to one of these to instantiate
849 * the device.
850 */
851static int lpc_ich_check_conflict_gpio(struct resource *res)
852{
853	int ret;
854	u8 use_gpio = 0;
855
856	if (resource_size(res) >= 0x50 &&
857	    !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
858		use_gpio |= 1 << 2;
859
860	if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
861		use_gpio |= 1 << 1;
862
863	ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
864	if (!ret)
865		use_gpio |= 1 << 0;
866
867	return use_gpio ? use_gpio : ret;
868}
869
870static int lpc_ich_init_gpio(struct pci_dev *dev)
871{
872	struct lpc_ich_priv *priv = pci_get_drvdata(dev);
873	u32 base_addr_cfg;
874	u32 base_addr;
875	int ret;
876	bool acpi_conflict = false;
877	struct resource *res;
878
879	/* Setup power management base register */
880	pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
881	base_addr = base_addr_cfg & 0x0000ff80;
882	if (!base_addr) {
883		dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
884		lpc_ich_cells[LPC_GPIO].num_resources--;
885		goto gpe0_done;
886	}
887
888	res = &gpio_ich_res[ICH_RES_GPE0];
889	res->start = base_addr + ACPIBASE_GPE_OFF;
890	res->end = base_addr + ACPIBASE_GPE_END;
891	ret = acpi_check_resource_conflict(res);
892	if (ret) {
893		/*
894		 * This isn't fatal for the GPIO, but we have to make sure that
895		 * the platform_device subsystem doesn't see this resource
896		 * or it will register an invalid region.
897		 */
898		lpc_ich_cells[LPC_GPIO].num_resources--;
899		acpi_conflict = true;
900	} else {
901		lpc_ich_enable_acpi_space(dev);
902	}
903
904gpe0_done:
905	/* Setup GPIO base register */
906	pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
907	base_addr = base_addr_cfg & 0x0000ff80;
908	if (!base_addr) {
909		dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
910		ret = -ENODEV;
911		goto gpio_done;
912	}
913
914	/* Older devices provide fewer GPIO and have a smaller resource size. */
915	res = &gpio_ich_res[ICH_RES_GPIO];
916	res->start = base_addr;
917	switch (lpc_chipset_info[priv->chipset].gpio_version) {
918	case ICH_V5_GPIO:
919	case ICH_V10CORP_GPIO:
920		res->end = res->start + 128 - 1;
921		break;
922	default:
923		res->end = res->start + 64 - 1;
924		break;
925	}
926
927	ret = lpc_ich_check_conflict_gpio(res);
928	if (ret < 0) {
929		/* this isn't necessarily fatal for the GPIO */
930		acpi_conflict = true;
931		goto gpio_done;
932	}
933	lpc_chipset_info[priv->chipset].use_gpio = ret;
934	lpc_ich_enable_gpio_space(dev);
935
936	lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_GPIO]);
937	ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_GPIO],
938			      1, NULL, 0, NULL);
939
940gpio_done:
941	if (acpi_conflict)
942		pr_warn("Resource conflict(s) found affecting %s\n",
943				lpc_ich_cells[LPC_GPIO].name);
944	return ret;
945}
946
947static int lpc_ich_init_wdt(struct pci_dev *dev)
948{
949	struct lpc_ich_priv *priv = pci_get_drvdata(dev);
950	u32 base_addr_cfg;
951	u32 base_addr;
952	int ret;
953	struct resource *res;
954
955	/* Setup power management base register */
956	pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
957	base_addr = base_addr_cfg & 0x0000ff80;
958	if (!base_addr) {
959		dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
960		ret = -ENODEV;
961		goto wdt_done;
962	}
963
964	res = wdt_io_res(ICH_RES_IO_TCO);
965	res->start = base_addr + ACPIBASE_TCO_OFF;
966	res->end = base_addr + ACPIBASE_TCO_END;
967
968	res = wdt_io_res(ICH_RES_IO_SMI);
969	res->start = base_addr + ACPIBASE_SMI_OFF;
970	res->end = base_addr + ACPIBASE_SMI_END;
971
972	lpc_ich_enable_acpi_space(dev);
973
974	/*
975	 * iTCO v2:
976	 * Get the Memory-Mapped GCS register. To get access to it
977	 * we have to read RCBA from PCI Config space 0xf0 and use
978	 * it as base. GCS = RCBA + ICH6_GCS(0x3410).
979	 *
980	 * iTCO v3:
981	 * Get the Power Management Configuration register.  To get access
982	 * to it we have to read the PMC BASE from config space and address
983	 * the register at offset 0x8.
984	 */
985	if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
986		/* Don't register iomem for TCO ver 1 */
987		lpc_ich_cells[LPC_WDT].num_resources--;
988	} else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
989		pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
990		base_addr = base_addr_cfg & 0xffffc000;
991		if (!(base_addr_cfg & 1)) {
992			dev_notice(&dev->dev, "RCBA is disabled by "
993					"hardware/BIOS, device disabled\n");
994			ret = -ENODEV;
995			goto wdt_done;
996		}
997		res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
998		res->start = base_addr + ACPIBASE_GCS_OFF;
999		res->end = base_addr + ACPIBASE_GCS_END;
1000	} else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
1001		lpc_ich_enable_pmc_space(dev);
1002		pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
1003		base_addr = base_addr_cfg & 0xfffffe00;
1004
1005		res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1006		res->start = base_addr + ACPIBASE_PMC_OFF;
1007		res->end = base_addr + ACPIBASE_PMC_END;
1008	}
1009
1010	lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_WDT]);
1011	ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_WDT],
1012			      1, NULL, 0, NULL);
1013
1014wdt_done:
1015	return ret;
1016}
1017
1018static int lpc_ich_probe(struct pci_dev *dev,
1019				const struct pci_device_id *id)
1020{
1021	struct lpc_ich_priv *priv;
1022	int ret;
1023	bool cell_added = false;
1024
1025	priv = devm_kzalloc(&dev->dev,
1026			    sizeof(struct lpc_ich_priv), GFP_KERNEL);
1027	if (!priv)
1028		return -ENOMEM;
1029
1030	priv->chipset = id->driver_data;
1031
1032	priv->actrl_pbase_save = -1;
1033	priv->abase_save = -1;
1034
1035	priv->abase = ACPIBASE;
1036	priv->actrl_pbase = ACPICTRL_PMCBASE;
1037
1038	priv->gctrl_save = -1;
1039	if (priv->chipset <= LPC_ICH5) {
1040		priv->gbase = GPIOBASE_ICH0;
1041		priv->gctrl = GPIOCTRL_ICH0;
1042	} else {
1043		priv->gbase = GPIOBASE_ICH6;
1044		priv->gctrl = GPIOCTRL_ICH6;
1045	}
1046
1047	pci_set_drvdata(dev, priv);
1048
1049	if (lpc_chipset_info[priv->chipset].iTCO_version) {
1050		ret = lpc_ich_init_wdt(dev);
1051		if (!ret)
1052			cell_added = true;
1053	}
1054
1055	if (lpc_chipset_info[priv->chipset].gpio_version) {
1056		ret = lpc_ich_init_gpio(dev);
1057		if (!ret)
1058			cell_added = true;
1059	}
1060
1061	/*
1062	 * We only care if at least one or none of the cells registered
1063	 * successfully.
1064	 */
1065	if (!cell_added) {
1066		dev_warn(&dev->dev, "No MFD cells added\n");
1067		lpc_ich_restore_config_space(dev);
1068		return -ENODEV;
1069	}
1070
1071	return 0;
1072}
1073
1074static void lpc_ich_remove(struct pci_dev *dev)
1075{
1076	mfd_remove_devices(&dev->dev);
1077	lpc_ich_restore_config_space(dev);
1078}
1079
1080static struct pci_driver lpc_ich_driver = {
1081	.name		= "lpc_ich",
1082	.id_table	= lpc_ich_ids,
1083	.probe		= lpc_ich_probe,
1084	.remove		= lpc_ich_remove,
1085};
1086
1087module_pci_driver(lpc_ich_driver);
1088
1089MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1090MODULE_DESCRIPTION("LPC interface for Intel ICH");
1091MODULE_LICENSE("GPL");
1092