1/* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 */ 13 14#include <linux/types.h> 15#include <linux/kernel.h> 16#include <linux/export.h> 17#include <linux/pci.h> 18#include <linux/init.h> 19#include <linux/delay.h> 20#include <linux/acpi.h> 21#include <linux/kallsyms.h> 22#include <linux/dmi.h> 23#include <linux/pci-aspm.h> 24#include <linux/ioport.h> 25#include <linux/sched.h> 26#include <linux/ktime.h> 27#include <linux/mm.h> 28#include <asm/dma.h> /* isa_dma_bridge_buggy */ 29#include "pci.h" 30 31/* 32 * Decoding should be disabled for a PCI device during BAR sizing to avoid 33 * conflict. But doing so may cause problems on host bridge and perhaps other 34 * key system devices. For devices that need to have mmio decoding always-on, 35 * we need to set the dev->mmio_always_on bit. 36 */ 37static void quirk_mmio_always_on(struct pci_dev *dev) 38{ 39 dev->mmio_always_on = 1; 40} 41DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 43 44/* The Mellanox Tavor device gives false positive parity errors 45 * Mark this device with a broken_parity_status, to allow 46 * PCI scanning code to "skip" this now blacklisted device. 47 */ 48static void quirk_mellanox_tavor(struct pci_dev *dev) 49{ 50 dev->broken_parity_status = 1; /* This device gives false positives */ 51} 52DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 53DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 54 55/* Deal with broken BIOSes that neglect to enable passive release, 56 which can cause problems in combination with the 82441FX/PPro MTRRs */ 57static void quirk_passive_release(struct pci_dev *dev) 58{ 59 struct pci_dev *d = NULL; 60 unsigned char dlc; 61 62 /* We have to make sure a particular bit is set in the PIIX3 63 ISA bridge, so we have to go out and find it. */ 64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 65 pci_read_config_byte(d, 0x82, &dlc); 66 if (!(dlc & 1<<1)) { 67 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); 68 dlc |= 1<<1; 69 pci_write_config_byte(d, 0x82, dlc); 70 } 71 } 72} 73DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 74DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 75 76/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 77 but VIA don't answer queries. If you happen to have good contacts at VIA 78 ask them for me please -- Alan 79 80 This appears to be BIOS not version dependent. So presumably there is a 81 chipset level fix */ 82 83static void quirk_isa_dma_hangs(struct pci_dev *dev) 84{ 85 if (!isa_dma_bridge_buggy) { 86 isa_dma_bridge_buggy = 1; 87 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 88 } 89} 90 /* 91 * Its not totally clear which chipsets are the problematic ones 92 * We know 82C586 and 82C596 variants are affected. 93 */ 94DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 95DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 101 102/* 103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 104 * for some HT machines to use C4 w/o hanging. 105 */ 106static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 107{ 108 u32 pmbase; 109 u16 pm1a; 110 111 pci_read_config_dword(dev, 0x40, &pmbase); 112 pmbase = pmbase & 0xff80; 113 pm1a = inw(pmbase); 114 115 if (pm1a & 0x10) { 116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 117 outw(0x10, pmbase); 118 } 119} 120DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 121 122/* 123 * Chipsets where PCI->PCI transfers vanish or hang 124 */ 125static void quirk_nopcipci(struct pci_dev *dev) 126{ 127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 129 pci_pci_problems |= PCIPCI_FAIL; 130 } 131} 132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 133DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 134 135static void quirk_nopciamd(struct pci_dev *dev) 136{ 137 u8 rev; 138 pci_read_config_byte(dev, 0x08, &rev); 139 if (rev == 0x13) { 140 /* Erratum 24 */ 141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 142 pci_pci_problems |= PCIAGP_FAIL; 143 } 144} 145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 146 147/* 148 * Triton requires workarounds to be used by the drivers 149 */ 150static void quirk_triton(struct pci_dev *dev) 151{ 152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 154 pci_pci_problems |= PCIPCI_TRITON; 155 } 156} 157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 161 162/* 163 * VIA Apollo KT133 needs PCI latency patch 164 * Made according to a windows driver based patch by George E. Breese 165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 166 * and http://www.georgebreese.com/net/software/#PCI 167 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 168 * the info on which Mr Breese based his work. 169 * 170 * Updated based on further information from the site and also on 171 * information provided by VIA 172 */ 173static void quirk_vialatency(struct pci_dev *dev) 174{ 175 struct pci_dev *p; 176 u8 busarb; 177 /* Ok we have a potential problem chipset here. Now see if we have 178 a buggy southbridge */ 179 180 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 181 if (p != NULL) { 182 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 183 /* Check for buggy part revisions */ 184 if (p->revision < 0x40 || p->revision > 0x42) 185 goto exit; 186 } else { 187 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 188 if (p == NULL) /* No problem parts */ 189 goto exit; 190 /* Check for buggy part revisions */ 191 if (p->revision < 0x10 || p->revision > 0x12) 192 goto exit; 193 } 194 195 /* 196 * Ok we have the problem. Now set the PCI master grant to 197 * occur every master grant. The apparent bug is that under high 198 * PCI load (quite common in Linux of course) you can get data 199 * loss when the CPU is held off the bus for 3 bus master requests 200 * This happens to include the IDE controllers.... 201 * 202 * VIA only apply this fix when an SB Live! is present but under 203 * both Linux and Windows this isn't enough, and we have seen 204 * corruption without SB Live! but with things like 3 UDMA IDE 205 * controllers. So we ignore that bit of the VIA recommendation.. 206 */ 207 208 pci_read_config_byte(dev, 0x76, &busarb); 209 /* Set bit 4 and bi 5 of byte 76 to 0x01 210 "Master priority rotation on every PCI master grant */ 211 busarb &= ~(1<<5); 212 busarb |= (1<<4); 213 pci_write_config_byte(dev, 0x76, busarb); 214 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 215exit: 216 pci_dev_put(p); 217} 218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 221/* Must restore this on a resume from RAM */ 222DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 223DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 224DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 225 226/* 227 * VIA Apollo VP3 needs ETBF on BT848/878 228 */ 229static void quirk_viaetbf(struct pci_dev *dev) 230{ 231 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 232 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 233 pci_pci_problems |= PCIPCI_VIAETBF; 234 } 235} 236DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 237 238static void quirk_vsfx(struct pci_dev *dev) 239{ 240 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 241 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 242 pci_pci_problems |= PCIPCI_VSFX; 243 } 244} 245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 246 247/* 248 * Ali Magik requires workarounds to be used by the drivers 249 * that DMA to AGP space. Latency must be set to 0xA and triton 250 * workaround applied too 251 * [Info kindly provided by ALi] 252 */ 253static void quirk_alimagik(struct pci_dev *dev) 254{ 255 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 256 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 257 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 258 } 259} 260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 262 263/* 264 * Natoma has some interesting boundary conditions with Zoran stuff 265 * at least 266 */ 267static void quirk_natoma(struct pci_dev *dev) 268{ 269 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 270 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 271 pci_pci_problems |= PCIPCI_NATOMA; 272 } 273} 274DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 275DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 276DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 280 281/* 282 * This chip can cause PCI parity errors if config register 0xA0 is read 283 * while DMAs are occurring. 284 */ 285static void quirk_citrine(struct pci_dev *dev) 286{ 287 dev->cfg_size = 0xA0; 288} 289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 290 291/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 292static void quirk_extend_bar_to_page(struct pci_dev *dev) 293{ 294 int i; 295 296 for (i = 0; i < PCI_STD_RESOURCE_END; i++) { 297 struct resource *r = &dev->resource[i]; 298 299 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 300 r->end = PAGE_SIZE - 1; 301 r->start = 0; 302 r->flags |= IORESOURCE_UNSET; 303 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n", 304 i, r); 305 } 306 } 307} 308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 309 310/* 311 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 312 * If it's needed, re-allocate the region. 313 */ 314static void quirk_s3_64M(struct pci_dev *dev) 315{ 316 struct resource *r = &dev->resource[0]; 317 318 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 319 r->flags |= IORESOURCE_UNSET; 320 r->start = 0; 321 r->end = 0x3ffffff; 322 } 323} 324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 326 327static void quirk_io(struct pci_dev *dev, int pos, unsigned size, 328 const char *name) 329{ 330 u32 region; 331 struct pci_bus_region bus_region; 332 struct resource *res = dev->resource + pos; 333 334 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 335 336 if (!region) 337 return; 338 339 res->name = pci_name(dev); 340 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 341 res->flags |= 342 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 343 region &= ~(size - 1); 344 345 /* Convert from PCI bus to resource space */ 346 bus_region.start = region; 347 bus_region.end = region + size - 1; 348 pcibios_bus_to_resource(dev->bus, res, &bus_region); 349 350 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", 351 name, PCI_BASE_ADDRESS_0 + (pos << 2), res); 352} 353 354/* 355 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 356 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 357 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 358 * (which conflicts w/ BAR1's memory range). 359 * 360 * CS553x's ISA PCI BARs may also be read-only (ref: 361 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 362 */ 363static void quirk_cs5536_vsa(struct pci_dev *dev) 364{ 365 static char *name = "CS5536 ISA bridge"; 366 367 if (pci_resource_len(dev, 0) != 8) { 368 quirk_io(dev, 0, 8, name); /* SMB */ 369 quirk_io(dev, 1, 256, name); /* GPIO */ 370 quirk_io(dev, 2, 64, name); /* MFGPT */ 371 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n", 372 name); 373 } 374} 375DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 376 377static void quirk_io_region(struct pci_dev *dev, int port, 378 unsigned size, int nr, const char *name) 379{ 380 u16 region; 381 struct pci_bus_region bus_region; 382 struct resource *res = dev->resource + nr; 383 384 pci_read_config_word(dev, port, ®ion); 385 region &= ~(size - 1); 386 387 if (!region) 388 return; 389 390 res->name = pci_name(dev); 391 res->flags = IORESOURCE_IO; 392 393 /* Convert from PCI bus to resource space */ 394 bus_region.start = region; 395 bus_region.end = region + size - 1; 396 pcibios_bus_to_resource(dev->bus, res, &bus_region); 397 398 if (!pci_claim_resource(dev, nr)) 399 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name); 400} 401 402/* 403 * ATI Northbridge setups MCE the processor if you even 404 * read somewhere between 0x3b0->0x3bb or read 0x3d3 405 */ 406static void quirk_ati_exploding_mce(struct pci_dev *dev) 407{ 408 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 409 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 410 request_region(0x3b0, 0x0C, "RadeonIGP"); 411 request_region(0x3d3, 0x01, "RadeonIGP"); 412} 413DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 414 415/* 416 * In the AMD NL platform, this device ([1022:7912]) has a class code of 417 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 418 * claim it. 419 * But the dwc3 driver is a more specific driver for this device, and we'd 420 * prefer to use it instead of xhci. To prevent xhci from claiming the 421 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 422 * defines as "USB device (not host controller)". The dwc3 driver can then 423 * claim it based on its Vendor and Device ID. 424 */ 425static void quirk_amd_nl_class(struct pci_dev *pdev) 426{ 427 /* 428 * Use 'USB Device' (0x0c03fe) instead of PCI header provided 429 */ 430 pdev->class = 0x0c03fe; 431} 432DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 433 quirk_amd_nl_class); 434 435/* 436 * Let's make the southbridge information explicit instead 437 * of having to worry about people probing the ACPI areas, 438 * for example.. (Yes, it happens, and if you read the wrong 439 * ACPI register it will put the machine to sleep with no 440 * way of waking it up again. Bummer). 441 * 442 * ALI M7101: Two IO regions pointed to by words at 443 * 0xE0 (64 bytes of ACPI registers) 444 * 0xE2 (32 bytes of SMB registers) 445 */ 446static void quirk_ali7101_acpi(struct pci_dev *dev) 447{ 448 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 449 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 450} 451DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 452 453static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 454{ 455 u32 devres; 456 u32 mask, size, base; 457 458 pci_read_config_dword(dev, port, &devres); 459 if ((devres & enable) != enable) 460 return; 461 mask = (devres >> 16) & 15; 462 base = devres & 0xffff; 463 size = 16; 464 for (;;) { 465 unsigned bit = size >> 1; 466 if ((bit & mask) == bit) 467 break; 468 size = bit; 469 } 470 /* 471 * For now we only print it out. Eventually we'll want to 472 * reserve it (at least if it's in the 0x1000+ range), but 473 * let's get enough confirmation reports first. 474 */ 475 base &= -size; 476 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, 477 base + size - 1); 478} 479 480static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 481{ 482 u32 devres; 483 u32 mask, size, base; 484 485 pci_read_config_dword(dev, port, &devres); 486 if ((devres & enable) != enable) 487 return; 488 base = devres & 0xffff0000; 489 mask = (devres & 0x3f) << 16; 490 size = 128 << 16; 491 for (;;) { 492 unsigned bit = size >> 1; 493 if ((bit & mask) == bit) 494 break; 495 size = bit; 496 } 497 /* 498 * For now we only print it out. Eventually we'll want to 499 * reserve it, but let's get enough confirmation reports first. 500 */ 501 base &= -size; 502 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, 503 base + size - 1); 504} 505 506/* 507 * PIIX4 ACPI: Two IO regions pointed to by longwords at 508 * 0x40 (64 bytes of ACPI registers) 509 * 0x90 (16 bytes of SMB registers) 510 * and a few strange programmable PIIX4 device resources. 511 */ 512static void quirk_piix4_acpi(struct pci_dev *dev) 513{ 514 u32 res_a; 515 516 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 517 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 518 519 /* Device resource A has enables for some of the other ones */ 520 pci_read_config_dword(dev, 0x5c, &res_a); 521 522 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 523 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 524 525 /* Device resource D is just bitfields for static resources */ 526 527 /* Device 12 enabled? */ 528 if (res_a & (1 << 29)) { 529 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 530 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 531 } 532 /* Device 13 enabled? */ 533 if (res_a & (1 << 30)) { 534 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 535 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 536 } 537 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 538 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 539} 540DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 541DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 542 543#define ICH_PMBASE 0x40 544#define ICH_ACPI_CNTL 0x44 545#define ICH4_ACPI_EN 0x10 546#define ICH6_ACPI_EN 0x80 547#define ICH4_GPIOBASE 0x58 548#define ICH4_GPIO_CNTL 0x5c 549#define ICH4_GPIO_EN 0x10 550#define ICH6_GPIOBASE 0x48 551#define ICH6_GPIO_CNTL 0x4c 552#define ICH6_GPIO_EN 0x10 553 554/* 555 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 556 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 557 * 0x58 (64 bytes of GPIO I/O space) 558 */ 559static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 560{ 561 u8 enable; 562 563 /* 564 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 565 * with low legacy (and fixed) ports. We don't know the decoding 566 * priority and can't tell whether the legacy device or the one created 567 * here is really at that address. This happens on boards with broken 568 * BIOSes. 569 */ 570 571 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 572 if (enable & ICH4_ACPI_EN) 573 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 574 "ICH4 ACPI/GPIO/TCO"); 575 576 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 577 if (enable & ICH4_GPIO_EN) 578 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 579 "ICH4 GPIO"); 580} 581DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 582DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 583DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 584DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 585DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 586DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 587DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 588DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 589DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 590DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 591 592static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 593{ 594 u8 enable; 595 596 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 597 if (enable & ICH6_ACPI_EN) 598 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 599 "ICH6 ACPI/GPIO/TCO"); 600 601 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 602 if (enable & ICH6_GPIO_EN) 603 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 604 "ICH6 GPIO"); 605} 606 607static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 608{ 609 u32 val; 610 u32 size, base; 611 612 pci_read_config_dword(dev, reg, &val); 613 614 /* Enabled? */ 615 if (!(val & 1)) 616 return; 617 base = val & 0xfffc; 618 if (dynsize) { 619 /* 620 * This is not correct. It is 16, 32 or 64 bytes depending on 621 * register D31:F0:ADh bits 5:4. 622 * 623 * But this gets us at least _part_ of it. 624 */ 625 size = 16; 626 } else { 627 size = 128; 628 } 629 base &= ~(size-1); 630 631 /* Just print it out for now. We should reserve it after more debugging */ 632 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 633} 634 635static void quirk_ich6_lpc(struct pci_dev *dev) 636{ 637 /* Shared ACPI/GPIO decode with all ICH6+ */ 638 ich6_lpc_acpi_gpio(dev); 639 640 /* ICH6-specific generic IO decode */ 641 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 642 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 643} 644DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 646 647static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 648{ 649 u32 val; 650 u32 mask, base; 651 652 pci_read_config_dword(dev, reg, &val); 653 654 /* Enabled? */ 655 if (!(val & 1)) 656 return; 657 658 /* 659 * IO base in bits 15:2, mask in bits 23:18, both 660 * are dword-based 661 */ 662 base = val & 0xfffc; 663 mask = (val >> 16) & 0xfc; 664 mask |= 3; 665 666 /* Just print it out for now. We should reserve it after more debugging */ 667 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 668} 669 670/* ICH7-10 has the same common LPC generic IO decode registers */ 671static void quirk_ich7_lpc(struct pci_dev *dev) 672{ 673 /* We share the common ACPI/GPIO decode with ICH6 */ 674 ich6_lpc_acpi_gpio(dev); 675 676 /* And have 4 ICH7+ generic decodes */ 677 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 678 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 679 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 680 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 681} 682DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 683DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 685DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 686DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 687DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 688DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 689DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 690DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 691DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 692DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 693DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 694DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 695 696/* 697 * VIA ACPI: One IO region pointed to by longword at 698 * 0x48 or 0x20 (256 bytes of ACPI registers) 699 */ 700static void quirk_vt82c586_acpi(struct pci_dev *dev) 701{ 702 if (dev->revision & 0x10) 703 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 704 "vt82c586 ACPI"); 705} 706DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 707 708/* 709 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 710 * 0x48 (256 bytes of ACPI registers) 711 * 0x70 (128 bytes of hardware monitoring register) 712 * 0x90 (16 bytes of SMB registers) 713 */ 714static void quirk_vt82c686_acpi(struct pci_dev *dev) 715{ 716 quirk_vt82c586_acpi(dev); 717 718 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 719 "vt82c686 HW-mon"); 720 721 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 722} 723DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 724 725/* 726 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 727 * 0x88 (128 bytes of power management registers) 728 * 0xd0 (16 bytes of SMB registers) 729 */ 730static void quirk_vt8235_acpi(struct pci_dev *dev) 731{ 732 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 733 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 734} 735DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 736 737/* 738 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 739 * Disable fast back-to-back on the secondary bus segment 740 */ 741static void quirk_xio2000a(struct pci_dev *dev) 742{ 743 struct pci_dev *pdev; 744 u16 command; 745 746 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 747 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 748 pci_read_config_word(pdev, PCI_COMMAND, &command); 749 if (command & PCI_COMMAND_FAST_BACK) 750 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 751 } 752} 753DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 754 quirk_xio2000a); 755 756#ifdef CONFIG_X86_IO_APIC 757 758#include <asm/io_apic.h> 759 760/* 761 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 762 * devices to the external APIC. 763 * 764 * TODO: When we have device-specific interrupt routers, 765 * this code will go away from quirks. 766 */ 767static void quirk_via_ioapic(struct pci_dev *dev) 768{ 769 u8 tmp; 770 771 if (nr_ioapics < 1) 772 tmp = 0; /* nothing routed to external APIC */ 773 else 774 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 775 776 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 777 tmp == 0 ? "Disa" : "Ena"); 778 779 /* Offset 0x58: External APIC IRQ output control */ 780 pci_write_config_byte(dev, 0x58, tmp); 781} 782DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 783DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 784 785/* 786 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 787 * This leads to doubled level interrupt rates. 788 * Set this bit to get rid of cycle wastage. 789 * Otherwise uncritical. 790 */ 791static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 792{ 793 u8 misc_control2; 794#define BYPASS_APIC_DEASSERT 8 795 796 pci_read_config_byte(dev, 0x5B, &misc_control2); 797 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 798 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 799 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 800 } 801} 802DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 803DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 804 805/* 806 * The AMD io apic can hang the box when an apic irq is masked. 807 * We check all revs >= B0 (yet not in the pre production!) as the bug 808 * is currently marked NoFix 809 * 810 * We have multiple reports of hangs with this chipset that went away with 811 * noapic specified. For the moment we assume it's the erratum. We may be wrong 812 * of course. However the advice is demonstrably good even if so.. 813 */ 814static void quirk_amd_ioapic(struct pci_dev *dev) 815{ 816 if (dev->revision >= 0x02) { 817 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 818 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 819 } 820} 821DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 822 823static void quirk_ioapic_rmw(struct pci_dev *dev) 824{ 825 if (dev->devfn == 0 && dev->bus->number == 0) 826 sis_apic_bug = 1; 827} 828DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); 829#endif /* CONFIG_X86_IO_APIC */ 830 831/* 832 * Some settings of MMRBC can lead to data corruption so block changes. 833 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 834 */ 835static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 836{ 837 if (dev->subordinate && dev->revision <= 0x12) { 838 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 839 dev->revision); 840 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 841 } 842} 843DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 844 845/* 846 * FIXME: it is questionable that quirk_via_acpi 847 * is needed. It shows up as an ISA bridge, and does not 848 * support the PCI_INTERRUPT_LINE register at all. Therefore 849 * it seems like setting the pci_dev's 'irq' to the 850 * value of the ACPI SCI interrupt is only done for convenience. 851 * -jgarzik 852 */ 853static void quirk_via_acpi(struct pci_dev *d) 854{ 855 /* 856 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 857 */ 858 u8 irq; 859 pci_read_config_byte(d, 0x42, &irq); 860 irq &= 0xf; 861 if (irq && (irq != 2)) 862 d->irq = irq; 863} 864DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 865DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 866 867 868/* 869 * VIA bridges which have VLink 870 */ 871 872static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 873 874static void quirk_via_bridge(struct pci_dev *dev) 875{ 876 /* See what bridge we have and find the device ranges */ 877 switch (dev->device) { 878 case PCI_DEVICE_ID_VIA_82C686: 879 /* The VT82C686 is special, it attaches to PCI and can have 880 any device number. All its subdevices are functions of 881 that single device. */ 882 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 883 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 884 break; 885 case PCI_DEVICE_ID_VIA_8237: 886 case PCI_DEVICE_ID_VIA_8237A: 887 via_vlink_dev_lo = 15; 888 break; 889 case PCI_DEVICE_ID_VIA_8235: 890 via_vlink_dev_lo = 16; 891 break; 892 case PCI_DEVICE_ID_VIA_8231: 893 case PCI_DEVICE_ID_VIA_8233_0: 894 case PCI_DEVICE_ID_VIA_8233A: 895 case PCI_DEVICE_ID_VIA_8233C_0: 896 via_vlink_dev_lo = 17; 897 break; 898 } 899} 900DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 901DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 902DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 903DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 904DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 905DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 906DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 907DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 908 909/** 910 * quirk_via_vlink - VIA VLink IRQ number update 911 * @dev: PCI device 912 * 913 * If the device we are dealing with is on a PIC IRQ we need to 914 * ensure that the IRQ line register which usually is not relevant 915 * for PCI cards, is actually written so that interrupts get sent 916 * to the right place. 917 * We only do this on systems where a VIA south bridge was detected, 918 * and only for VIA devices on the motherboard (see quirk_via_bridge 919 * above). 920 */ 921 922static void quirk_via_vlink(struct pci_dev *dev) 923{ 924 u8 irq, new_irq; 925 926 /* Check if we have VLink at all */ 927 if (via_vlink_dev_lo == -1) 928 return; 929 930 new_irq = dev->irq; 931 932 /* Don't quirk interrupts outside the legacy IRQ range */ 933 if (!new_irq || new_irq > 15) 934 return; 935 936 /* Internal device ? */ 937 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 938 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 939 return; 940 941 /* This is an internal VLink device on a PIC interrupt. The BIOS 942 ought to have set this but may not have, so we redo it */ 943 944 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 945 if (new_irq != irq) { 946 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 947 irq, new_irq); 948 udelay(15); /* unknown if delay really needed */ 949 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 950 } 951} 952DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 953 954/* 955 * VIA VT82C598 has its device ID settable and many BIOSes 956 * set it to the ID of VT82C597 for backward compatibility. 957 * We need to switch it off to be able to recognize the real 958 * type of the chip. 959 */ 960static void quirk_vt82c598_id(struct pci_dev *dev) 961{ 962 pci_write_config_byte(dev, 0xfc, 0); 963 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 964} 965DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 966 967/* 968 * CardBus controllers have a legacy base address that enables them 969 * to respond as i82365 pcmcia controllers. We don't want them to 970 * do this even if the Linux CardBus driver is not loaded, because 971 * the Linux i82365 driver does not (and should not) handle CardBus. 972 */ 973static void quirk_cardbus_legacy(struct pci_dev *dev) 974{ 975 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 976} 977DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 978 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 979DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 980 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 981 982/* 983 * Following the PCI ordering rules is optional on the AMD762. I'm not 984 * sure what the designers were smoking but let's not inhale... 985 * 986 * To be fair to AMD, it follows the spec by default, its BIOS people 987 * who turn it off! 988 */ 989static void quirk_amd_ordering(struct pci_dev *dev) 990{ 991 u32 pcic; 992 pci_read_config_dword(dev, 0x4C, &pcic); 993 if ((pcic & 6) != 6) { 994 pcic |= 6; 995 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 996 pci_write_config_dword(dev, 0x4C, pcic); 997 pci_read_config_dword(dev, 0x84, &pcic); 998 pcic |= (1 << 23); /* Required in this mode */ 999 pci_write_config_dword(dev, 0x84, pcic); 1000 } 1001} 1002DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1003DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1004 1005/* 1006 * DreamWorks provided workaround for Dunord I-3000 problem 1007 * 1008 * This card decodes and responds to addresses not apparently 1009 * assigned to it. We force a larger allocation to ensure that 1010 * nothing gets put too close to it. 1011 */ 1012static void quirk_dunord(struct pci_dev *dev) 1013{ 1014 struct resource *r = &dev->resource[1]; 1015 1016 r->flags |= IORESOURCE_UNSET; 1017 r->start = 0; 1018 r->end = 0xffffff; 1019} 1020DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1021 1022/* 1023 * i82380FB mobile docking controller: its PCI-to-PCI bridge 1024 * is subtractive decoding (transparent), and does indicate this 1025 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 1026 * instead of 0x01. 1027 */ 1028static void quirk_transparent_bridge(struct pci_dev *dev) 1029{ 1030 dev->transparent = 1; 1031} 1032DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1033DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1034 1035/* 1036 * Common misconfiguration of the MediaGX/Geode PCI master that will 1037 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 1038 * datasheets found at http://www.national.com/analog for info on what 1039 * these bits do. <christer@weinigel.se> 1040 */ 1041static void quirk_mediagx_master(struct pci_dev *dev) 1042{ 1043 u8 reg; 1044 1045 pci_read_config_byte(dev, 0x41, ®); 1046 if (reg & 2) { 1047 reg &= ~2; 1048 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1049 reg); 1050 pci_write_config_byte(dev, 0x41, reg); 1051 } 1052} 1053DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1054DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1055 1056/* 1057 * Ensure C0 rev restreaming is off. This is normally done by 1058 * the BIOS but in the odd case it is not the results are corruption 1059 * hence the presence of a Linux check 1060 */ 1061static void quirk_disable_pxb(struct pci_dev *pdev) 1062{ 1063 u16 config; 1064 1065 if (pdev->revision != 0x04) /* Only C0 requires this */ 1066 return; 1067 pci_read_config_word(pdev, 0x40, &config); 1068 if (config & (1<<6)) { 1069 config &= ~(1<<6); 1070 pci_write_config_word(pdev, 0x40, config); 1071 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1072 } 1073} 1074DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1075DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1076 1077static void quirk_amd_ide_mode(struct pci_dev *pdev) 1078{ 1079 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1080 u8 tmp; 1081 1082 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1083 if (tmp == 0x01) { 1084 pci_read_config_byte(pdev, 0x40, &tmp); 1085 pci_write_config_byte(pdev, 0x40, tmp|1); 1086 pci_write_config_byte(pdev, 0x9, 1); 1087 pci_write_config_byte(pdev, 0xa, 6); 1088 pci_write_config_byte(pdev, 0x40, tmp); 1089 1090 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1091 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 1092 } 1093} 1094DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1095DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1096DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1097DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1098DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1099DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1100DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1101DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1102 1103/* 1104 * Serverworks CSB5 IDE does not fully support native mode 1105 */ 1106static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1107{ 1108 u8 prog; 1109 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1110 if (prog & 5) { 1111 prog &= ~5; 1112 pdev->class &= ~5; 1113 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1114 /* PCI layer will sort out resources */ 1115 } 1116} 1117DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1118 1119/* 1120 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1121 */ 1122static void quirk_ide_samemode(struct pci_dev *pdev) 1123{ 1124 u8 prog; 1125 1126 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1127 1128 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1129 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 1130 prog &= ~5; 1131 pdev->class &= ~5; 1132 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1133 } 1134} 1135DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1136 1137/* 1138 * Some ATA devices break if put into D3 1139 */ 1140 1141static void quirk_no_ata_d3(struct pci_dev *pdev) 1142{ 1143 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1144} 1145/* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1146DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1147 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1148DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1149 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1150/* ALi loses some register settings that we cannot then restore */ 1151DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1152 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1153/* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1154 occur when mode detecting */ 1155DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1156 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1157 1158/* This was originally an Alpha specific thing, but it really fits here. 1159 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1160 */ 1161static void quirk_eisa_bridge(struct pci_dev *dev) 1162{ 1163 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1164} 1165DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1166 1167 1168/* 1169 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1170 * is not activated. The myth is that Asus said that they do not want the 1171 * users to be irritated by just another PCI Device in the Win98 device 1172 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1173 * package 2.7.0 for details) 1174 * 1175 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1176 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1177 * becomes necessary to do this tweak in two steps -- the chosen trigger 1178 * is either the Host bridge (preferred) or on-board VGA controller. 1179 * 1180 * Note that we used to unhide the SMBus that way on Toshiba laptops 1181 * (Satellite A40 and Tecra M2) but then found that the thermal management 1182 * was done by SMM code, which could cause unsynchronized concurrent 1183 * accesses to the SMBus registers, with potentially bad effects. Thus you 1184 * should be very careful when adding new entries: if SMM is accessing the 1185 * Intel SMBus, this is a very good reason to leave it hidden. 1186 * 1187 * Likewise, many recent laptops use ACPI for thermal management. If the 1188 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1189 * natively, and keeping the SMBus hidden is the right thing to do. If you 1190 * are about to add an entry in the table below, please first disassemble 1191 * the DSDT and double-check that there is no code accessing the SMBus. 1192 */ 1193static int asus_hides_smbus; 1194 1195static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1196{ 1197 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1198 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1199 switch (dev->subsystem_device) { 1200 case 0x8025: /* P4B-LX */ 1201 case 0x8070: /* P4B */ 1202 case 0x8088: /* P4B533 */ 1203 case 0x1626: /* L3C notebook */ 1204 asus_hides_smbus = 1; 1205 } 1206 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1207 switch (dev->subsystem_device) { 1208 case 0x80b1: /* P4GE-V */ 1209 case 0x80b2: /* P4PE */ 1210 case 0x8093: /* P4B533-V */ 1211 asus_hides_smbus = 1; 1212 } 1213 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1214 switch (dev->subsystem_device) { 1215 case 0x8030: /* P4T533 */ 1216 asus_hides_smbus = 1; 1217 } 1218 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1219 switch (dev->subsystem_device) { 1220 case 0x8070: /* P4G8X Deluxe */ 1221 asus_hides_smbus = 1; 1222 } 1223 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1224 switch (dev->subsystem_device) { 1225 case 0x80c9: /* PU-DLS */ 1226 asus_hides_smbus = 1; 1227 } 1228 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1229 switch (dev->subsystem_device) { 1230 case 0x1751: /* M2N notebook */ 1231 case 0x1821: /* M5N notebook */ 1232 case 0x1897: /* A6L notebook */ 1233 asus_hides_smbus = 1; 1234 } 1235 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1236 switch (dev->subsystem_device) { 1237 case 0x184b: /* W1N notebook */ 1238 case 0x186a: /* M6Ne notebook */ 1239 asus_hides_smbus = 1; 1240 } 1241 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1242 switch (dev->subsystem_device) { 1243 case 0x80f2: /* P4P800-X */ 1244 asus_hides_smbus = 1; 1245 } 1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1247 switch (dev->subsystem_device) { 1248 case 0x1882: /* M6V notebook */ 1249 case 0x1977: /* A6VA notebook */ 1250 asus_hides_smbus = 1; 1251 } 1252 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1253 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1254 switch (dev->subsystem_device) { 1255 case 0x088C: /* HP Compaq nc8000 */ 1256 case 0x0890: /* HP Compaq nc6000 */ 1257 asus_hides_smbus = 1; 1258 } 1259 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1260 switch (dev->subsystem_device) { 1261 case 0x12bc: /* HP D330L */ 1262 case 0x12bd: /* HP D530 */ 1263 case 0x006a: /* HP Compaq nx9500 */ 1264 asus_hides_smbus = 1; 1265 } 1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1267 switch (dev->subsystem_device) { 1268 case 0x12bf: /* HP xw4100 */ 1269 asus_hides_smbus = 1; 1270 } 1271 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1272 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1273 switch (dev->subsystem_device) { 1274 case 0xC00C: /* Samsung P35 notebook */ 1275 asus_hides_smbus = 1; 1276 } 1277 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1278 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1279 switch (dev->subsystem_device) { 1280 case 0x0058: /* Compaq Evo N620c */ 1281 asus_hides_smbus = 1; 1282 } 1283 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1284 switch (dev->subsystem_device) { 1285 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1286 /* Motherboard doesn't have Host bridge 1287 * subvendor/subdevice IDs, therefore checking 1288 * its on-board VGA controller */ 1289 asus_hides_smbus = 1; 1290 } 1291 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1292 switch (dev->subsystem_device) { 1293 case 0x00b8: /* Compaq Evo D510 CMT */ 1294 case 0x00b9: /* Compaq Evo D510 SFF */ 1295 case 0x00ba: /* Compaq Evo D510 USDT */ 1296 /* Motherboard doesn't have Host bridge 1297 * subvendor/subdevice IDs and on-board VGA 1298 * controller is disabled if an AGP card is 1299 * inserted, therefore checking USB UHCI 1300 * Controller #1 */ 1301 asus_hides_smbus = 1; 1302 } 1303 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1304 switch (dev->subsystem_device) { 1305 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1306 /* Motherboard doesn't have host bridge 1307 * subvendor/subdevice IDs, therefore checking 1308 * its on-board VGA controller */ 1309 asus_hides_smbus = 1; 1310 } 1311 } 1312} 1313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1314DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1315DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1316DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1317DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1318DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1323 1324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1327 1328static void asus_hides_smbus_lpc(struct pci_dev *dev) 1329{ 1330 u16 val; 1331 1332 if (likely(!asus_hides_smbus)) 1333 return; 1334 1335 pci_read_config_word(dev, 0xF2, &val); 1336 if (val & 0x8) { 1337 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1338 pci_read_config_word(dev, 0xF2, &val); 1339 if (val & 0x8) 1340 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1341 val); 1342 else 1343 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1344 } 1345} 1346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1347DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1348DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1349DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1350DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1351DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1352DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1353DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1354DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1355DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1356DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1357DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1358DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1359DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1360 1361/* It appears we just have one such device. If not, we have a warning */ 1362static void __iomem *asus_rcba_base; 1363static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1364{ 1365 u32 rcba; 1366 1367 if (likely(!asus_hides_smbus)) 1368 return; 1369 WARN_ON(asus_rcba_base); 1370 1371 pci_read_config_dword(dev, 0xF0, &rcba); 1372 /* use bits 31:14, 16 kB aligned */ 1373 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1374 if (asus_rcba_base == NULL) 1375 return; 1376} 1377 1378static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1379{ 1380 u32 val; 1381 1382 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1383 return; 1384 /* read the Function Disable register, dword mode only */ 1385 val = readl(asus_rcba_base + 0x3418); 1386 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1387} 1388 1389static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1390{ 1391 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1392 return; 1393 iounmap(asus_rcba_base); 1394 asus_rcba_base = NULL; 1395 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1396} 1397 1398static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1399{ 1400 asus_hides_smbus_lpc_ich6_suspend(dev); 1401 asus_hides_smbus_lpc_ich6_resume_early(dev); 1402 asus_hides_smbus_lpc_ich6_resume(dev); 1403} 1404DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1405DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1406DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1407DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1408 1409/* 1410 * SiS 96x south bridge: BIOS typically hides SMBus device... 1411 */ 1412static void quirk_sis_96x_smbus(struct pci_dev *dev) 1413{ 1414 u8 val = 0; 1415 pci_read_config_byte(dev, 0x77, &val); 1416 if (val & 0x10) { 1417 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1418 pci_write_config_byte(dev, 0x77, val & ~0x10); 1419 } 1420} 1421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1422DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1424DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1425DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1426DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1427DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1428DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1429 1430/* 1431 * ... This is further complicated by the fact that some SiS96x south 1432 * bridges pretend to be 85C503/5513 instead. In that case see if we 1433 * spotted a compatible north bridge to make sure. 1434 * (pci_find_device doesn't work yet) 1435 * 1436 * We can also enable the sis96x bit in the discovery register.. 1437 */ 1438#define SIS_DETECT_REGISTER 0x40 1439 1440static void quirk_sis_503(struct pci_dev *dev) 1441{ 1442 u8 reg; 1443 u16 devid; 1444 1445 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1446 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1447 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1448 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1449 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1450 return; 1451 } 1452 1453 /* 1454 * Ok, it now shows up as a 96x.. run the 96x quirk by 1455 * hand in case it has already been processed. 1456 * (depends on link order, which is apparently not guaranteed) 1457 */ 1458 dev->device = devid; 1459 quirk_sis_96x_smbus(dev); 1460} 1461DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1462DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1463 1464 1465/* 1466 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1467 * and MC97 modem controller are disabled when a second PCI soundcard is 1468 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1469 * -- bjd 1470 */ 1471static void asus_hides_ac97_lpc(struct pci_dev *dev) 1472{ 1473 u8 val; 1474 int asus_hides_ac97 = 0; 1475 1476 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1477 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1478 asus_hides_ac97 = 1; 1479 } 1480 1481 if (!asus_hides_ac97) 1482 return; 1483 1484 pci_read_config_byte(dev, 0x50, &val); 1485 if (val & 0xc0) { 1486 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1487 pci_read_config_byte(dev, 0x50, &val); 1488 if (val & 0xc0) 1489 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1490 val); 1491 else 1492 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1493 } 1494} 1495DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1496DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1497 1498#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1499 1500/* 1501 * If we are using libata we can drive this chip properly but must 1502 * do this early on to make the additional device appear during 1503 * the PCI scanning. 1504 */ 1505static void quirk_jmicron_ata(struct pci_dev *pdev) 1506{ 1507 u32 conf1, conf5, class; 1508 u8 hdr; 1509 1510 /* Only poke fn 0 */ 1511 if (PCI_FUNC(pdev->devfn)) 1512 return; 1513 1514 pci_read_config_dword(pdev, 0x40, &conf1); 1515 pci_read_config_dword(pdev, 0x80, &conf5); 1516 1517 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1518 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1519 1520 switch (pdev->device) { 1521 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1522 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1523 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1524 /* The controller should be in single function ahci mode */ 1525 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1526 break; 1527 1528 case PCI_DEVICE_ID_JMICRON_JMB365: 1529 case PCI_DEVICE_ID_JMICRON_JMB366: 1530 /* Redirect IDE second PATA port to the right spot */ 1531 conf5 |= (1 << 24); 1532 /* Fall through */ 1533 case PCI_DEVICE_ID_JMICRON_JMB361: 1534 case PCI_DEVICE_ID_JMICRON_JMB363: 1535 case PCI_DEVICE_ID_JMICRON_JMB369: 1536 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1537 /* Set the class codes correctly and then direct IDE 0 */ 1538 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1539 break; 1540 1541 case PCI_DEVICE_ID_JMICRON_JMB368: 1542 /* The controller should be in single function IDE mode */ 1543 conf1 |= 0x00C00000; /* Set 22, 23 */ 1544 break; 1545 } 1546 1547 pci_write_config_dword(pdev, 0x40, conf1); 1548 pci_write_config_dword(pdev, 0x80, conf5); 1549 1550 /* Update pdev accordingly */ 1551 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1552 pdev->hdr_type = hdr & 0x7f; 1553 pdev->multifunction = !!(hdr & 0x80); 1554 1555 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1556 pdev->class = class >> 8; 1557} 1558DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1559DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1560DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1561DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1562DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1563DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1564DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1565DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1566DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1567DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1568DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1569DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1570DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1571DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1572DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1573DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1574DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1575DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1576 1577#endif 1578 1579static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1580{ 1581 if (dev->multifunction) { 1582 device_disable_async_suspend(&dev->dev); 1583 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1584 } 1585} 1586DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1587DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1589DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1590 1591#ifdef CONFIG_X86_IO_APIC 1592static void quirk_alder_ioapic(struct pci_dev *pdev) 1593{ 1594 int i; 1595 1596 if ((pdev->class >> 8) != 0xff00) 1597 return; 1598 1599 /* the first BAR is the location of the IO APIC...we must 1600 * not touch this (and it's already covered by the fixmap), so 1601 * forcibly insert it into the resource tree */ 1602 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1603 insert_resource(&iomem_resource, &pdev->resource[0]); 1604 1605 /* The next five BARs all seem to be rubbish, so just clean 1606 * them out */ 1607 for (i = 1; i < 6; i++) 1608 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1609} 1610DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1611#endif 1612 1613static void quirk_pcie_mch(struct pci_dev *pdev) 1614{ 1615 pci_msi_off(pdev); 1616 pdev->no_msi = 1; 1617} 1618DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1621 1622 1623/* 1624 * It's possible for the MSI to get corrupted if shpc and acpi 1625 * are used together on certain PXH-based systems. 1626 */ 1627static void quirk_pcie_pxh(struct pci_dev *dev) 1628{ 1629 pci_msi_off(dev); 1630 dev->no_msi = 1; 1631 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1632} 1633DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1634DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1635DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1636DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1637DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1638 1639/* 1640 * Some Intel PCI Express chipsets have trouble with downstream 1641 * device power management. 1642 */ 1643static void quirk_intel_pcie_pm(struct pci_dev *dev) 1644{ 1645 pci_pm_d3_delay = 120; 1646 dev->no_d1d2 = 1; 1647} 1648 1649DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1650DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1651DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1652DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1654DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1655DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1659DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1660DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1661DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1662DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1670 1671#ifdef CONFIG_X86_IO_APIC 1672/* 1673 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1674 * remap the original interrupt in the linux kernel to the boot interrupt, so 1675 * that a PCI device's interrupt handler is installed on the boot interrupt 1676 * line instead. 1677 */ 1678static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1679{ 1680 if (noioapicquirk || noioapicreroute) 1681 return; 1682 1683 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1684 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", 1685 dev->vendor, dev->device); 1686} 1687DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1688DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1689DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1690DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1691DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1692DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1693DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1694DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1695DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1696DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1697DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1698DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1699DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1700DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1701DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1702DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1703 1704/* 1705 * On some chipsets we can disable the generation of legacy INTx boot 1706 * interrupts. 1707 */ 1708 1709/* 1710 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1711 * 300641-004US, section 5.7.3. 1712 */ 1713#define INTEL_6300_IOAPIC_ABAR 0x40 1714#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1715 1716static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1717{ 1718 u16 pci_config_word; 1719 1720 if (noioapicquirk) 1721 return; 1722 1723 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1724 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1725 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1726 1727 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1728 dev->vendor, dev->device); 1729} 1730DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1731DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1732 1733/* 1734 * disable boot interrupts on HT-1000 1735 */ 1736#define BC_HT1000_FEATURE_REG 0x64 1737#define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1738#define BC_HT1000_MAP_IDX 0xC00 1739#define BC_HT1000_MAP_DATA 0xC01 1740 1741static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1742{ 1743 u32 pci_config_dword; 1744 u8 irq; 1745 1746 if (noioapicquirk) 1747 return; 1748 1749 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1750 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1751 BC_HT1000_PIC_REGS_ENABLE); 1752 1753 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1754 outb(irq, BC_HT1000_MAP_IDX); 1755 outb(0x00, BC_HT1000_MAP_DATA); 1756 } 1757 1758 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1759 1760 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1761 dev->vendor, dev->device); 1762} 1763DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1764DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1765 1766/* 1767 * disable boot interrupts on AMD and ATI chipsets 1768 */ 1769/* 1770 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1771 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1772 * (due to an erratum). 1773 */ 1774#define AMD_813X_MISC 0x40 1775#define AMD_813X_NOIOAMODE (1<<0) 1776#define AMD_813X_REV_B1 0x12 1777#define AMD_813X_REV_B2 0x13 1778 1779static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1780{ 1781 u32 pci_config_dword; 1782 1783 if (noioapicquirk) 1784 return; 1785 if ((dev->revision == AMD_813X_REV_B1) || 1786 (dev->revision == AMD_813X_REV_B2)) 1787 return; 1788 1789 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1790 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1791 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1792 1793 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1794 dev->vendor, dev->device); 1795} 1796DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1797DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1798DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1799DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1800 1801#define AMD_8111_PCI_IRQ_ROUTING 0x56 1802 1803static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 1804{ 1805 u16 pci_config_word; 1806 1807 if (noioapicquirk) 1808 return; 1809 1810 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1811 if (!pci_config_word) { 1812 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n", 1813 dev->vendor, dev->device); 1814 return; 1815 } 1816 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1817 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1818 dev->vendor, dev->device); 1819} 1820DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1821DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1822#endif /* CONFIG_X86_IO_APIC */ 1823 1824/* 1825 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1826 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1827 * Re-allocate the region if needed... 1828 */ 1829static void quirk_tc86c001_ide(struct pci_dev *dev) 1830{ 1831 struct resource *r = &dev->resource[0]; 1832 1833 if (r->start & 0x8) { 1834 r->flags |= IORESOURCE_UNSET; 1835 r->start = 0; 1836 r->end = 0xf; 1837 } 1838} 1839DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1840 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1841 quirk_tc86c001_ide); 1842 1843/* 1844 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the 1845 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 1846 * being read correctly if bit 7 of the base address is set. 1847 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 1848 * Re-allocate the regions to a 256-byte boundary if necessary. 1849 */ 1850static void quirk_plx_pci9050(struct pci_dev *dev) 1851{ 1852 unsigned int bar; 1853 1854 /* Fixed in revision 2 (PCI 9052). */ 1855 if (dev->revision >= 2) 1856 return; 1857 for (bar = 0; bar <= 1; bar++) 1858 if (pci_resource_len(dev, bar) == 0x80 && 1859 (pci_resource_start(dev, bar) & 0x80)) { 1860 struct resource *r = &dev->resource[bar]; 1861 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 1862 bar); 1863 r->flags |= IORESOURCE_UNSET; 1864 r->start = 0; 1865 r->end = 0xff; 1866 } 1867} 1868DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 1869 quirk_plx_pci9050); 1870/* 1871 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 1872 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 1873 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 1874 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 1875 * 1876 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 1877 * driver. 1878 */ 1879DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 1880DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 1881 1882static void quirk_netmos(struct pci_dev *dev) 1883{ 1884 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1885 unsigned int num_serial = dev->subsystem_device & 0xf; 1886 1887 /* 1888 * These Netmos parts are multiport serial devices with optional 1889 * parallel ports. Even when parallel ports are present, they 1890 * are identified as class SERIAL, which means the serial driver 1891 * will claim them. To prevent this, mark them as class OTHER. 1892 * These combo devices should be claimed by parport_serial. 1893 * 1894 * The subdevice ID is of the form 0x00PS, where <P> is the number 1895 * of parallel ports and <S> is the number of serial ports. 1896 */ 1897 switch (dev->device) { 1898 case PCI_DEVICE_ID_NETMOS_9835: 1899 /* Well, this rule doesn't hold for the following 9835 device */ 1900 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 1901 dev->subsystem_device == 0x0299) 1902 return; 1903 case PCI_DEVICE_ID_NETMOS_9735: 1904 case PCI_DEVICE_ID_NETMOS_9745: 1905 case PCI_DEVICE_ID_NETMOS_9845: 1906 case PCI_DEVICE_ID_NETMOS_9855: 1907 if (num_parallel) { 1908 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 1909 dev->device, num_parallel, num_serial); 1910 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1911 (dev->class & 0xff); 1912 } 1913 } 1914} 1915DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 1916 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 1917 1918/* 1919 * Quirk non-zero PCI functions to route VPD access through function 0 for 1920 * devices that share VPD resources between functions. The functions are 1921 * expected to be identical devices. 1922 */ 1923static void quirk_f0_vpd_link(struct pci_dev *dev) 1924{ 1925 struct pci_dev *f0; 1926 1927 if (!PCI_FUNC(dev->devfn)) 1928 return; 1929 1930 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 1931 if (!f0) 1932 return; 1933 1934 if (f0->vpd && dev->class == f0->class && 1935 dev->vendor == f0->vendor && dev->device == f0->device) 1936 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0; 1937 1938 pci_dev_put(f0); 1939} 1940DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 1941 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link); 1942 1943static void quirk_e100_interrupt(struct pci_dev *dev) 1944{ 1945 u16 command, pmcsr; 1946 u8 __iomem *csr; 1947 u8 cmd_hi; 1948 1949 switch (dev->device) { 1950 /* PCI IDs taken from drivers/net/e100.c */ 1951 case 0x1029: 1952 case 0x1030 ... 0x1034: 1953 case 0x1038 ... 0x103E: 1954 case 0x1050 ... 0x1057: 1955 case 0x1059: 1956 case 0x1064 ... 0x106B: 1957 case 0x1091 ... 0x1095: 1958 case 0x1209: 1959 case 0x1229: 1960 case 0x2449: 1961 case 0x2459: 1962 case 0x245D: 1963 case 0x27DC: 1964 break; 1965 default: 1966 return; 1967 } 1968 1969 /* 1970 * Some firmware hands off the e100 with interrupts enabled, 1971 * which can cause a flood of interrupts if packets are 1972 * received before the driver attaches to the device. So 1973 * disable all e100 interrupts here. The driver will 1974 * re-enable them when it's ready. 1975 */ 1976 pci_read_config_word(dev, PCI_COMMAND, &command); 1977 1978 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 1979 return; 1980 1981 /* 1982 * Check that the device is in the D0 power state. If it's not, 1983 * there is no point to look any further. 1984 */ 1985 if (dev->pm_cap) { 1986 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1987 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 1988 return; 1989 } 1990 1991 /* Convert from PCI bus to resource space. */ 1992 csr = ioremap(pci_resource_start(dev, 0), 8); 1993 if (!csr) { 1994 dev_warn(&dev->dev, "Can't map e100 registers\n"); 1995 return; 1996 } 1997 1998 cmd_hi = readb(csr + 3); 1999 if (cmd_hi == 0) { 2000 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n"); 2001 writeb(1, csr + 3); 2002 } 2003 2004 iounmap(csr); 2005} 2006DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2007 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2008 2009/* 2010 * The 82575 and 82598 may experience data corruption issues when transitioning 2011 * out of L0S. To prevent this we need to disable L0S on the pci-e link 2012 */ 2013static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2014{ 2015 dev_info(&dev->dev, "Disabling L0s\n"); 2016 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2017} 2018DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2019DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2020DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2021DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2022DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2023DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2024DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2025DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2026DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2027DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2028DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2029DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2030DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2031DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2032 2033static void fixup_rev1_53c810(struct pci_dev *dev) 2034{ 2035 /* rev 1 ncr53c810 chips don't set the class at all which means 2036 * they don't get their resources remapped. Fix that here. 2037 */ 2038 2039 if (dev->class == PCI_CLASS_NOT_DEFINED) { 2040 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); 2041 dev->class = PCI_CLASS_STORAGE_SCSI; 2042 } 2043} 2044DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2045 2046/* Enable 1k I/O space granularity on the Intel P64H2 */ 2047static void quirk_p64h2_1k_io(struct pci_dev *dev) 2048{ 2049 u16 en1k; 2050 2051 pci_read_config_word(dev, 0x40, &en1k); 2052 2053 if (en1k & 0x200) { 2054 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 2055 dev->io_window_1k = 1; 2056 } 2057} 2058DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2059 2060/* Under some circumstances, AER is not linked with extended capabilities. 2061 * Force it to be linked by setting the corresponding control bit in the 2062 * config space. 2063 */ 2064static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2065{ 2066 uint8_t b; 2067 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2068 if (!(b & 0x20)) { 2069 pci_write_config_byte(dev, 0xf41, b | 0x20); 2070 dev_info(&dev->dev, "Linking AER extended capability\n"); 2071 } 2072 } 2073} 2074DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2075 quirk_nvidia_ck804_pcie_aer_ext_cap); 2076DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2077 quirk_nvidia_ck804_pcie_aer_ext_cap); 2078 2079static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2080{ 2081 /* 2082 * Disable PCI Bus Parking and PCI Master read caching on CX700 2083 * which causes unspecified timing errors with a VT6212L on the PCI 2084 * bus leading to USB2.0 packet loss. 2085 * 2086 * This quirk is only enabled if a second (on the external PCI bus) 2087 * VT6212L is found -- the CX700 core itself also contains a USB 2088 * host controller with the same PCI ID as the VT6212L. 2089 */ 2090 2091 /* Count VT6212L instances */ 2092 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2093 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2094 uint8_t b; 2095 2096 /* p should contain the first (internal) VT6212L -- see if we have 2097 an external one by searching again */ 2098 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2099 if (!p) 2100 return; 2101 pci_dev_put(p); 2102 2103 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2104 if (b & 0x40) { 2105 /* Turn off PCI Bus Parking */ 2106 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2107 2108 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n"); 2109 } 2110 } 2111 2112 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2113 if (b != 0) { 2114 /* Turn off PCI Master read caching */ 2115 pci_write_config_byte(dev, 0x72, 0x0); 2116 2117 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2118 pci_write_config_byte(dev, 0x75, 0x1); 2119 2120 /* Disable "Read FIFO Timer" */ 2121 pci_write_config_byte(dev, 0x77, 0x0); 2122 2123 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n"); 2124 } 2125 } 2126} 2127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2128 2129/* 2130 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 2131 * VPD end tag will hang the device. This problem was initially 2132 * observed when a vpd entry was created in sysfs 2133 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 2134 * will dump 32k of data. Reading a full 32k will cause an access 2135 * beyond the VPD end tag causing the device to hang. Once the device 2136 * is hung, the bnx2 driver will not be able to reset the device. 2137 * We believe that it is legal to read beyond the end tag and 2138 * therefore the solution is to limit the read/write length. 2139 */ 2140static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 2141{ 2142 /* 2143 * Only disable the VPD capability for 5706, 5706S, 5708, 2144 * 5708S and 5709 rev. A 2145 */ 2146 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 2147 (dev->device == PCI_DEVICE_ID_NX2_5706S) || 2148 (dev->device == PCI_DEVICE_ID_NX2_5708) || 2149 (dev->device == PCI_DEVICE_ID_NX2_5708S) || 2150 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 2151 (dev->revision & 0xf0) == 0x0)) { 2152 if (dev->vpd) 2153 dev->vpd->len = 0x80; 2154 } 2155} 2156 2157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2158 PCI_DEVICE_ID_NX2_5706, 2159 quirk_brcm_570x_limit_vpd); 2160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2161 PCI_DEVICE_ID_NX2_5706S, 2162 quirk_brcm_570x_limit_vpd); 2163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2164 PCI_DEVICE_ID_NX2_5708, 2165 quirk_brcm_570x_limit_vpd); 2166DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2167 PCI_DEVICE_ID_NX2_5708S, 2168 quirk_brcm_570x_limit_vpd); 2169DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2170 PCI_DEVICE_ID_NX2_5709, 2171 quirk_brcm_570x_limit_vpd); 2172DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2173 PCI_DEVICE_ID_NX2_5709S, 2174 quirk_brcm_570x_limit_vpd); 2175 2176static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2177{ 2178 u32 rev; 2179 2180 pci_read_config_dword(dev, 0xf4, &rev); 2181 2182 /* Only CAP the MRRS if the device is a 5719 A0 */ 2183 if (rev == 0x05719000) { 2184 int readrq = pcie_get_readrq(dev); 2185 if (readrq > 2048) 2186 pcie_set_readrq(dev, 2048); 2187 } 2188} 2189 2190DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2191 PCI_DEVICE_ID_TIGON3_5719, 2192 quirk_brcm_5719_limit_mrrs); 2193 2194/* Originally in EDAC sources for i82875P: 2195 * Intel tells BIOS developers to hide device 6 which 2196 * configures the overflow device access containing 2197 * the DRBs - this is where we expose device 6. 2198 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2199 */ 2200static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2201{ 2202 u8 reg; 2203 2204 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2205 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); 2206 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2207 } 2208} 2209 2210DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2211 quirk_unhide_mch_dev6); 2212DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2213 quirk_unhide_mch_dev6); 2214 2215#ifdef CONFIG_TILEPRO 2216/* 2217 * The Tilera TILEmpower tilepro platform needs to set the link speed 2218 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed 2219 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe 2220 * capability register of the PEX8624 PCIe switch. The switch 2221 * supports link speed auto negotiation, but falsely sets 2222 * the link speed to 5GT/s. 2223 */ 2224static void quirk_tile_plx_gen1(struct pci_dev *dev) 2225{ 2226 if (tile_plx_gen1) { 2227 pci_write_config_dword(dev, 0x98, 0x1); 2228 mdelay(50); 2229 } 2230} 2231DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); 2232#endif /* CONFIG_TILEPRO */ 2233 2234#ifdef CONFIG_PCI_MSI 2235/* Some chipsets do not support MSI. We cannot easily rely on setting 2236 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2237 * some other buses controlled by the chipset even if Linux is not 2238 * aware of it. Instead of setting the flag on all buses in the 2239 * machine, simply disable MSI globally. 2240 */ 2241static void quirk_disable_all_msi(struct pci_dev *dev) 2242{ 2243 pci_no_msi(); 2244 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2245} 2246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2247DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2249DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2250DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2251DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2252DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2253 2254/* Disable MSI on chipsets that are known to not support it */ 2255static void quirk_disable_msi(struct pci_dev *dev) 2256{ 2257 if (dev->subordinate) { 2258 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2259 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2260 } 2261} 2262DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2265 2266/* 2267 * The APC bridge device in AMD 780 family northbridges has some random 2268 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2269 * we use the possible vendor/device IDs of the host bridge for the 2270 * declared quirk, and search for the APC bridge by slot number. 2271 */ 2272static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2273{ 2274 struct pci_dev *apc_bridge; 2275 2276 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2277 if (apc_bridge) { 2278 if (apc_bridge->device == 0x9602) 2279 quirk_disable_msi(apc_bridge); 2280 pci_dev_put(apc_bridge); 2281 } 2282} 2283DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2284DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2285 2286/* Go through the list of Hypertransport capabilities and 2287 * return 1 if a HT MSI capability is found and enabled */ 2288static int msi_ht_cap_enabled(struct pci_dev *dev) 2289{ 2290 int pos, ttl = 48; 2291 2292 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2293 while (pos && ttl--) { 2294 u8 flags; 2295 2296 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2297 &flags) == 0) { 2298 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 2299 flags & HT_MSI_FLAGS_ENABLE ? 2300 "enabled" : "disabled"); 2301 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2302 } 2303 2304 pos = pci_find_next_ht_capability(dev, pos, 2305 HT_CAPTYPE_MSI_MAPPING); 2306 } 2307 return 0; 2308} 2309 2310/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2311static void quirk_msi_ht_cap(struct pci_dev *dev) 2312{ 2313 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2314 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2315 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2316 } 2317} 2318DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2319 quirk_msi_ht_cap); 2320 2321/* The nVidia CK804 chipset may have 2 HT MSI mappings. 2322 * MSI are supported if the MSI capability set in any of these mappings. 2323 */ 2324static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2325{ 2326 struct pci_dev *pdev; 2327 2328 if (!dev->subordinate) 2329 return; 2330 2331 /* check HT MSI cap on this chipset and the root one. 2332 * a single one having MSI is enough to be sure that MSI are supported. 2333 */ 2334 pdev = pci_get_slot(dev->bus, 0); 2335 if (!pdev) 2336 return; 2337 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2338 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); 2339 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2340 } 2341 pci_dev_put(pdev); 2342} 2343DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2344 quirk_nvidia_ck804_msi_ht_cap); 2345 2346/* Force enable MSI mapping capability on HT bridges */ 2347static void ht_enable_msi_mapping(struct pci_dev *dev) 2348{ 2349 int pos, ttl = 48; 2350 2351 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2352 while (pos && ttl--) { 2353 u8 flags; 2354 2355 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2356 &flags) == 0) { 2357 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2358 2359 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2360 flags | HT_MSI_FLAGS_ENABLE); 2361 } 2362 pos = pci_find_next_ht_capability(dev, pos, 2363 HT_CAPTYPE_MSI_MAPPING); 2364 } 2365} 2366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2367 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2368 ht_enable_msi_mapping); 2369 2370DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2371 ht_enable_msi_mapping); 2372 2373/* The P5N32-SLI motherboards from Asus have a problem with msi 2374 * for the MCP55 NIC. It is not yet determined whether the msi problem 2375 * also affects other devices. As for now, turn off msi for this device. 2376 */ 2377static void nvenet_msi_disable(struct pci_dev *dev) 2378{ 2379 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2380 2381 if (board_name && 2382 (strstr(board_name, "P5N32-SLI PREMIUM") || 2383 strstr(board_name, "P5N32-E SLI"))) { 2384 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n"); 2385 dev->no_msi = 1; 2386 } 2387} 2388DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2389 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2390 nvenet_msi_disable); 2391 2392/* 2393 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2394 * config register. This register controls the routing of legacy 2395 * interrupts from devices that route through the MCP55. If this register 2396 * is misprogrammed, interrupts are only sent to the BSP, unlike 2397 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2398 * having this register set properly prevents kdump from booting up 2399 * properly, so let's make sure that we have it set correctly. 2400 * Note that this is an undocumented register. 2401 */ 2402static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2403{ 2404 u32 cfg; 2405 2406 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2407 return; 2408 2409 pci_read_config_dword(dev, 0x74, &cfg); 2410 2411 if (cfg & ((1 << 2) | (1 << 15))) { 2412 printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); 2413 cfg &= ~((1 << 2) | (1 << 15)); 2414 pci_write_config_dword(dev, 0x74, cfg); 2415 } 2416} 2417 2418DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2419 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2420 nvbridge_check_legacy_irq_routing); 2421 2422DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2423 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2424 nvbridge_check_legacy_irq_routing); 2425 2426static int ht_check_msi_mapping(struct pci_dev *dev) 2427{ 2428 int pos, ttl = 48; 2429 int found = 0; 2430 2431 /* check if there is HT MSI cap or enabled on this device */ 2432 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2433 while (pos && ttl--) { 2434 u8 flags; 2435 2436 if (found < 1) 2437 found = 1; 2438 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2439 &flags) == 0) { 2440 if (flags & HT_MSI_FLAGS_ENABLE) { 2441 if (found < 2) { 2442 found = 2; 2443 break; 2444 } 2445 } 2446 } 2447 pos = pci_find_next_ht_capability(dev, pos, 2448 HT_CAPTYPE_MSI_MAPPING); 2449 } 2450 2451 return found; 2452} 2453 2454static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2455{ 2456 struct pci_dev *dev; 2457 int pos; 2458 int i, dev_no; 2459 int found = 0; 2460 2461 dev_no = host_bridge->devfn >> 3; 2462 for (i = dev_no + 1; i < 0x20; i++) { 2463 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2464 if (!dev) 2465 continue; 2466 2467 /* found next host bridge ?*/ 2468 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2469 if (pos != 0) { 2470 pci_dev_put(dev); 2471 break; 2472 } 2473 2474 if (ht_check_msi_mapping(dev)) { 2475 found = 1; 2476 pci_dev_put(dev); 2477 break; 2478 } 2479 pci_dev_put(dev); 2480 } 2481 2482 return found; 2483} 2484 2485#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2486#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2487 2488static int is_end_of_ht_chain(struct pci_dev *dev) 2489{ 2490 int pos, ctrl_off; 2491 int end = 0; 2492 u16 flags, ctrl; 2493 2494 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2495 2496 if (!pos) 2497 goto out; 2498 2499 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2500 2501 ctrl_off = ((flags >> 10) & 1) ? 2502 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2503 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2504 2505 if (ctrl & (1 << 6)) 2506 end = 1; 2507 2508out: 2509 return end; 2510} 2511 2512static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2513{ 2514 struct pci_dev *host_bridge; 2515 int pos; 2516 int i, dev_no; 2517 int found = 0; 2518 2519 dev_no = dev->devfn >> 3; 2520 for (i = dev_no; i >= 0; i--) { 2521 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2522 if (!host_bridge) 2523 continue; 2524 2525 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2526 if (pos != 0) { 2527 found = 1; 2528 break; 2529 } 2530 pci_dev_put(host_bridge); 2531 } 2532 2533 if (!found) 2534 return; 2535 2536 /* don't enable end_device/host_bridge with leaf directly here */ 2537 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2538 host_bridge_with_leaf(host_bridge)) 2539 goto out; 2540 2541 /* root did that ! */ 2542 if (msi_ht_cap_enabled(host_bridge)) 2543 goto out; 2544 2545 ht_enable_msi_mapping(dev); 2546 2547out: 2548 pci_dev_put(host_bridge); 2549} 2550 2551static void ht_disable_msi_mapping(struct pci_dev *dev) 2552{ 2553 int pos, ttl = 48; 2554 2555 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2556 while (pos && ttl--) { 2557 u8 flags; 2558 2559 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2560 &flags) == 0) { 2561 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); 2562 2563 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2564 flags & ~HT_MSI_FLAGS_ENABLE); 2565 } 2566 pos = pci_find_next_ht_capability(dev, pos, 2567 HT_CAPTYPE_MSI_MAPPING); 2568 } 2569} 2570 2571static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2572{ 2573 struct pci_dev *host_bridge; 2574 int pos; 2575 int found; 2576 2577 if (!pci_msi_enabled()) 2578 return; 2579 2580 /* check if there is HT MSI cap or enabled on this device */ 2581 found = ht_check_msi_mapping(dev); 2582 2583 /* no HT MSI CAP */ 2584 if (found == 0) 2585 return; 2586 2587 /* 2588 * HT MSI mapping should be disabled on devices that are below 2589 * a non-Hypertransport host bridge. Locate the host bridge... 2590 */ 2591 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2592 if (host_bridge == NULL) { 2593 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2594 return; 2595 } 2596 2597 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2598 if (pos != 0) { 2599 /* Host bridge is to HT */ 2600 if (found == 1) { 2601 /* it is not enabled, try to enable it */ 2602 if (all) 2603 ht_enable_msi_mapping(dev); 2604 else 2605 nv_ht_enable_msi_mapping(dev); 2606 } 2607 goto out; 2608 } 2609 2610 /* HT MSI is not enabled */ 2611 if (found == 1) 2612 goto out; 2613 2614 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2615 ht_disable_msi_mapping(dev); 2616 2617out: 2618 pci_dev_put(host_bridge); 2619} 2620 2621static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2622{ 2623 return __nv_msi_ht_cap_quirk(dev, 1); 2624} 2625 2626static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2627{ 2628 return __nv_msi_ht_cap_quirk(dev, 0); 2629} 2630 2631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2632DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2633 2634DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2635DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2636 2637static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2638{ 2639 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2640} 2641static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2642{ 2643 struct pci_dev *p; 2644 2645 /* SB700 MSI issue will be fixed at HW level from revision A21, 2646 * we need check PCI REVISION ID of SMBus controller to get SB700 2647 * revision. 2648 */ 2649 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2650 NULL); 2651 if (!p) 2652 return; 2653 2654 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2655 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2656 pci_dev_put(p); 2657} 2658static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2659{ 2660 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2661 if (dev->revision < 0x18) { 2662 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n"); 2663 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2664 } 2665} 2666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2667 PCI_DEVICE_ID_TIGON3_5780, 2668 quirk_msi_intx_disable_bug); 2669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2670 PCI_DEVICE_ID_TIGON3_5780S, 2671 quirk_msi_intx_disable_bug); 2672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2673 PCI_DEVICE_ID_TIGON3_5714, 2674 quirk_msi_intx_disable_bug); 2675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2676 PCI_DEVICE_ID_TIGON3_5714S, 2677 quirk_msi_intx_disable_bug); 2678DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2679 PCI_DEVICE_ID_TIGON3_5715, 2680 quirk_msi_intx_disable_bug); 2681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2682 PCI_DEVICE_ID_TIGON3_5715S, 2683 quirk_msi_intx_disable_bug); 2684 2685DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2686 quirk_msi_intx_disable_ati_bug); 2687DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2688 quirk_msi_intx_disable_ati_bug); 2689DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2690 quirk_msi_intx_disable_ati_bug); 2691DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2692 quirk_msi_intx_disable_ati_bug); 2693DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2694 quirk_msi_intx_disable_ati_bug); 2695 2696DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2697 quirk_msi_intx_disable_bug); 2698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2699 quirk_msi_intx_disable_bug); 2700DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2701 quirk_msi_intx_disable_bug); 2702 2703DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 2704 quirk_msi_intx_disable_bug); 2705DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 2706 quirk_msi_intx_disable_bug); 2707DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 2708 quirk_msi_intx_disable_bug); 2709DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 2710 quirk_msi_intx_disable_bug); 2711DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 2712 quirk_msi_intx_disable_bug); 2713DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 2714 quirk_msi_intx_disable_bug); 2715DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 2716 quirk_msi_intx_disable_qca_bug); 2717DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 2718 quirk_msi_intx_disable_qca_bug); 2719DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 2720 quirk_msi_intx_disable_qca_bug); 2721DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 2722 quirk_msi_intx_disable_qca_bug); 2723DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 2724 quirk_msi_intx_disable_qca_bug); 2725#endif /* CONFIG_PCI_MSI */ 2726 2727/* Allow manual resource allocation for PCI hotplug bridges 2728 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2729 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2730 * kernel fails to allocate resources when hotplug device is 2731 * inserted and PCI bus is rescanned. 2732 */ 2733static void quirk_hotplug_bridge(struct pci_dev *dev) 2734{ 2735 dev->is_hotplug_bridge = 1; 2736} 2737 2738DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2739 2740/* 2741 * This is a quirk for the Ricoh MMC controller found as a part of 2742 * some mulifunction chips. 2743 2744 * This is very similar and based on the ricoh_mmc driver written by 2745 * Philip Langdale. Thank you for these magic sequences. 2746 * 2747 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2748 * and one or both of cardbus or firewire. 2749 * 2750 * It happens that they implement SD and MMC 2751 * support as separate controllers (and PCI functions). The linux SDHCI 2752 * driver supports MMC cards but the chip detects MMC cards in hardware 2753 * and directs them to the MMC controller - so the SDHCI driver never sees 2754 * them. 2755 * 2756 * To get around this, we must disable the useless MMC controller. 2757 * At that point, the SDHCI controller will start seeing them 2758 * It seems to be the case that the relevant PCI registers to deactivate the 2759 * MMC controller live on PCI function 0, which might be the cardbus controller 2760 * or the firewire controller, depending on the particular chip in question 2761 * 2762 * This has to be done early, because as soon as we disable the MMC controller 2763 * other pci functions shift up one level, e.g. function #2 becomes function 2764 * #1, and this will confuse the pci core. 2765 */ 2766 2767#ifdef CONFIG_MMC_RICOH_MMC 2768static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2769{ 2770 /* disable via cardbus interface */ 2771 u8 write_enable; 2772 u8 write_target; 2773 u8 disable; 2774 2775 /* disable must be done via function #0 */ 2776 if (PCI_FUNC(dev->devfn)) 2777 return; 2778 2779 pci_read_config_byte(dev, 0xB7, &disable); 2780 if (disable & 0x02) 2781 return; 2782 2783 pci_read_config_byte(dev, 0x8E, &write_enable); 2784 pci_write_config_byte(dev, 0x8E, 0xAA); 2785 pci_read_config_byte(dev, 0x8D, &write_target); 2786 pci_write_config_byte(dev, 0x8D, 0xB7); 2787 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2788 pci_write_config_byte(dev, 0x8E, write_enable); 2789 pci_write_config_byte(dev, 0x8D, write_target); 2790 2791 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2792 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2793} 2794DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2795DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2796 2797static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2798{ 2799 /* disable via firewire interface */ 2800 u8 write_enable; 2801 u8 disable; 2802 2803 /* disable must be done via function #0 */ 2804 if (PCI_FUNC(dev->devfn)) 2805 return; 2806 /* 2807 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2808 * certain types of SD/MMC cards. Lowering the SD base 2809 * clock frequency from 200Mhz to 50Mhz fixes this issue. 2810 * 2811 * 0x150 - SD2.0 mode enable for changing base clock 2812 * frequency to 50Mhz 2813 * 0xe1 - Base clock frequency 2814 * 0x32 - 50Mhz new clock frequency 2815 * 0xf9 - Key register for 0x150 2816 * 0xfc - key register for 0xe1 2817 */ 2818 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 2819 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 2820 pci_write_config_byte(dev, 0xf9, 0xfc); 2821 pci_write_config_byte(dev, 0x150, 0x10); 2822 pci_write_config_byte(dev, 0xf9, 0x00); 2823 pci_write_config_byte(dev, 0xfc, 0x01); 2824 pci_write_config_byte(dev, 0xe1, 0x32); 2825 pci_write_config_byte(dev, 0xfc, 0x00); 2826 2827 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); 2828 } 2829 2830 pci_read_config_byte(dev, 0xCB, &disable); 2831 2832 if (disable & 0x02) 2833 return; 2834 2835 pci_read_config_byte(dev, 0xCA, &write_enable); 2836 pci_write_config_byte(dev, 0xCA, 0x57); 2837 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2838 pci_write_config_byte(dev, 0xCA, write_enable); 2839 2840 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2841 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2842 2843} 2844DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2845DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2846DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2847DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 2848DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2849DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2850#endif /*CONFIG_MMC_RICOH_MMC*/ 2851 2852#ifdef CONFIG_DMAR_TABLE 2853#define VTUNCERRMSK_REG 0x1ac 2854#define VTD_MSK_SPEC_ERRORS (1 << 31) 2855/* 2856 * This is a quirk for masking vt-d spec defined errors to platform error 2857 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets 2858 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 2859 * on the RAS config settings of the platform) when a vt-d fault happens. 2860 * The resulting SMI caused the system to hang. 2861 * 2862 * VT-d spec related errors are already handled by the VT-d OS code, so no 2863 * need to report the same error through other channels. 2864 */ 2865static void vtd_mask_spec_errors(struct pci_dev *dev) 2866{ 2867 u32 word; 2868 2869 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 2870 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 2871} 2872DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 2873DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 2874#endif 2875 2876static void fixup_ti816x_class(struct pci_dev *dev) 2877{ 2878 u32 class = dev->class; 2879 2880 /* TI 816x devices do not have class code set when in PCIe boot mode */ 2881 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 2882 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n", 2883 class, dev->class); 2884} 2885DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 2886 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class); 2887 2888/* Some PCIe devices do not work reliably with the claimed maximum 2889 * payload size supported. 2890 */ 2891static void fixup_mpss_256(struct pci_dev *dev) 2892{ 2893 dev->pcie_mpss = 1; /* 256 bytes */ 2894} 2895DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2896 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 2897DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2898 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 2899DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 2900 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 2901 2902/* Intel 5000 and 5100 Memory controllers have an errata with read completion 2903 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 2904 * Since there is no way of knowing what the PCIE MPS on each fabric will be 2905 * until all of the devices are discovered and buses walked, read completion 2906 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 2907 * it is possible to hotplug a device with MPS of 256B. 2908 */ 2909static void quirk_intel_mc_errata(struct pci_dev *dev) 2910{ 2911 int err; 2912 u16 rcc; 2913 2914 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) 2915 return; 2916 2917 /* Intel errata specifies bits to change but does not say what they are. 2918 * Keeping them magical until such time as the registers and values can 2919 * be explained. 2920 */ 2921 err = pci_read_config_word(dev, 0x48, &rcc); 2922 if (err) { 2923 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n"); 2924 return; 2925 } 2926 2927 if (!(rcc & (1 << 10))) 2928 return; 2929 2930 rcc &= ~(1 << 10); 2931 2932 err = pci_write_config_word(dev, 0x48, rcc); 2933 if (err) { 2934 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n"); 2935 return; 2936 } 2937 2938 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n"); 2939} 2940/* Intel 5000 series memory controllers and ports 2-7 */ 2941DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 2942DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 2943DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 2944DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 2945DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 2946DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 2947DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 2948DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 2949DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 2950DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 2951DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 2952DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 2953DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 2954DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 2955/* Intel 5100 series memory controllers and ports 2-7 */ 2956DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 2957DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 2958DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 2959DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 2960DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 2961DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 2962DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 2963DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 2964DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 2965DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 2966DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 2967 2968 2969/* 2970 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To 2971 * work around this, query the size it should be configured to by the device and 2972 * modify the resource end to correspond to this new size. 2973 */ 2974static void quirk_intel_ntb(struct pci_dev *dev) 2975{ 2976 int rc; 2977 u8 val; 2978 2979 rc = pci_read_config_byte(dev, 0x00D0, &val); 2980 if (rc) 2981 return; 2982 2983 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; 2984 2985 rc = pci_read_config_byte(dev, 0x00D1, &val); 2986 if (rc) 2987 return; 2988 2989 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; 2990} 2991DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 2992DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 2993 2994static ktime_t fixup_debug_start(struct pci_dev *dev, 2995 void (*fn)(struct pci_dev *dev)) 2996{ 2997 ktime_t calltime = ktime_set(0, 0); 2998 2999 dev_dbg(&dev->dev, "calling %pF\n", fn); 3000 if (initcall_debug) { 3001 pr_debug("calling %pF @ %i for %s\n", 3002 fn, task_pid_nr(current), dev_name(&dev->dev)); 3003 calltime = ktime_get(); 3004 } 3005 3006 return calltime; 3007} 3008 3009static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 3010 void (*fn)(struct pci_dev *dev)) 3011{ 3012 ktime_t delta, rettime; 3013 unsigned long long duration; 3014 3015 if (initcall_debug) { 3016 rettime = ktime_get(); 3017 delta = ktime_sub(rettime, calltime); 3018 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 3019 pr_debug("pci fixup %pF returned after %lld usecs for %s\n", 3020 fn, duration, dev_name(&dev->dev)); 3021 } 3022} 3023 3024/* 3025 * Some BIOS implementations leave the Intel GPU interrupts enabled, 3026 * even though no one is handling them (f.e. i915 driver is never loaded). 3027 * Additionally the interrupt destination is not set up properly 3028 * and the interrupt ends up -somewhere-. 3029 * 3030 * These spurious interrupts are "sticky" and the kernel disables 3031 * the (shared) interrupt line after 100.000+ generated interrupts. 3032 * 3033 * Fix it by disabling the still enabled interrupts. 3034 * This resolves crashes often seen on monitor unplug. 3035 */ 3036#define I915_DEIER_REG 0x4400c 3037static void disable_igfx_irq(struct pci_dev *dev) 3038{ 3039 void __iomem *regs = pci_iomap(dev, 0, 0); 3040 if (regs == NULL) { 3041 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n"); 3042 return; 3043 } 3044 3045 /* Check if any interrupt line is still enabled */ 3046 if (readl(regs + I915_DEIER_REG) != 0) { 3047 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3048 3049 writel(0, regs + I915_DEIER_REG); 3050 } 3051 3052 pci_iounmap(dev, regs); 3053} 3054DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3055DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3056DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3057 3058/* 3059 * PCI devices which are on Intel chips can skip the 10ms delay 3060 * before entering D3 mode. 3061 */ 3062static void quirk_remove_d3_delay(struct pci_dev *dev) 3063{ 3064 dev->d3_delay = 0; 3065} 3066DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); 3067DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); 3068DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); 3069DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); 3070DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); 3071DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); 3072DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); 3073DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); 3074DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); 3075DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); 3076DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); 3077DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); 3078DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); 3079DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); 3080 3081/* 3082 * Some devices may pass our check in pci_intx_mask_supported if 3083 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3084 * support this feature. 3085 */ 3086static void quirk_broken_intx_masking(struct pci_dev *dev) 3087{ 3088 dev->broken_intx_masking = 1; 3089} 3090DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030, 3091 quirk_broken_intx_masking); 3092DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3093 quirk_broken_intx_masking); 3094/* 3095 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3096 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3097 * 3098 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3099 */ 3100DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169, 3101 quirk_broken_intx_masking); 3102DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3103 quirk_broken_intx_masking); 3104 3105static void quirk_no_bus_reset(struct pci_dev *dev) 3106{ 3107 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3108} 3109 3110/* 3111 * Atheros AR93xx chips do not behave after a bus reset. The device will 3112 * throw a Link Down error on AER-capable systems and regardless of AER, 3113 * config space of the device is never accessible again and typically 3114 * causes the system to hang or reset when access is attempted. 3115 * http://www.spinics.net/lists/linux-pci/msg34797.html 3116 */ 3117DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3118 3119static void quirk_no_pm_reset(struct pci_dev *dev) 3120{ 3121 /* 3122 * We can't do a bus reset on root bus devices, but an ineffective 3123 * PM reset may be better than nothing. 3124 */ 3125 if (!pci_is_root_bus(dev->bus)) 3126 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3127} 3128 3129/* 3130 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3131 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3132 * to have no effect on the device: it retains the framebuffer contents and 3133 * monitor sync. Advertising this support makes other layers, like VFIO, 3134 * assume pci_reset_function() is viable for this device. Mark it as 3135 * unavailable to skip it when testing reset methods. 3136 */ 3137DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3138 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3139 3140#ifdef CONFIG_ACPI 3141/* 3142 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3143 * 3144 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3145 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3146 * be present after resume if a device was plugged in before suspend. 3147 * 3148 * The thunderbolt controller consists of a pcie switch with downstream 3149 * bridges leading to the NHI and to the tunnel pci bridges. 3150 * 3151 * This quirk cuts power to the whole chip. Therefore we have to apply it 3152 * during suspend_noirq of the upstream bridge. 3153 * 3154 * Power is automagically restored before resume. No action is needed. 3155 */ 3156static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3157{ 3158 acpi_handle bridge, SXIO, SXFP, SXLV; 3159 3160 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc.")) 3161 return; 3162 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3163 return; 3164 bridge = ACPI_HANDLE(&dev->dev); 3165 if (!bridge) 3166 return; 3167 /* 3168 * SXIO and SXLV are present only on machines requiring this quirk. 3169 * TB bridges in external devices might have the same device id as those 3170 * on the host, but they will not have the associated ACPI methods. This 3171 * implicitly checks that we are at the right bridge. 3172 */ 3173 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3174 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3175 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3176 return; 3177 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n"); 3178 3179 /* magic sequence */ 3180 acpi_execute_simple_method(SXIO, NULL, 1); 3181 acpi_execute_simple_method(SXFP, NULL, 0); 3182 msleep(300); 3183 acpi_execute_simple_method(SXLV, NULL, 0); 3184 acpi_execute_simple_method(SXIO, NULL, 0); 3185 acpi_execute_simple_method(SXLV, NULL, 0); 3186} 3187DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 0x1547, 3188 quirk_apple_poweroff_thunderbolt); 3189 3190/* 3191 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels. 3192 * 3193 * During suspend the thunderbolt controller is reset and all pci 3194 * tunnels are lost. The NHI driver will try to reestablish all tunnels 3195 * during resume. We have to manually wait for the NHI since there is 3196 * no parent child relationship between the NHI and the tunneled 3197 * bridges. 3198 */ 3199static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) 3200{ 3201 struct pci_dev *sibling = NULL; 3202 struct pci_dev *nhi = NULL; 3203 3204 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc.")) 3205 return; 3206 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) 3207 return; 3208 /* 3209 * Find the NHI and confirm that we are a bridge on the tb host 3210 * controller and not on a tb endpoint. 3211 */ 3212 sibling = pci_get_slot(dev->bus, 0x0); 3213 if (sibling == dev) 3214 goto out; /* we are the downstream bridge to the NHI */ 3215 if (!sibling || !sibling->subordinate) 3216 goto out; 3217 nhi = pci_get_slot(sibling->subordinate, 0x0); 3218 if (!nhi) 3219 goto out; 3220 if (nhi->vendor != PCI_VENDOR_ID_INTEL 3221 || (nhi->device != 0x1547 && nhi->device != 0x156c) 3222 || nhi->subsystem_vendor != 0x2222 3223 || nhi->subsystem_device != 0x1111) 3224 goto out; 3225 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); 3226 device_pm_wait_for_dev(&dev->dev, &nhi->dev); 3227out: 3228 pci_dev_put(nhi); 3229 pci_dev_put(sibling); 3230} 3231DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x1547, 3232 quirk_apple_wait_for_thunderbolt); 3233DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x156d, 3234 quirk_apple_wait_for_thunderbolt); 3235#endif 3236 3237static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 3238 struct pci_fixup *end) 3239{ 3240 ktime_t calltime; 3241 3242 for (; f < end; f++) 3243 if ((f->class == (u32) (dev->class >> f->class_shift) || 3244 f->class == (u32) PCI_ANY_ID) && 3245 (f->vendor == dev->vendor || 3246 f->vendor == (u16) PCI_ANY_ID) && 3247 (f->device == dev->device || 3248 f->device == (u16) PCI_ANY_ID)) { 3249 calltime = fixup_debug_start(dev, f->hook); 3250 f->hook(dev); 3251 fixup_debug_report(dev, calltime, f->hook); 3252 } 3253} 3254 3255extern struct pci_fixup __start_pci_fixups_early[]; 3256extern struct pci_fixup __end_pci_fixups_early[]; 3257extern struct pci_fixup __start_pci_fixups_header[]; 3258extern struct pci_fixup __end_pci_fixups_header[]; 3259extern struct pci_fixup __start_pci_fixups_final[]; 3260extern struct pci_fixup __end_pci_fixups_final[]; 3261extern struct pci_fixup __start_pci_fixups_enable[]; 3262extern struct pci_fixup __end_pci_fixups_enable[]; 3263extern struct pci_fixup __start_pci_fixups_resume[]; 3264extern struct pci_fixup __end_pci_fixups_resume[]; 3265extern struct pci_fixup __start_pci_fixups_resume_early[]; 3266extern struct pci_fixup __end_pci_fixups_resume_early[]; 3267extern struct pci_fixup __start_pci_fixups_suspend[]; 3268extern struct pci_fixup __end_pci_fixups_suspend[]; 3269extern struct pci_fixup __start_pci_fixups_suspend_late[]; 3270extern struct pci_fixup __end_pci_fixups_suspend_late[]; 3271 3272static bool pci_apply_fixup_final_quirks; 3273 3274void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 3275{ 3276 struct pci_fixup *start, *end; 3277 3278 switch (pass) { 3279 case pci_fixup_early: 3280 start = __start_pci_fixups_early; 3281 end = __end_pci_fixups_early; 3282 break; 3283 3284 case pci_fixup_header: 3285 start = __start_pci_fixups_header; 3286 end = __end_pci_fixups_header; 3287 break; 3288 3289 case pci_fixup_final: 3290 if (!pci_apply_fixup_final_quirks) 3291 return; 3292 start = __start_pci_fixups_final; 3293 end = __end_pci_fixups_final; 3294 break; 3295 3296 case pci_fixup_enable: 3297 start = __start_pci_fixups_enable; 3298 end = __end_pci_fixups_enable; 3299 break; 3300 3301 case pci_fixup_resume: 3302 start = __start_pci_fixups_resume; 3303 end = __end_pci_fixups_resume; 3304 break; 3305 3306 case pci_fixup_resume_early: 3307 start = __start_pci_fixups_resume_early; 3308 end = __end_pci_fixups_resume_early; 3309 break; 3310 3311 case pci_fixup_suspend: 3312 start = __start_pci_fixups_suspend; 3313 end = __end_pci_fixups_suspend; 3314 break; 3315 3316 case pci_fixup_suspend_late: 3317 start = __start_pci_fixups_suspend_late; 3318 end = __end_pci_fixups_suspend_late; 3319 break; 3320 3321 default: 3322 /* stupid compiler warning, you would think with an enum... */ 3323 return; 3324 } 3325 pci_do_fixups(dev, start, end); 3326} 3327EXPORT_SYMBOL(pci_fixup_device); 3328 3329 3330static int __init pci_apply_final_quirks(void) 3331{ 3332 struct pci_dev *dev = NULL; 3333 u8 cls = 0; 3334 u8 tmp; 3335 3336 if (pci_cache_line_size) 3337 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 3338 pci_cache_line_size << 2); 3339 3340 pci_apply_fixup_final_quirks = true; 3341 for_each_pci_dev(dev) { 3342 pci_fixup_device(pci_fixup_final, dev); 3343 /* 3344 * If arch hasn't set it explicitly yet, use the CLS 3345 * value shared by all PCI devices. If there's a 3346 * mismatch, fall back to the default value. 3347 */ 3348 if (!pci_cache_line_size) { 3349 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 3350 if (!cls) 3351 cls = tmp; 3352 if (!tmp || cls == tmp) 3353 continue; 3354 3355 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n", 3356 cls << 2, tmp << 2, 3357 pci_dfl_cache_line_size << 2); 3358 pci_cache_line_size = pci_dfl_cache_line_size; 3359 } 3360 } 3361 3362 if (!pci_cache_line_size) { 3363 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 3364 cls << 2, pci_dfl_cache_line_size << 2); 3365 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 3366 } 3367 3368 return 0; 3369} 3370 3371fs_initcall_sync(pci_apply_final_quirks); 3372 3373/* 3374 * Followings are device-specific reset methods which can be used to 3375 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3376 * not available. 3377 */ 3378static int reset_intel_generic_dev(struct pci_dev *dev, int probe) 3379{ 3380 int pos; 3381 3382 /* only implement PCI_CLASS_SERIAL_USB at present */ 3383 if (dev->class == PCI_CLASS_SERIAL_USB) { 3384 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); 3385 if (!pos) 3386 return -ENOTTY; 3387 3388 if (probe) 3389 return 0; 3390 3391 pci_write_config_byte(dev, pos + 0x4, 1); 3392 msleep(100); 3393 3394 return 0; 3395 } else { 3396 return -ENOTTY; 3397 } 3398} 3399 3400static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3401{ 3402 /* 3403 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3404 * 3405 * The 82599 supports FLR on VFs, but FLR support is reported only 3406 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3407 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP. 3408 */ 3409 3410 if (probe) 3411 return 0; 3412 3413 if (!pci_wait_for_pending_transaction(dev)) 3414 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 3415 3416 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3417 3418 msleep(100); 3419 3420 return 0; 3421} 3422 3423#include "../gpu/drm/i915/i915_reg.h" 3424#define MSG_CTL 0x45010 3425#define NSDE_PWR_STATE 0xd0100 3426#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3427 3428static int reset_ivb_igd(struct pci_dev *dev, int probe) 3429{ 3430 void __iomem *mmio_base; 3431 unsigned long timeout; 3432 u32 val; 3433 3434 if (probe) 3435 return 0; 3436 3437 mmio_base = pci_iomap(dev, 0, 0); 3438 if (!mmio_base) 3439 return -ENOMEM; 3440 3441 iowrite32(0x00000002, mmio_base + MSG_CTL); 3442 3443 /* 3444 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3445 * driver loaded sets the right bits. However, this's a reset and 3446 * the bits have been set by i915 previously, so we clobber 3447 * SOUTH_CHICKEN2 register directly here. 3448 */ 3449 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3450 3451 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3452 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3453 3454 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3455 do { 3456 val = ioread32(mmio_base + PCH_PP_STATUS); 3457 if ((val & 0xb0000000) == 0) 3458 goto reset_complete; 3459 msleep(10); 3460 } while (time_before(jiffies, timeout)); 3461 dev_warn(&dev->dev, "timeout during reset\n"); 3462 3463reset_complete: 3464 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3465 3466 pci_iounmap(dev, mmio_base); 3467 return 0; 3468} 3469 3470/* 3471 * Device-specific reset method for Chelsio T4-based adapters. 3472 */ 3473static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3474{ 3475 u16 old_command; 3476 u16 msix_flags; 3477 3478 /* 3479 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3480 * that we have no device-specific reset method. 3481 */ 3482 if ((dev->device & 0xf000) != 0x4000) 3483 return -ENOTTY; 3484 3485 /* 3486 * If this is the "probe" phase, return 0 indicating that we can 3487 * reset this device. 3488 */ 3489 if (probe) 3490 return 0; 3491 3492 /* 3493 * T4 can wedge if there are DMAs in flight within the chip and Bus 3494 * Master has been disabled. We need to have it on till the Function 3495 * Level Reset completes. (BUS_MASTER is disabled in 3496 * pci_reset_function()). 3497 */ 3498 pci_read_config_word(dev, PCI_COMMAND, &old_command); 3499 pci_write_config_word(dev, PCI_COMMAND, 3500 old_command | PCI_COMMAND_MASTER); 3501 3502 /* 3503 * Perform the actual device function reset, saving and restoring 3504 * configuration information around the reset. 3505 */ 3506 pci_save_state(dev); 3507 3508 /* 3509 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 3510 * are disabled when an MSI-X interrupt message needs to be delivered. 3511 * So we briefly re-enable MSI-X interrupts for the duration of the 3512 * FLR. The pci_restore_state() below will restore the original 3513 * MSI-X state. 3514 */ 3515 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 3516 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 3517 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 3518 msix_flags | 3519 PCI_MSIX_FLAGS_ENABLE | 3520 PCI_MSIX_FLAGS_MASKALL); 3521 3522 /* 3523 * Start of pcie_flr() code sequence. This reset code is a copy of 3524 * the guts of pcie_flr() because that's not an exported function. 3525 */ 3526 3527 if (!pci_wait_for_pending_transaction(dev)) 3528 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 3529 3530 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3531 msleep(100); 3532 3533 /* 3534 * End of pcie_flr() code sequence. 3535 */ 3536 3537 /* 3538 * Restore the configuration information (BAR values, etc.) including 3539 * the original PCI Configuration Space Command word, and return 3540 * success. 3541 */ 3542 pci_restore_state(dev); 3543 pci_write_config_word(dev, PCI_COMMAND, old_command); 3544 return 0; 3545} 3546 3547#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 3548#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 3549#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 3550 3551static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3552 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3553 reset_intel_82599_sfp_virtfn }, 3554 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 3555 reset_ivb_igd }, 3556 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 3557 reset_ivb_igd }, 3558 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 3559 reset_intel_generic_dev }, 3560 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 3561 reset_chelsio_generic_dev }, 3562 { 0 } 3563}; 3564 3565/* 3566 * These device-specific reset methods are here rather than in a driver 3567 * because when a host assigns a device to a guest VM, the host may need 3568 * to reset the device but probably doesn't have a driver for it. 3569 */ 3570int pci_dev_specific_reset(struct pci_dev *dev, int probe) 3571{ 3572 const struct pci_dev_reset_methods *i; 3573 3574 for (i = pci_dev_reset_methods; i->reset; i++) { 3575 if ((i->vendor == dev->vendor || 3576 i->vendor == (u16)PCI_ANY_ID) && 3577 (i->device == dev->device || 3578 i->device == (u16)PCI_ANY_ID)) 3579 return i->reset(dev, probe); 3580 } 3581 3582 return -ENOTTY; 3583} 3584 3585static void quirk_dma_func0_alias(struct pci_dev *dev) 3586{ 3587 if (PCI_FUNC(dev->devfn) != 0) { 3588 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0); 3589 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3590 } 3591} 3592 3593/* 3594 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 3595 * 3596 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 3597 */ 3598DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 3599DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 3600 3601static void quirk_dma_func1_alias(struct pci_dev *dev) 3602{ 3603 if (PCI_FUNC(dev->devfn) != 1) { 3604 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1); 3605 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3606 } 3607} 3608 3609/* 3610 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 3611 * SKUs function 1 is present and is a legacy IDE controller, in other 3612 * SKUs this function is not present, making this a ghost requester. 3613 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 3614 */ 3615DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 3616 quirk_dma_func1_alias); 3617/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 3618DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 3619 quirk_dma_func1_alias); 3620/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 3621DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 3622 quirk_dma_func1_alias); 3623/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 3624DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 3625 quirk_dma_func1_alias); 3626/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 3627DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 3628 quirk_dma_func1_alias); 3629/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 3630DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 3631 quirk_dma_func1_alias); 3632DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 3633 quirk_dma_func1_alias); 3634/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 3635DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 3636 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 3637 quirk_dma_func1_alias); 3638 3639/* 3640 * Some devices DMA with the wrong devfn, not just the wrong function. 3641 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 3642 * the alias is "fixed" and independent of the device devfn. 3643 * 3644 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 3645 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 3646 * single device on the secondary bus. In reality, the single exposed 3647 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 3648 * that provides a bridge to the internal bus of the I/O processor. The 3649 * controller supports private devices, which can be hidden from PCI config 3650 * space. In the case of the Adaptec 3405, a private device at 01.0 3651 * appears to be the DMA engine, which therefore needs to become a DMA 3652 * alias for the device. 3653 */ 3654static const struct pci_device_id fixed_dma_alias_tbl[] = { 3655 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 3656 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 3657 .driver_data = PCI_DEVFN(1, 0) }, 3658 { 0 } 3659}; 3660 3661static void quirk_fixed_dma_alias(struct pci_dev *dev) 3662{ 3663 const struct pci_device_id *id; 3664 3665 id = pci_match_id(fixed_dma_alias_tbl, dev); 3666 if (id) { 3667 dev->dma_alias_devfn = id->driver_data; 3668 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; 3669 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n", 3670 PCI_SLOT(dev->dma_alias_devfn), 3671 PCI_FUNC(dev->dma_alias_devfn)); 3672 } 3673} 3674 3675DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 3676 3677/* 3678 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 3679 * using the wrong DMA alias for the device. Some of these devices can be 3680 * used as either forward or reverse bridges, so we need to test whether the 3681 * device is operating in the correct mode. We could probably apply this 3682 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 3683 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 3684 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 3685 */ 3686static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 3687{ 3688 if (!pci_is_root_bus(pdev->bus) && 3689 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 3690 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 3691 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 3692 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 3693} 3694/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 3695DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 3696 quirk_use_pcie_bridge_dma_alias); 3697/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 3698DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 3699/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 3700DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 3701/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 3702DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 3703 3704/* 3705 * AMD has indicated that the devices below do not support peer-to-peer 3706 * in any system where they are found in the southbridge with an AMD 3707 * IOMMU in the system. Multifunction devices that do not support 3708 * peer-to-peer between functions can claim to support a subset of ACS. 3709 * Such devices effectively enable request redirect (RR) and completion 3710 * redirect (CR) since all transactions are redirected to the upstream 3711 * root complex. 3712 * 3713 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 3714 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 3715 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 3716 * 3717 * 1002:4385 SBx00 SMBus Controller 3718 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 3719 * 1002:4383 SBx00 Azalia (Intel HDA) 3720 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 3721 * 1002:4384 SBx00 PCI to PCI Bridge 3722 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 3723 * 3724 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 3725 * 3726 * 1022:780f [AMD] FCH PCI Bridge 3727 * 1022:7809 [AMD] FCH USB OHCI Controller 3728 */ 3729static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 3730{ 3731#ifdef CONFIG_ACPI 3732 struct acpi_table_header *header = NULL; 3733 acpi_status status; 3734 3735 /* Targeting multifunction devices on the SB (appears on root bus) */ 3736 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 3737 return -ENODEV; 3738 3739 /* The IVRS table describes the AMD IOMMU */ 3740 status = acpi_get_table("IVRS", 0, &header); 3741 if (ACPI_FAILURE(status)) 3742 return -ENODEV; 3743 3744 /* Filter out flags not applicable to multifunction */ 3745 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 3746 3747 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; 3748#else 3749 return -ENODEV; 3750#endif 3751} 3752 3753/* 3754 * Many Intel PCH root ports do provide ACS-like features to disable peer 3755 * transactions and validate bus numbers in requests, but do not provide an 3756 * actual PCIe ACS capability. This is the list of device IDs known to fall 3757 * into that category as provided by Intel in Red Hat bugzilla 1037684. 3758 */ 3759static const u16 pci_quirk_intel_pch_acs_ids[] = { 3760 /* Ibexpeak PCH */ 3761 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 3762 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 3763 /* Cougarpoint PCH */ 3764 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 3765 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 3766 /* Pantherpoint PCH */ 3767 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 3768 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 3769 /* Lynxpoint-H PCH */ 3770 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 3771 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 3772 /* Lynxpoint-LP PCH */ 3773 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 3774 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 3775 /* Wildcat PCH */ 3776 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 3777 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 3778 /* Patsburg (X79) PCH */ 3779 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 3780 /* Wellsburg (X99) PCH */ 3781 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 3782 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 3783}; 3784 3785static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 3786{ 3787 int i; 3788 3789 /* Filter out a few obvious non-matches first */ 3790 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 3791 return false; 3792 3793 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 3794 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 3795 return true; 3796 3797 return false; 3798} 3799 3800#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV) 3801 3802static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 3803{ 3804 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? 3805 INTEL_PCH_ACS_FLAGS : 0; 3806 3807 if (!pci_quirk_intel_pch_acs_match(dev)) 3808 return -ENOTTY; 3809 3810 return acs_flags & ~flags ? 0 : 1; 3811} 3812 3813static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 3814{ 3815 /* 3816 * SV, TB, and UF are not relevant to multifunction endpoints. 3817 * 3818 * Multifunction devices are only required to implement RR, CR, and DT 3819 * in their ACS capability if they support peer-to-peer transactions. 3820 * Devices matching this quirk have been verified by the vendor to not 3821 * perform peer-to-peer with other functions, allowing us to mask out 3822 * these bits as if they were unimplemented in the ACS capability. 3823 */ 3824 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 3825 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 3826 3827 return acs_flags ? 0 : 1; 3828} 3829 3830static const struct pci_dev_acs_enabled { 3831 u16 vendor; 3832 u16 device; 3833 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 3834} pci_dev_acs_enabled[] = { 3835 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 3836 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 3837 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 3838 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 3839 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 3840 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 3841 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 3842 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 3843 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 3844 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 3845 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 3846 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 3847 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 3848 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 3849 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 3850 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 3851 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 3852 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 3853 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 3854 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 3855 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 3856 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 3857 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 3858 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 3859 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 3860 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 3861 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 3862 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 3863 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 3864 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 3865 /* 82580 */ 3866 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 3867 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 3868 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 3869 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 3870 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 3871 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 3872 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 3873 /* 82576 */ 3874 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 3875 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 3876 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 3877 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 3878 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 3879 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 3880 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 3881 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 3882 /* 82575 */ 3883 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 3884 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 3885 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 3886 /* I350 */ 3887 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 3888 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 3889 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 3890 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 3891 /* 82571 (Quads omitted due to non-ACS switch) */ 3892 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 3893 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 3894 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 3895 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 3896 /* Intel PCH root ports */ 3897 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 3898 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 3899 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 3900 { 0 } 3901}; 3902 3903int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 3904{ 3905 const struct pci_dev_acs_enabled *i; 3906 int ret; 3907 3908 /* 3909 * Allow devices that do not expose standard PCIe ACS capabilities 3910 * or control to indicate their support here. Multi-function express 3911 * devices which do not allow internal peer-to-peer between functions, 3912 * but do not implement PCIe ACS may wish to return true here. 3913 */ 3914 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 3915 if ((i->vendor == dev->vendor || 3916 i->vendor == (u16)PCI_ANY_ID) && 3917 (i->device == dev->device || 3918 i->device == (u16)PCI_ANY_ID)) { 3919 ret = i->acs_enabled(dev, acs_flags); 3920 if (ret >= 0) 3921 return ret; 3922 } 3923 } 3924 3925 return -ENOTTY; 3926} 3927 3928/* Config space offset of Root Complex Base Address register */ 3929#define INTEL_LPC_RCBA_REG 0xf0 3930/* 31:14 RCBA address */ 3931#define INTEL_LPC_RCBA_MASK 0xffffc000 3932/* RCBA Enable */ 3933#define INTEL_LPC_RCBA_ENABLE (1 << 0) 3934 3935/* Backbone Scratch Pad Register */ 3936#define INTEL_BSPR_REG 0x1104 3937/* Backbone Peer Non-Posted Disable */ 3938#define INTEL_BSPR_REG_BPNPD (1 << 8) 3939/* Backbone Peer Posted Disable */ 3940#define INTEL_BSPR_REG_BPPD (1 << 9) 3941 3942/* Upstream Peer Decode Configuration Register */ 3943#define INTEL_UPDCR_REG 0x1114 3944/* 5:0 Peer Decode Enable bits */ 3945#define INTEL_UPDCR_REG_MASK 0x3f 3946 3947static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 3948{ 3949 u32 rcba, bspr, updcr; 3950 void __iomem *rcba_mem; 3951 3952 /* 3953 * Read the RCBA register from the LPC (D31:F0). PCH root ports 3954 * are D28:F* and therefore get probed before LPC, thus we can't 3955 * use pci_get_slot/pci_read_config_dword here. 3956 */ 3957 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 3958 INTEL_LPC_RCBA_REG, &rcba); 3959 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 3960 return -EINVAL; 3961 3962 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK, 3963 PAGE_ALIGN(INTEL_UPDCR_REG)); 3964 if (!rcba_mem) 3965 return -ENOMEM; 3966 3967 /* 3968 * The BSPR can disallow peer cycles, but it's set by soft strap and 3969 * therefore read-only. If both posted and non-posted peer cycles are 3970 * disallowed, we're ok. If either are allowed, then we need to use 3971 * the UPDCR to disable peer decodes for each port. This provides the 3972 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 3973 */ 3974 bspr = readl(rcba_mem + INTEL_BSPR_REG); 3975 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 3976 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 3977 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 3978 if (updcr & INTEL_UPDCR_REG_MASK) { 3979 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n"); 3980 updcr &= ~INTEL_UPDCR_REG_MASK; 3981 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 3982 } 3983 } 3984 3985 iounmap(rcba_mem); 3986 return 0; 3987} 3988 3989/* Miscellaneous Port Configuration register */ 3990#define INTEL_MPC_REG 0xd8 3991/* MPC: Invalid Receive Bus Number Check Enable */ 3992#define INTEL_MPC_REG_IRBNCE (1 << 26) 3993 3994static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 3995{ 3996 u32 mpc; 3997 3998 /* 3999 * When enabled, the IRBNCE bit of the MPC register enables the 4000 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 4001 * ensures that requester IDs fall within the bus number range 4002 * of the bridge. Enable if not already. 4003 */ 4004 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 4005 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 4006 dev_info(&dev->dev, "Enabling MPC IRBNCE\n"); 4007 mpc |= INTEL_MPC_REG_IRBNCE; 4008 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 4009 } 4010} 4011 4012static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 4013{ 4014 if (!pci_quirk_intel_pch_acs_match(dev)) 4015 return -ENOTTY; 4016 4017 if (pci_quirk_enable_intel_lpc_acs(dev)) { 4018 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n"); 4019 return 0; 4020 } 4021 4022 pci_quirk_enable_intel_rp_mpc_acs(dev); 4023 4024 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 4025 4026 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n"); 4027 4028 return 0; 4029} 4030 4031static const struct pci_dev_enable_acs { 4032 u16 vendor; 4033 u16 device; 4034 int (*enable_acs)(struct pci_dev *dev); 4035} pci_dev_enable_acs[] = { 4036 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs }, 4037 { 0 } 4038}; 4039 4040void pci_dev_specific_enable_acs(struct pci_dev *dev) 4041{ 4042 const struct pci_dev_enable_acs *i; 4043 int ret; 4044 4045 for (i = pci_dev_enable_acs; i->enable_acs; i++) { 4046 if ((i->vendor == dev->vendor || 4047 i->vendor == (u16)PCI_ANY_ID) && 4048 (i->device == dev->device || 4049 i->device == (u16)PCI_ANY_ID)) { 4050 ret = i->enable_acs(dev); 4051 if (ret >= 0) 4052 return; 4053 } 4054 } 4055} 4056