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Searched refs:INTEL_INFO (Results 1 – 36 of 36) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Di915_suspend.c37 if (INTEL_INFO(dev)->gen <= 4) in i915_save_display()
43 else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) in i915_save_display()
60 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) in i915_save_display()
70 if (INTEL_INFO(dev)->gen <= 4) in i915_restore_display()
78 else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) in i915_restore_display()
98 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) in i915_restore_display()
118 if (INTEL_INFO(dev)->gen < 7) in i915_save_state()
152 if (INTEL_INFO(dev)->gen < 7) in i915_restore_state()
Di915_drv.h142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
228 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
231 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
235 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
2280 #define INTEL_INFO(p) (&__I915__(p)->info) macro
2281 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2286 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2288 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2291 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2292 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
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Di915_gem_tiling.c94 if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) { in i915_gem_detect_bit_6_swizzle()
104 } else if (INTEL_INFO(dev)->gen >= 6) { in i915_gem_detect_bit_6_swizzle()
249 if (INTEL_INFO(dev)->gen >= 7) { in i915_tiling_ok()
252 } else if (INTEL_INFO(dev)->gen >= 4) { in i915_tiling_ok()
272 if (INTEL_INFO(dev)->gen >= 4) { in i915_tiling_ok()
294 if (INTEL_INFO(obj->base.dev)->gen >= 4) in i915_gem_object_fence_ok()
297 if (INTEL_INFO(obj->base.dev)->gen == 3) { in i915_gem_object_fence_ok()
Di915_dma.c109 value = INTEL_INFO(dev)->gen >= 4; in i915_getparam()
157 value = INTEL_INFO(dev)->subslice_total; in i915_getparam()
162 value = INTEL_INFO(dev)->eu_total; in i915_getparam()
232 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_alloc_mchbar_resource()
237 if (INTEL_INFO(dev)->gen >= 4) in intel_alloc_mchbar_resource()
264 if (INTEL_INFO(dev)->gen >= 4) in intel_alloc_mchbar_resource()
278 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_setup_mchbar()
318 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_teardown_mchbar()
440 if (INTEL_INFO(dev)->num_pipes == 0) in i915_load_modeset_init()
588 if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9) in intel_device_info_runtime_init()
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Dintel_fbc.c451 if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) in intel_fbc_find_crtc()
453 else if (INTEL_INFO(dev_priv)->gen <= 4) in intel_fbc_find_crtc()
556 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) { in intel_fbc_update()
559 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in intel_fbc_update()
572 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) && in intel_fbc_update()
588 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && in intel_fbc_update()
715 if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) in intel_fbc_init()
719 if (INTEL_INFO(dev_priv)->gen >= 7) { in intel_fbc_init()
723 } else if (INTEL_INFO(dev_priv)->gen >= 5) { in intel_fbc_init()
Dintel_ringbuffer.c452 if (INTEL_INFO(ring->dev)->gen >= 8) in intel_ring_get_active_head()
455 else if (INTEL_INFO(ring->dev)->gen >= 4) in intel_ring_get_active_head()
469 if (INTEL_INFO(ring->dev)->gen >= 4) in ring_setup_phys_status_page()
520 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { in intel_ring_setup_status_page()
658 if (INTEL_INFO(dev)->gen >= 5) { in intel_fini_pipe_control()
1064 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) in init_render_ring()
1073 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9) in init_render_ring()
1078 if (INTEL_INFO(dev)->gen == 6) in init_render_ring()
1098 if (INTEL_INFO(dev)->gen >= 6) in init_render_ring()
1130 num_rings = hweight32(INTEL_INFO(dev)->ring_mask); in gen8_rcs_signal()
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Di915_gpu_error.c262 if (INTEL_INFO(dev)->gen >= 4) { in i915_ring_error_state()
270 if (INTEL_INFO(dev)->gen >= 6) { in i915_ring_error_state()
288 if (INTEL_INFO(dev)->gen >= 8) { in i915_ring_error_state()
368 if (INTEL_INFO(dev)->gen >= 8) { in i915_error_state_to_str()
387 if (INTEL_INFO(dev)->gen >= 6) { in i915_error_state_to_str()
390 if (INTEL_INFO(dev)->gen >= 8) in i915_error_state_to_str()
397 if (INTEL_INFO(dev)->gen == 7) in i915_error_state_to_str()
790 else if (INTEL_INFO(dev)->gen >= 6) in i915_gem_record_fences()
854 if (INTEL_INFO(dev)->gen >= 6) { in i915_record_ring_state()
857 if (INTEL_INFO(dev)->gen >= 8) in i915_record_ring_state()
[all …]
Di915_gem_context.c114 switch (INTEL_INFO(dev)->gen) { in get_context_size()
172 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { in i915_gem_alloc_context_obj()
500 hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 : in mi_set_context()
516 if (!IS_HASWELL(ring->dev) && INTEL_INFO(ring->dev)->gen < 8) in mi_set_context()
521 if (INTEL_INFO(ring->dev)->gen >= 7) in mi_set_context()
529 if (INTEL_INFO(ring->dev)->gen >= 7) { in mi_set_context()
555 if (INTEL_INFO(ring->dev)->gen >= 7) { in mi_set_context()
606 if (INTEL_INFO(ring->dev)->gen < 8) in needs_pd_load_pre()
Di915_gem_stolen.c63 if (INTEL_INFO(dev)->gen >= 3) { in i915_stolen_to_physical()
78 if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) { in i915_stolen_to_physical()
185 if (ret && INTEL_INFO(dev)->gen <= 4) { in find_compression_threshold()
300 if (intel_iommu_gfx_mapped && INTEL_INFO(dev)->gen < 8) { in i915_gem_init_stolen()
316 if (INTEL_INFO(dev)->gen >= 8) { in i915_gem_init_stolen()
Di915_irq.c209 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; in gen6_pm_iir()
214 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; in gen6_pm_imr()
219 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; in gen6_pm_ier()
308 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) in gen6_sanitize_rps_pm_mask()
311 if (INTEL_INFO(dev_priv)->gen >= 8) in gen6_sanitize_rps_pm_mask()
487 if (INTEL_INFO(dev)->gen >= 4) in i915_enable_asle_pipestat()
684 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in i915_get_crtc_scanoutpos()
746 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in i915_get_crtc_scanoutpos()
781 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { in i915_get_vblank_timestamp()
1477 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), in intel_hpd_irq_handler()
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Di915_debugfs.c84 const struct intel_device_info *info = INTEL_INFO(dev); in i915_capabilities()
591 if (INTEL_INFO(dev)->gen >= 4) in i915_gem_pageflip_info()
760 } else if (INTEL_INFO(dev)->gen >= 8) { in i915_interrupt_info()
881 if (INTEL_INFO(dev)->gen >= 6) { in i915_interrupt_info()
1520 else if (INTEL_INFO(dev)->gen >= 6) in i915_drpc_info()
1593 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) in i915_fbc_fc_get()
1609 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) in i915_fbc_fc_set()
1645 if (INTEL_INFO(dev)->gen >= 8) { in i915_ips_status()
2100 } else if (INTEL_INFO(dev)->gen >= 6) { in i915_swizzle_info()
2109 if (INTEL_INFO(dev)->gen >= 8) in i915_swizzle_info()
[all …]
Di915_gem_gtt.c108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; in sanitize_enable_ppgtt()
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; in sanitize_enable_ppgtt()
118 if (INTEL_INFO(dev)->gen < 9 && in sanitize_enable_ppgtt()
130 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { in sanitize_enable_ppgtt()
143 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) in sanitize_enable_ppgtt()
338 const size_t count = INTEL_INFO(dev)->gen >= 8 ? in alloc_pt_single()
1168 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; in mark_tlbs_dirty()
1441 if (INTEL_INFO(dev)->gen < 8) in __hw_ppgtt_init()
1482 else if (INTEL_INFO(dev)->gen >= 8) in i915_ppgtt_init_hw()
1485 MISSING_CASE(INTEL_INFO(dev)->gen); in i915_ppgtt_init_hw()
[all …]
Dintel_display.c1028 if (INTEL_INFO(dev)->gen >= 4) { in intel_wait_for_pipe_off()
1205 if (INTEL_INFO(dev_priv->dev)->gen == 5) in assert_fdi_tx_pll_enabled()
1347 if (INTEL_INFO(dev)->gen >= 4) { in assert_planes_disabled()
1375 if (INTEL_INFO(dev)->gen >= 9) { in assert_sprites_disabled()
1390 } else if (INTEL_INFO(dev)->gen >= 7) { in assert_sprites_disabled()
1396 } else if (INTEL_INFO(dev)->gen >= 5) { in assert_sprites_disabled()
1683 BUG_ON(INTEL_INFO(dev)->gen >= 5); in i9xx_enable_pll()
1708 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_enable_pll()
1915 BUG_ON(INTEL_INFO(dev)->gen < 5); in intel_disable_shared_dpll()
2192 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); in intel_flush_primary_plane()
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Di915_gem_execbuffer.c276 if (INTEL_INFO(dev)->gen >= 8) { in relocate_entry_cpu()
320 if (INTEL_INFO(dev)->gen >= 8) { in relocate_entry_gtt()
367 if (INTEL_INFO(dev)->gen >= 8) { in relocate_entry_clflush()
451 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { in i915_gem_execbuffer_relocate_entry()
691 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; in i915_gem_execbuffer_reserve()
1110 if (INTEL_INFO(ring->dev)->gen >= 4) { in i915_emit_box()
1209 if (INTEL_INFO(dev)->gen >= 5) { in i915_gem_ringbuffer_submission()
1274 if (INTEL_INFO(dev)->gen < 4) { in i915_gem_ringbuffer_submission()
1280 if (INTEL_INFO(dev)->gen > 5 && in i915_gem_ringbuffer_submission()
1288 if (INTEL_INFO(dev)->gen >= 6) in i915_gem_ringbuffer_submission()
[all …]
Dintel_lrc.c223 if (INTEL_INFO(dev)->gen >= 9) in intel_sanitize_enable_execlists()
1497 if (INTEL_INFO(dev)->gen >= 9) in logical_render_ring_init()
1691 if (INTEL_INFO(dev)->gen < 9) in make_rpcs()
1700 if (INTEL_INFO(dev)->has_slice_pg) { in make_rpcs()
1702 rpcs |= INTEL_INFO(dev)->slice_total << in make_rpcs()
1707 if (INTEL_INFO(dev)->has_subslice_pg) { in make_rpcs()
1709 rpcs |= INTEL_INFO(dev)->subslice_per_slice << in make_rpcs()
1714 if (INTEL_INFO(dev)->has_eu_pg) { in make_rpcs()
1715 rpcs |= INTEL_INFO(dev)->eu_per_subslice << in make_rpcs()
1717 rpcs |= INTEL_INFO(dev)->eu_per_subslice << in make_rpcs()
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Dintel_pm.c1000 fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1; in vlv_compute_sr_wm()
1596 if (INTEL_INFO(dev)->gen >= 8) in ilk_display_fifo_size()
1598 else if (INTEL_INFO(dev)->gen >= 7) in ilk_display_fifo_size()
1607 if (INTEL_INFO(dev)->gen >= 8) in ilk_plane_wm_reg_max()
1610 else if (INTEL_INFO(dev)->gen >= 7) in ilk_plane_wm_reg_max()
1624 if (INTEL_INFO(dev)->gen >= 7) in ilk_cursor_wm_reg_max()
1632 if (INTEL_INFO(dev)->gen >= 8) in ilk_fbc_wm_reg_max()
1653 fifo_size /= INTEL_INFO(dev)->num_pipes; in ilk_plane_wm_max()
1660 if (INTEL_INFO(dev)->gen <= 6) in ilk_plane_wm_max()
1888 } else if (INTEL_INFO(dev)->gen >= 6) { in intel_read_wm_latency()
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Dintel_psr.c168 aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ? in hsw_psr_enable_sink()
170 aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ? in hsw_psr_enable_sink()
178 if (INTEL_INFO(dev)->gen >= 9) { in hsw_psr_enable_sink()
374 if (INTEL_INFO(dev)->gen >= 9) in intel_psr_enable()
Dintel_uncore.c338 INTEL_INFO(dev)->gen >= 9) && in intel_uncore_ellc_detect()
1049 if (INTEL_INFO(dev_priv->dev)->gen <= 5) in intel_uncore_fw_domains_init()
1149 switch (INTEL_INFO(dev)->gen) { in intel_uncore_init()
1151 MISSING_CASE(INTEL_INFO(dev)->gen); in intel_uncore_init()
1233 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) in i915_reg_read_ioctl()
1422 if (INTEL_INFO(dev)->gen >= 6) in intel_gpu_reset()
1430 else if (INTEL_INFO(dev)->gen >= 3) in intel_gpu_reset()
Dintel_lvds.c122 if (INTEL_INFO(dev)->gen < 4) { in intel_lvds_get_config()
191 if (INTEL_INFO(dev)->gen == 4) { in intel_pre_enable_lvds()
293 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { in intel_lvds_compute_config()
896 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) in intel_lvds_supported()
Dintel_crt.c164 if (INTEL_INFO(dev)->gen >= 5) in intel_crt_set_dpms()
240 if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) in intel_crt_dpms()
715 else if (INTEL_INFO(dev)->gen < 4) in intel_crt_detect()
778 if (INTEL_INFO(dev)->gen >= 5) { in intel_crt_reset()
Di915_gem_render_state.c52 so->gen = INTEL_INFO(dev)->gen; in render_state_init()
Dintel_fbdev.c498 num_connectors_enabled < INTEL_INFO(dev)->num_pipes) { in intel_fb_initial_config()
692 if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0)) in intel_fbdev_init()
705 INTEL_INFO(dev)->num_pipes, 4); in intel_fbdev_init()
Di915_drv.c442 if (INTEL_INFO(dev)->num_pipes == 0) { in intel_detect_pch()
508 if (INTEL_INFO(dev)->gen < 6) in i915_semaphore_is_enabled()
524 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) in i915_semaphore_is_enabled()
661 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6)) in i915_drm_suspend_late()
899 if (INTEL_INFO(dev)->gen > 5) in i915_reset()
Dintel_panel.c331 if (INTEL_INFO(dev)->gen >= 4) in intel_gmch_panel_fitting()
345 if (INTEL_INFO(dev)->gen >= 4) in intel_gmch_panel_fitting()
361 if (INTEL_INFO(dev)->gen >= 4) in intel_gmch_panel_fitting()
372 if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18) in intel_gmch_panel_fitting()
508 if (INTEL_INFO(dev)->gen < 4) in i9xx_get_backlight()
1361 if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9)) { in intel_panel_init_backlight_funcs()
Di915_gem.c1233 if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { in __i915_wait_request()
1776 if (INTEL_INFO(dev)->gen >= 4 || in i915_gem_get_gtt_size()
1781 if (INTEL_INFO(dev)->gen == 3) in i915_gem_get_gtt_size()
1807 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || in i915_gem_get_gtt_alignment()
3063 if (INTEL_INFO(dev)->gen >= 6) { in i965_write_fence_reg()
3215 else if (INTEL_INFO(dev)->gen >= 4) in i915_gem_write_fence()
3749 if (INTEL_INFO(dev)->gen < 6) { in i915_gem_object_set_cache_level()
4662 if (INTEL_INFO(dev)->gen < 5 || in i915_gem_init_swizzling()
4786 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) in i915_gem_init_hw()
4804 } else if (INTEL_INFO(dev)->gen >= 7) { in i915_gem_init_hw()
[all …]
Dintel_dp.c1160 (INTEL_INFO(dev)->gen >= 9)) in intel_dp_source_supports_hbr2()
1169 if (INTEL_INFO(dev)->gen >= 9) { in intel_dp_source_rates()
2315 if (INTEL_INFO(dev)->gen < 5) in intel_disable_dp()
2886 if (INTEL_INFO(dev)->gen >= 9) { in intel_dp_voltage_max()
2906 if (INTEL_INFO(dev)->gen >= 9) { in intel_dp_pre_emphasis_max()
3418 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { in intel_dp_set_signal_levels()
5041 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { in intel_dp_set_drrs_state()
5053 } else if (INTEL_INFO(dev)->gen > 6) { in intel_dp_set_drrs_state()
5318 if (INTEL_INFO(dev)->gen <= 6) { in intel_dp_drrs_init()
5465 if (INTEL_INFO(dev)->gen >= 9) in intel_dp_init_connector()
[all …]
Dintel_sdvo.c1259 if (INTEL_INFO(dev)->gen >= 4) { in intel_sdvo_pre_enable()
1265 if (INTEL_INFO(dev)->gen < 5) in intel_sdvo_pre_enable()
1288 if (INTEL_INFO(dev)->gen >= 4) { in intel_sdvo_pre_enable()
1298 INTEL_INFO(dev)->gen < 5) in intel_sdvo_pre_enable()
2423 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { in intel_sdvo_add_hdmi_properties()
Dintel_audio.c459 } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) { in intel_init_audio()
Dintel_ddi.c886 if (INTEL_INFO(dev)->gen <= 8) in intel_ddi_clock_get()
1581 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9) in intel_ddi_pre_enable()
1655 if (port == PORT_A && INTEL_INFO(dev)->gen < 9) in intel_enable_ddi()
Dintel_sprite.c1202 if (INTEL_INFO(dev)->gen < 5) in intel_plane_init()
1216 switch (INTEL_INFO(dev)->gen) { in intel_plane_init()
Dintel_overlay.c876 if (INTEL_INFO(dev)->gen >= 4) { in update_pfit_vscale_ratio()
1040 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) in intel_panel_fitter_pipe()
Di915_sysfs.c653 else if (INTEL_INFO(dev)->gen >= 6) in i915_setup_sysfs()
Dintel_drv.h807 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; in intel_num_planes()
Dintel_bios.c396 switch (INTEL_INFO(dev)->gen) { in intel_bios_ssc_frequency()
Dintel_tv.c1110 if (INTEL_INFO(dev)->gen >= 4) in intel_tv_pre_enable()
Dintel_hdmi.c927 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) in hdmi_portclock_limit()