Searched refs:HCLK (Results 1 - 65 of 65) sorted by relevance

/linux-4.1.27/arch/arm/mach-lpc32xx/
H A Dpm.c23 * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
24 * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
28 * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
59 * HCLK PLL state is restored
H A Dsuspend.S92 @ Save HCLK PLL state and disable HCLK PLL
108 @ Restore original HCLK PLL value and wait for PLL lock
H A Dclock.c51 * The CPU and chip bus rates are derived from the HCLK PLL, which can
53 * rates (PCLK and HCLK) are generated from dividers based on the HCLK
54 * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
55 * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
56 * level clocks are based on either HCLK or PCLK, but have their own
60 * The HCLK PLL is clocked from SYSCLK, which can be derived from the
75 * the HCLK PLL to be used as another system clock that can be routed
79 * - HCLK and PCLK rates cannot be changed as part of this driver.
81 * block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
229 * Setup the HCLK PLL with a PLL structure
1247 * Setup muxed SYSCLK for HCLK PLL base -this selects the clk_init()
1261 /* Compute HCLK and PCLK bus rates */ clk_init()
1274 printk(KERN_ERR "Error enabling system HCLK and PCLK\n"); clk_init()
/linux-4.1.27/arch/arm/plat-samsung/include/plat/
H A Dcpu-freq.h24 * @hclk_tns: HCLK cycle time in 10ths of nano-seconds.
25 * @hclk: The HCLK frequency in Hz.
75 * @h_divisor: Divisor from FCLK to HCLK.
/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dsamsung,s3c64xx-clock.h30 #define HCLK 8 macro
33 /* HCLK bus clocks. */
H A Ds3c2410.h28 #define HCLK 5 macro
H A Ds3c2412.h30 #define HCLK 7 macro
H A Ds3c2443.h27 #define HCLK 5 macro
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dsamsung,s3c64xx-clock.h30 #define HCLK 8 macro
33 /* HCLK bus clocks. */
H A Ds3c2410.h28 #define HCLK 5 macro
H A Ds3c2412.h30 #define HCLK 7 macro
H A Ds3c2443.h27 #define HCLK 5 macro
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dsamsung,s3c64xx-clock.h30 #define HCLK 8 macro
33 /* HCLK bus clocks. */
H A Ds3c2410.h28 #define HCLK 5 macro
H A Ds3c2412.h30 #define HCLK 7 macro
H A Ds3c2443.h27 #define HCLK 5 macro
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dsamsung,s3c64xx-clock.h30 #define HCLK 8 macro
33 /* HCLK bus clocks. */
H A Ds3c2410.h28 #define HCLK 5 macro
H A Ds3c2412.h30 #define HCLK 7 macro
H A Ds3c2443.h27 #define HCLK 5 macro
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dsamsung,s3c64xx-clock.h30 #define HCLK 8 macro
33 /* HCLK bus clocks. */
H A Ds3c2410.h28 #define HCLK 5 macro
H A Ds3c2412.h30 #define HCLK 7 macro
H A Ds3c2443.h27 #define HCLK 5 macro
/linux-4.1.27/include/dt-bindings/clock/
H A Dsamsung,s3c64xx-clock.h30 #define HCLK 8 macro
33 /* HCLK bus clocks. */
H A Ds3c2410.h28 #define HCLK 5 macro
H A Ds3c2412.h30 #define HCLK 7 macro
H A Ds3c2443.h27 #define HCLK 5 macro
/linux-4.1.27/arch/arm/mach-s3c24xx/
H A Dcpufreq-utils.c42 * This should work for HCLK up to 133MHz and refresh period up s3c2410_cpufreq_setrefresh()
H A Diotiming-s3c2410.c82 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
85 * HCLK.
98 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
146 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
265 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
277 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
H A Dmach-qt2410.c115 .pixclock = 40000, /* HCLK/4 */
137 .pixclock = 40000, /* HCLK/4 */
159 .pixclock = 100000, /* HCLK/10 */
H A Dmach-at2440evb.c161 .pixclock = 33333, /* HCLK 60 MHz, divisor 2 */
H A Dmach-osiris-dvs.c48 /* at the moment, we assume ARMCLK = HCLK => DVS */ is_dvs()
H A Dmach-smdk2440.c118 .pixclock = 166667, /* HCLK 60 MHz, divisor 10 */
H A Dmach-amlm5900.c181 .pixclock = 680000, /* HCLK = 100MHz */
H A Diotiming-s3c2412.c273 * This should work for HCLK up to 133MHz and refresh period up s3c2412_cpufreq_setrefresh()
H A Dmach-n30.c520 * GPH9 CLKOUT0 HCLK -- unknown use n30_hwinit()
/linux-4.1.27/arch/arm/mach-mv78xx0/
H A Dcommon.c52 * HCLK tick rate is configured by DEV_D[7:5] pins. get_hclk()
71 panic("unknown HCLK PLL setting: %.8x\n", get_hclk()
93 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK get_pclk_l2clk()
405 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); mv78xx0_init()
/linux-4.1.27/drivers/clk/mvebu/
H A Darmada-38x.c22 * SAR[14:10] : Ratios between PCLK0, NBCLK, HCLK and DRAM clocks
H A Darmada-39x.c23 * SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
/linux-4.1.27/include/video/
H A Dkyro.h33 u32 HCLK; /* Hor Clock */ member in struct:kyrofb_info
/linux-4.1.27/drivers/clk/samsung/
H A Dclk-s3c2410.c152 ALIAS(HCLK, NULL, "hclk"),
206 DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
275 MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
H A Dclk-s3c2412.c112 DIV(HCLK, "hclk", "armdiv", CLKDIVN, 0, 2),
204 ALIAS(HCLK, NULL, "hclk"),
H A Dclk-s3c2443.c149 DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d),
194 ALIAS(HCLK, NULL, "hclk"),
H A Dclk-s3c64xx.c230 DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
384 ALIAS(HCLK, NULL, "hclk"),
/linux-4.1.27/drivers/mmc/host/
H A Dtoshsd.c78 * SD/MMC cards at full speed (24/20MHz). HCLK (=33MHz PCI clock?) is too high
89 while (ios->clock < HCLK / div) __toshsd_set_ios()
645 mmc->f_min = HCLK / 512; toshsd_probe()
646 mmc->f_max = HCLK; toshsd_probe()
H A Dtoshsd.h15 #define HCLK 33000000 /* 33 MHz (PCI clock) */ macro
H A Dsdhci-msm.c509 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */ sdhci_msm_probe()
/linux-4.1.27/drivers/clk/tegra/
H A Dclk-tegra-super-gen4.c70 /* HCLK */ tegra_sclk_init()
/linux-4.1.27/drivers/cpufreq/
H A Ds3c24xx-cpufreq-debugfs.c88 seq_printf(seq, " HCLK %ld Hz (%lu.%lu ns)\n", info_show()
H A Ds3c2416-cpufreq.c393 pr_err("cpufreq: Unable to obtain HCLK: %d\n", ret); s3c2416_cpufreq_driver_init()
402 pr_err("cpufreq: HCLK not at 133MHz\n"); s3c2416_cpufreq_driver_init()
H A Ds3c2412-cpufreq.c153 * should work for HCLK up to 133MHz and refresh period up to 30usec. s3c2412_cpufreq_setrefresh()
H A Ds3c2440-cpufreq.c73 /* if we are in DVS, we need HCLK to be <= ARMCLK */ s3c2440_cpufreq_calcdivs()
/linux-4.1.27/arch/arm/mach-pxa/
H A Dmxm8x10.c151 GPIO17_2 - HCLK
/linux-4.1.27/include/linux/mfd/
H A Dasic3.h254 #define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */
/linux-4.1.27/drivers/mfd/
H A Dasic3.c758 * when HCLK is stopped. asic3_mmc_enable()
763 /* HCLK 24.576 MHz, BCLK 12.288 MHz: */ asic3_mmc_enable()
/linux-4.1.27/drivers/media/platform/s3c-camif/
H A Dcamif-core.c41 /* HCLK CAMIF clock */
/linux-4.1.27/drivers/clk/
H A Dclk-nomadik.c545 * The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4. of_nomadik_hclk_setup()
/linux-4.1.27/drivers/video/fbdev/kyro/
H A Dfbdev.c503 par->HCLK = (1000000000 + (lineclock / 2)) / lineclock; kyrofb_set_par()
/linux-4.1.27/arch/arm/mach-ep93xx/
H A Dclock.c556 pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", ep93xx_clock_init()
/linux-4.1.27/drivers/ata/
H A Dpata_ep93xx.c165 * of HCLK cycles to hold the data bus after a PIO write operation.
175 * Maximum possible value for HCLK is 100MHz.
/linux-4.1.27/drivers/net/ethernet/cirrus/
H A Dep93xx_eth.c855 ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */ ep93xx_eth_probe()
/linux-4.1.27/arch/mips/cavium-octeon/
H A Docteon-platform.c133 /* Step 3: Configure the reference clock, PHY, and HCLK */ octeon2_usb_clocks_start()
/linux-4.1.27/drivers/staging/octeon-usb/
H A Docteon-hcd.c780 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and cvmx_usb_initialize()
795 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */ cvmx_usb_initialize()
H A Docteon-hcd.h1584 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to

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