1/* 2 * include/linux/mfd/asic3.h 3 * 4 * Compaq ASIC3 headers. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Copyright 2001 Compaq Computer Corporation. 11 * Copyright 2007-2008 OpenedHand Ltd. 12 */ 13 14#ifndef __ASIC3_H__ 15#define __ASIC3_H__ 16 17#include <linux/types.h> 18 19struct led_classdev; 20struct asic3_led { 21 const char *name; 22 const char *default_trigger; 23 struct led_classdev *cdev; 24}; 25 26struct asic3_platform_data { 27 u16 *gpio_config; 28 unsigned int gpio_config_num; 29 30 unsigned int irq_base; 31 32 unsigned int gpio_base; 33 34 unsigned int clock_rate; 35 36 struct asic3_led *leds; 37}; 38 39#define ASIC3_NUM_GPIO_BANKS 4 40#define ASIC3_GPIOS_PER_BANK 16 41#define ASIC3_NUM_GPIOS 64 42#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6 43 44#define ASIC3_IRQ_LED0 64 45#define ASIC3_IRQ_LED1 65 46#define ASIC3_IRQ_LED2 66 47#define ASIC3_IRQ_SPI 67 48#define ASIC3_IRQ_SMBUS 68 49#define ASIC3_IRQ_OWM 69 50 51#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio)) 52 53#define ASIC3_GPIO_BANK_A 0 54#define ASIC3_GPIO_BANK_B 1 55#define ASIC3_GPIO_BANK_C 2 56#define ASIC3_GPIO_BANK_D 3 57 58#define ASIC3_GPIO(bank, gpio) \ 59 ((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio)) 60#define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf)) 61/* All offsets below are specified with this address bus shift */ 62#define ASIC3_DEFAULT_ADDR_SHIFT 2 63 64#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg) 65#define ASIC3_GPIO_OFFSET(base, reg) \ 66 (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg) 67 68#define ASIC3_GPIO_A_BASE 0x0000 69#define ASIC3_GPIO_B_BASE 0x0100 70#define ASIC3_GPIO_C_BASE 0x0200 71#define ASIC3_GPIO_D_BASE 0x0300 72 73#define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4) 74#define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \ 75 (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4))) 76#define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio)) 77#define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100)) 78#define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100)) 79 80#define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */ 81#define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */ 82#define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */ 83#define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */ 84#define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */ 85#define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */ 86#define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */ 87#define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */ 88#define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */ 89#define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */ 90#define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */ 91#define ASIC3_GPIO_SLEEP_CONF 0x2c /* 92 * R/W bit 1: autosleep 93 * 0: disable gposlpout in normal mode, 94 * enable gposlpout in sleep mode. 95 */ 96#define ASIC3_GPIO_STATUS 0x30 /* R Pin status */ 97 98/* 99 * ASIC3 GPIO config 100 * 101 * Bits 0..6 gpio number 102 * Bits 7..13 Alternate function 103 * Bit 14 Direction 104 * Bit 15 Initial value 105 * 106 */ 107#define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f) 108#define ASIC3_CONFIG_GPIO_ALT(config) (((config) & (0x7f << 7)) >> 7) 109#define ASIC3_CONFIG_GPIO_DIR(config) ((config & (1 << 14)) >> 14) 110#define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15) 111#define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \ 112 | (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \ 113 | (((init) & 0x1) << 15)) 114#define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \ 115 ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init)) 116#define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \ 117 ASIC3_CONFIG_GPIO((gpio), 0, 1, (init)) 118 119/* 120 * Alternate functions 121 */ 122#define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0) 123#define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0) 124#define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0) 125#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 0, 0) 126#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 0, 0) 127#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 0, 0) 128#define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0) 129#define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0) 130#define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0) 131#define ASIC3_GPIOC5_SPI_CLK ASIC3_CONFIG_GPIO(37, 1, 1, 0) 132#define ASIC3_GPIOC5_nCIOW ASIC3_CONFIG_GPIO(37, 1, 1, 0) 133#define ASIC3_GPIOC6_nCIOR ASIC3_CONFIG_GPIO(38, 1, 1, 0) 134#define ASIC3_GPIOC7_nPCE_1 ASIC3_CONFIG_GPIO(39, 1, 0, 0) 135#define ASIC3_GPIOC8_nPCE_2 ASIC3_CONFIG_GPIO(40, 1, 0, 0) 136#define ASIC3_GPIOC9_nPOE ASIC3_CONFIG_GPIO(41, 1, 0, 0) 137#define ASIC3_GPIOC10_nPWE ASIC3_CONFIG_GPIO(42, 1, 0, 0) 138#define ASIC3_GPIOC11_PSKTSEL ASIC3_CONFIG_GPIO(43, 1, 0, 0) 139#define ASIC3_GPIOC12_nPREG ASIC3_CONFIG_GPIO(44, 1, 0, 0) 140#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0) 141#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0) 142#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0) 143#define ASIC3_GPIOD4_CF_nCD ASIC3_CONFIG_GPIO(52, 1, 0, 0) 144#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0) 145#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0) 146#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0) 147 148 149#define ASIC3_SPI_Base 0x0400 150#define ASIC3_SPI_Control 0x0000 151#define ASIC3_SPI_TxData 0x0004 152#define ASIC3_SPI_RxData 0x0008 153#define ASIC3_SPI_Int 0x000c 154#define ASIC3_SPI_Status 0x0010 155 156#define SPI_CONTROL_SPR(clk) ((clk) & 0x0f) /* Clock rate */ 157 158#define ASIC3_PWM_0_Base 0x0500 159#define ASIC3_PWM_1_Base 0x0600 160#define ASIC3_PWM_TimeBase 0x0000 161#define ASIC3_PWM_PeriodTime 0x0004 162#define ASIC3_PWM_DutyTime 0x0008 163 164#define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */ 165#define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */ 166 167#define ASIC3_NUM_LEDS 3 168#define ASIC3_LED_0_Base 0x0700 169#define ASIC3_LED_1_Base 0x0800 170#define ASIC3_LED_2_Base 0x0900 171#define ASIC3_LED_TimeBase 0x0000 /* R/W 7 bits */ 172#define ASIC3_LED_PeriodTime 0x0004 /* R/W 12 bits */ 173#define ASIC3_LED_DutyTime 0x0008 /* R/W 12 bits */ 174#define ASIC3_LED_AutoStopCount 0x000c /* R/W 16 bits */ 175 176/* LED TimeBase bits - match ASIC2 */ 177#define LED_TBS 0x0f /* Low 4 bits sets time base, max = 13 */ 178 /* Note: max = 5 on hx4700 */ 179 /* 0: maximum time base */ 180 /* 1: maximum time base / 2 */ 181 /* n: maximum time base / 2^n */ 182 183#define LED_EN (1 << 4) /* LED ON/OFF 0:off, 1:on */ 184#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */ 185#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */ 186 187#define ASIC3_CLOCK_BASE 0x0A00 188#define ASIC3_CLOCK_CDEX 0x00 189#define ASIC3_CLOCK_SEL 0x04 190 191#define CLOCK_CDEX_SOURCE (1 << 0) /* 2 bits */ 192#define CLOCK_CDEX_SOURCE0 (1 << 0) 193#define CLOCK_CDEX_SOURCE1 (1 << 1) 194#define CLOCK_CDEX_SPI (1 << 2) 195#define CLOCK_CDEX_OWM (1 << 3) 196#define CLOCK_CDEX_PWM0 (1 << 4) 197#define CLOCK_CDEX_PWM1 (1 << 5) 198#define CLOCK_CDEX_LED0 (1 << 6) 199#define CLOCK_CDEX_LED1 (1 << 7) 200#define CLOCK_CDEX_LED2 (1 << 8) 201 202/* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */ 203#define CLOCK_CDEX_SD_HOST (1 << 9) /* R/W: SD host clock source */ 204#define CLOCK_CDEX_SD_BUS (1 << 10) /* R/W: SD bus clock source ctrl */ 205#define CLOCK_CDEX_SMBUS (1 << 11) 206#define CLOCK_CDEX_CONTROL_CX (1 << 12) 207 208#define CLOCK_CDEX_EX0 (1 << 13) /* R/W: 32.768 kHz crystal */ 209#define CLOCK_CDEX_EX1 (1 << 14) /* R/W: 24.576 MHz crystal */ 210 211#define CLOCK_SEL_SD_HCLK_SEL (1 << 0) /* R/W: SDIO host clock select */ 212#define CLOCK_SEL_SD_BCLK_SEL (1 << 1) /* R/W: SDIO bus clock select */ 213 214/* R/W: INT clock source control (32.768 kHz) */ 215#define CLOCK_SEL_CX (1 << 2) 216 217 218#define ASIC3_INTR_BASE 0x0B00 219 220#define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */ 221#define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */ 222#define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */ 223#define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */ 224 225#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */ 226#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */ 227#define ASIC3_INTMASK_MASK0 (1 << 2) 228#define ASIC3_INTMASK_MASK1 (1 << 3) 229#define ASIC3_INTMASK_MASK2 (1 << 4) 230#define ASIC3_INTMASK_MASK3 (1 << 5) 231#define ASIC3_INTMASK_MASK4 (1 << 6) 232#define ASIC3_INTMASK_MASK5 (1 << 7) 233 234#define ASIC3_INTR_PERIPHERAL_A (1 << 0) 235#define ASIC3_INTR_PERIPHERAL_B (1 << 1) 236#define ASIC3_INTR_PERIPHERAL_C (1 << 2) 237#define ASIC3_INTR_PERIPHERAL_D (1 << 3) 238#define ASIC3_INTR_LED0 (1 << 4) 239#define ASIC3_INTR_LED1 (1 << 5) 240#define ASIC3_INTR_LED2 (1 << 6) 241#define ASIC3_INTR_SPI (1 << 7) 242#define ASIC3_INTR_SMBUS (1 << 8) 243#define ASIC3_INTR_OWM (1 << 9) 244 245#define ASIC3_INTR_CPS(x) ((x)&0x0f) /* 4 bits, max 14 */ 246#define ASIC3_INTR_CPS_SET (1 << 4) /* Time base enable */ 247 248 249/* Basic control of the SD ASIC */ 250#define ASIC3_SDHWCTRL_BASE 0x0E00 251#define ASIC3_SDHWCTRL_SDCONF 0x00 252 253#define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */ 254#define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */ 255#define ASIC3_SDHWCTRL_PCLR (1 << 2) /* All registers of SDIO cleared */ 256#define ASIC3_SDHWCTRL_LEVCD (1 << 3) /* SD card detection: 0:low */ 257 258/* SD card write protection: 0=high */ 259#define ASIC3_SDHWCTRL_LEVWP (1 << 4) 260#define ASIC3_SDHWCTRL_SDLED (1 << 5) /* SD card LED signal 0=disable */ 261 262/* SD card power supply ctrl 1=enable */ 263#define ASIC3_SDHWCTRL_SDPWR (1 << 6) 264 265#define ASIC3_EXTCF_BASE 0x1100 266 267#define ASIC3_EXTCF_SELECT 0x00 268#define ASIC3_EXTCF_RESET 0x04 269 270#define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */ 271#define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */ 272#define ASIC3_EXTCF_SMOD2 (1 << 2) /* slot number of mode 2 */ 273#define ASIC3_EXTCF_OWM_EN (1 << 4) /* enable onewire module */ 274#define ASIC3_EXTCF_OWM_SMB (1 << 5) /* OWM bus selection */ 275#define ASIC3_EXTCF_OWM_RESET (1 << 6) /* ?? used by OWM and CF */ 276#define ASIC3_EXTCF_CF0_SLEEP_MODE (1 << 7) /* CF0 sleep state */ 277#define ASIC3_EXTCF_CF1_SLEEP_MODE (1 << 8) /* CF1 sleep state */ 278#define ASIC3_EXTCF_CF0_PWAIT_EN (1 << 10) /* CF0 PWAIT_n control */ 279#define ASIC3_EXTCF_CF1_PWAIT_EN (1 << 11) /* CF1 PWAIT_n control */ 280#define ASIC3_EXTCF_CF0_BUF_EN (1 << 12) /* CF0 buffer control */ 281#define ASIC3_EXTCF_CF1_BUF_EN (1 << 13) /* CF1 buffer control */ 282#define ASIC3_EXTCF_SD_MEM_ENABLE (1 << 14) 283#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */ 284 285/********************************************* 286 * The Onewire interface (DS1WM) is handled 287 * by the ds1wm driver. 288 * 289 *********************************************/ 290 291#define ASIC3_OWM_BASE 0xC00 292 293/***************************************************************************** 294 * The SD configuration registers are at a completely different location 295 * in memory. They are divided into three sets of registers: 296 * 297 * SD_CONFIG Core configuration register 298 * SD_CTRL Control registers for SD operations 299 * SDIO_CTRL Control registers for SDIO operations 300 * 301 *****************************************************************************/ 302#define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */ 303#define ASIC3_SD_CONFIG_SIZE 0x0200 /* Assumes 32 bit addressing */ 304#define ASIC3_SD_CTRL_BASE 0x1000 305#define ASIC3_SDIO_CTRL_BASE 0x1200 306 307#define ASIC3_MAP_SIZE_32BIT 0x2000 308#define ASIC3_MAP_SIZE_16BIT 0x1000 309 310/* Functions needed by leds-asic3 */ 311 312struct asic3; 313extern void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 val); 314extern u32 asic3_read_register(struct asic3 *asic, unsigned int reg); 315 316#endif /* __ASIC3_H__ */ 317