Searched refs:FPGA (Results 1 - 200 of 242) sorted by relevance

12

/linux-4.1.27/arch/sh/boards/mach-highlander/
H A Dirq-r7785rp.c20 /* FPGA specific interrupt sources */
74 __raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */ highlander_plat_irq_setup()
76 /* Setup the FPGA IRL */ highlander_plat_irq_setup()
77 __raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */ highlander_plat_irq_setup()
78 __raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */ highlander_plat_irq_setup()
79 __raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */ highlander_plat_irq_setup()
80 __raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */ highlander_plat_irq_setup()
81 __raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */ highlander_plat_irq_setup()
82 __raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */ highlander_plat_irq_setup()
H A Dirq-r7780mp.c23 SCIF1, /* FPGA SCIF1 */
24 SCIF0, /* FPGA SCIF0 */
H A Dsetup.c150 /* R7785RP has a slightly more sensible FPGA.. */
363 "FPGA version: %d (revision %d)\n", highlander_setup()
/linux-4.1.27/arch/sh/boards/mach-se/7780/
H A Dirq.c26 /* enable all interrupt at FPGA */ init_se7780_IRQ()
30 /* enable all interrupt at FPGA */ init_se7780_IRQ()
33 /* set FPGA INTSEL register */ init_se7780_IRQ()
34 /* FPGA + 0x06 */ init_se7780_IRQ()
38 /* FPGA + 0x08 */ init_se7780_IRQ()
44 /* FPGA + 0x0A */ init_se7780_IRQ()
53 * FPGA PCISEL register initialize init_se7780_IRQ()
/linux-4.1.27/arch/sh/boards/mach-sdk7786/
H A Dirq.c2 * SDK7786 FPGA IRQ Controller Support.
37 /* Clear FPGA interrupt status registers */ sdk7786_init_irq()
41 /* Unmask FPGA interrupts */ sdk7786_init_irq()
H A Dsram.c2 * SDK7786 FPGA SRAM Support.
29 /* Enable FPGA SRAM */ fpga_sram_init()
39 pr_err("FPGA memory unmapped.\n"); fpga_sram_init()
50 * The FPGA SRAM resides in translatable physical space, so set fpga_sram_init()
55 pr_err("Failed remapping FPGA memory.\n"); fpga_sram_init()
59 pr_info("Adding %dKiB of FPGA memory at 0x%08lx-0x%08lx " fpga_sram_init()
H A Dfpga.c2 * SDK7786 FPGA Support.
20 * The FPGA can be mapped in any of the generally available areas,
23 * Once the FPGA is located, the rest of the mapping data for the other
33 * Iterate over all of the areas where the FPGA could be mapped. sdk7786_fpga_probe()
61 panic("FPGA detection failed.\n"); sdk7786_fpga_init()
H A Dsetup.c125 * Hand over I2C control to the FPGA. sdk7786_i2c_setup()
154 * FPGA-driven PCIe clocks
159 * to the same bit position as the oscillator bit for earlier FPGA
163 * off through the FPGA along with the PCI slots, we simply leave them in
211 * Setup the FPGA clocks. sdk7786_clk_init()
215 pr_err("FPGA clock registration failed\n"); sdk7786_clk_init()
235 * wait a bit until we've been shut off. Even though newer FPGA sdk7786_power_off()
H A Dgpio.c2 * SDK7786 FPGA USRGPIR Support.
H A Dnmi.c2 * SDK7786 FPGA NMI Support.
/linux-4.1.27/arch/sh/include/mach-common/mach/
H A Dmicrodev.h19 * controller (INTC) on the CPU-board FPGA. should be noted that there
20 * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
25 #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
26 #define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
27 #define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
28 #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */
29 #define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */
31 #define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */
32 #define MICRODEV_FPGA_INTSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */
33 #define MICRODEV_FPGA_INTREQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */
50 * The following are the IRQ numbers for the INTC on the FPGA for
52 * FPGA.
H A Dsdk7780.h36 /* FPGA base address */
56 #define FPGA_FPVERR (PA_FPGA + 0x0D0) /* FPGA version */
57 #define FPGA_FPDATER (PA_FPGA + 0x0E0) /* FPGA date */
H A Durquell.h46 #define FPVERR_OFS 0x0150 /* FPGA Version register */
47 #define FPDATER_OFS 0x0160 /* FPGA Date register */
48 #define FPYEARR_OFS 0x0170 /* FPGA Year register */
H A Dsh7763rdp.h39 /* FPGA */
H A Dr2d.h14 #define PA_BCR 0xa4000000 /* FPGA */
37 #define PA_VERREG 0xa4000032 /* FPGA Version Register */
H A Dhighlander.h9 #define PA_BCR 0xa4000000 /* FPGA */
66 #define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
76 #define PA_BCR 0xa5000000 /* FPGA */
118 #define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
130 #define PA_BCR 0xa4000000 /* FPGA */
/linux-4.1.27/drivers/misc/
H A Dlattice-ecp3-config.c23 * The JTAG ID's of the supported FPGA's. The ID is 32bit wide
29 /* FPGA commands */
45 #define FPGA_CLEAR_TIMEOUT 5000 /* max. 5000ms for FPGA clear */
97 /* Trying to speak with the FPGA via SPI... */ firmware_load()
101 dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", jedec_id); firmware_load()
109 "Error: No supported FPGA detected (JEDEC_ID=%08x)!\n", firmware_load()
114 dev_info(&spi->dev, "FPGA %s detected\n", ecp3_dev[i].name); firmware_load()
119 dev_dbg(&spi->dev, "FPGA Status=%08x\n", status); firmware_load()
146 * Wait for FPGA memory to become cleared firmware_load()
160 "Error: Timeout waiting for FPGA to clear (status=%08x)!\n", firmware_load()
166 dev_info(&spi->dev, "Configuring the FPGA...\n"); firmware_load()
175 dev_dbg(&spi->dev, "FPGA Status=%08x\n", status); firmware_load()
179 dev_info(&spi->dev, "FPGA successfully configured!\n"); firmware_load()
181 dev_info(&spi->dev, "FPGA not configured (DONE not set)\n"); firmware_load()
214 dev_info(&spi->dev, "FPGA bitstream configuration driver registered\n"); lattice_ecp3_probe()
248 MODULE_DESCRIPTION("Lattice ECP3 FPGA configuration via SPI");
/linux-4.1.27/arch/mn10300/unit-asb2364/
H A Dirq-fpga.c1 /* ASB2364 FPGA interrupt multiplexing
18 * FPGA PIC operations
55 * FPGA PIC interrupt handler
74 * Define an interrupt action for each FPGA PIC output
85 * Initialise the FPGA's PIC
106 /* the FPGA drives the XIRQ1 input on the CPU PIC */ irq_fpga_init()
H A Dunit-init.c46 /* Attempt to reset the FPGA attached peripherals */ unit_init()
63 /* XIRQ[1]: LAN, UART, I2C, USB, PCI, FPGA */ unit_init()
/linux-4.1.27/arch/arm/mach-omap1/
H A Dfpga.c4 * Interrupt handler for OMAP-1510 Innovator FPGA
11 * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
66 /* Don't need to explicitly ACK FPGA interrupts */ fpga_ack_irq()
110 .name = "FPGA-ack",
118 .name = "FPGA",
125 * All of the FPGA interrupt request inputs except for the touchscreen are
128 * status register from the FPGA. The edge-sensitive interrupt inputs
131 * interrupt input is masked in the FPGA, which results in a missed
135 * mask_ack routine for all of the FPGA interrupts has been changed from
136 * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt
137 * being serviced is left unmasked. We can do this because the FPGA cascade
142 * on other FPGA interrupts as well, but any drivers that explicitly mask
165 * All FPGA interrupts except the touchscreen are omap1510_fpga_init_irq()
176 * The FPGA interrupt line is connected to GPIO13. Claim this pin for omap1510_fpga_init_irq()
182 res = gpio_request(13, "FPGA irq"); omap1510_fpga_init_irq()
H A Dfpga.h2 * Interrupt handler for OMAP-1510 FPGA
9 * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
22 * H2/P2 Debug board FPGA
25 /* maps in the FPGA registers and the ETHR registers */
31 #define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
H A Dboard-innovator.c11 * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
164 /* Only FPGA needs to be mapped here. All others are done with ioremap */
229 /* FPGA (bus "10") CS0 has an ads7846e */
349 * - mmc_get_cover_state that uses FPGA F4 UIO43
443 udelay(10); /* Delay needed for FPGA */ innovator_map_io()
445 /* Dump the Innovator FPGA rev early - useful info for support. */ innovator_map_io()
446 pr_debug("Innovator FPGA Rev %d.%d Board Rev %d\n", innovator_map_io()
H A DMakefile51 # Innovator-1510 FPGA
H A Dboard-perseus2.c304 /* Only FPGA needs to be mapped here. All others are done with ioremap */
H A Dboard-fsample.c336 /* Only FPGA needs to be mapped here. All others are done with ioremap */
H A Dboard-h2.c11 * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
/linux-4.1.27/arch/frv/kernel/
H A Dirq-mb93093.c1 /* irq-mb93093.c: MB93093 FPGA interrupt handling
35 * off-CPU FPGA PIC operations
78 * FPGA PIC interrupt handler
102 * define an interrupt action for each FPGA PIC output
103 * - use dev_id to indicate the FPGA PIC input to output mappings
114 * initialise the motherboard FPGA's PIC
127 /* the FPGA drives external IRQ input #2 on the CPU PIC */ fpga_init()
H A Dirq-mb93091.c1 /* irq-mb93091.c: MB93091 FPGA interrupt handling
36 * on-motherboard FPGA PIC operations
80 * FPGA PIC interrupt handler
104 * define an interrupt action for each FPGA PIC output
105 * - use dev_id to indicate the FPGA PIC input to output mappings
135 * initialise the motherboard FPGA's PIC
152 /* the FPGA drives the first four external IRQ inputs on the CPU PIC */ fpga_init()
H A Dpm-mb93093.c32 /* mask all but FPGA interrupt sources. */ mb93093_power_switch_setup()
H A Dsetup.c439 /* the FPGA on the CB70 has extra registers determine_cpu()
440 * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is determine_cpu()
539 * through the FPGA. */ determine_clocks()
553 //__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA determine_clocks()
/linux-4.1.27/arch/sh/boards/mach-se/7722/
H A Dirq.c2 * Hitachi UL SolutionEngine 7722 FPGA IRQ Support.
11 #define DRV_NAME "SE7722-FPGA"
100 * Initialize FPGA IRQs
111 * All FPGA IRQs disabled by default init_se7722_IRQ()
H A Dsetup.c159 __raw_writew(0x010D, FPGA_OUT); /* FPGA */ se7722_setup()
/linux-4.1.27/arch/sh/drivers/pci/
H A Dfixups-sdk7786.c2 * SDK7786 FPGA PCIe mux handling
18 * The SDK7786 FPGA supports mangling of most of the slots in some way or
23 * Misconfigurations can be detected through the FPGA via the slot
/linux-4.1.27/arch/arm/mach-shmobile/
H A Dboard-bockw-reference.c28 #define FPGA 0x18200000 macro
45 fpga = ioremap_nocache(FPGA, SZ_1M); bockw_init()
50 * IRQ0/1 is cascaded interrupt from FPGA. bockw_init()
H A Dboard-bockw.c43 #define FPGA 0x18200000 macro
83 * SW54: 1pin (ak4554 FPGA control)
85 * SW60: 1pin (ak4554 FPGA control)
653 fpga = ioremap_nocache(FPGA, SZ_1M); bockw_init()
658 * IRQ0/1 is cascaded interrupt from FPGA. bockw_init()
/linux-4.1.27/drivers/char/xillybus/
H A Dxillybus.h6 * Header file for the Xillybus FPGA/host framework.
41 * Read-write confusion: wr_* and rd_* notation sticks to FPGA view, so
42 * wr_* buffers are those consumed by read(), since the FPGA writes to them
52 struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */
73 struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */
H A Dxillybus_core.c6 * Driver for the Xillybus FPGA/host framework.
8 * This driver interfaces with a special IP core in an FPGA, setting up
284 "FPGA reported a fatal error. This means that the low-level communication with the device has failed. This hardware problem is most likely unrelated to Xillybus (neither kernel module nor FPGA core), but reports are still welcome. All I/O is aborted.\n"); xillybus_isr()
773 * Tell FPGA the buffer is done with. It's an xillybus_read()
774 * atomic operation to the FPGA, so what xillybus_read()
805 * Nonblocking read: The "ready" flag tells us that the FPGA xillybus_read()
808 * where we ask for the FPGA to send all it has, and wait xillybus_read()
956 * So tell the FPGA to send anything it has or gets. xillybus_read()
1624 * the last one the FPGA submitted. Note that xillybus_release()
1749 * the FPGA, and users expecting select() to wake up, which it may xillybus_poll()
1959 * endianness this processor is using, so the FPGA can swap words as xillybus_endpoint_discovery()
1993 dev_err(endpoint->dev, "No response from FPGA. Aborting.\n"); xillybus_endpoint_discovery()
H A Dxillybus_of.c6 * Driver for the Xillybus FPGA/host framework using Open Firmware.
H A Dxillybus_pcie.c6 * Driver for the Xillybus FPGA/host framework using PCI Express.
/linux-4.1.27/arch/sh/boards/mach-se/7206/
H A Dirq.c39 /* FPGA mask set */ disable_se7206_irq()
71 /* FPGA mask reset */ enable_se7206_irq()
98 /* FPGA isr clear */ eoi_se7206_irq()
119 .name = "SE7206-FPGA",
144 /* FPGA System register setup*/ init_se7206_IRQ()
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A Dballoon3.h33 /* FPGA / CPLD registers for CF socket */
36 /* FPGA / CPLD version register */
38 /* FPGA / CPLD registers for NAND flash */
109 /* FPGA Interrupt Mask/Acknowledge Register */
113 /* CPLD (and FPGA) interface definitions */
H A Dlubbock.h28 /* FPGA register virtual addresses */
H A Didp.h82 /* FPGA register virtual addresses */
H A Dmainstone.h31 /* board level registers in the FPGA */
/linux-4.1.27/arch/mips/include/asm/mach-pmcs-msp71xx/
H A Dmsp_prom.h59 #define MACHINE_TYPE_POLO_FPGA "POLO-FPGA"
60 #define MACHINE_TYPE_DUET_FPGA "DUET-FPGA"
62 #define MACHINE_TYPE_MSP2000REVB_FPGA "MSP2000REVB-FPGA"
63 #define MACHINE_TYPE_MSP5000_FPGA "MSP5000-FPGA"
64 #define MACHINE_TYPE_MSP4200_FPGA "MSP4200-FPGA"
65 #define MACHINE_TYPE_MSP7100_FPGA "MSP7100-FPGA"
66 #define MACHINE_TYPE_OTHER_FPGA "OTHER-FPGA"
H A Dmsp_regs.h548 #define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */
549 #define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */
/linux-4.1.27/drivers/misc/carma/
H A Dcarma-fpga.c2 * CARMA DATA-FPGA Access Driver
13 * FPGA Memory Dump Format
15 * FPGA #0 control registers (32 x 32-bit words)
16 * FPGA #1 control registers (32 x 32-bit words)
17 * FPGA #2 control registers (32 x 32-bit words)
18 * FPGA #3 control registers (32 x 32-bit words)
20 * FPGA #0 correlation array (NUM_CORL0 correlation blocks)
21 * FPGA #1 correlation array (NUM_CORL1 correlation blocks)
22 * FPGA #2 correlation array (NUM_CORL2 correlation blocks)
23 * FPGA #3 correlation array (NUM_CORL3 correlation blocks)
32 * the FPGA configuration registers. They do not change once the FPGA's
85 * To handle this, the system controller FPGA has the capability to connect the
119 /* FPGA registers */
160 /* FPGA registers and information */
165 /* FPGA Physical Address/Size Information */
430 * fpga_start_addr() - get the physical address a DATA-FPGA
432 * @fpga: the DATA-FPGA number (zero based)
442 * @fpga: the DATA-FPGA number (zero based)
482 /* Add the DATA FPGA registers to the scatterlist */ data_setup_corl_table()
490 /* Add the SYS-FPGA registers to the scatterlist */ data_setup_corl_table()
495 /* Add the FPGA correlation data blocks to the scatterlist */ data_setup_corl_table()
507 * now. It can be reused for every FPGA DATA interrupt data_setup_corl_table()
513 * FPGA Register Access Helpers
548 /* Each buffer starts with the 5 FPGA register areas */ data_calculate_bufsize()
551 /* Read and store the configuration data for each FPGA */ data_calculate_bufsize()
579 dev_dbg(priv->dev, "FPGA %d NUM_CORL: %d\n", i, num_corl); data_calculate_bufsize()
580 dev_dbg(priv->dev, "FPGA %d NUM_PACK: %d\n", i, num_pack); data_calculate_bufsize()
581 dev_dbg(priv->dev, "FPGA %d NUM_LAGS: %d\n", i, num_lags); data_calculate_bufsize()
582 dev_dbg(priv->dev, "FPGA %d NUM_META: %d\n", i, num_meta); data_calculate_bufsize()
583 dev_dbg(priv->dev, "FPGA %d NUM_QCNT: %d\n", i, num_qcnt); data_calculate_bufsize()
584 dev_dbg(priv->dev, "FPGA %d BLK_SIZE: %d\n", i, blk_size); data_calculate_bufsize()
613 * Unhide interrupts by switching to the FPGA interrupt source. At the
614 * same time, clear the DATA-FPGA status registers.
620 /* clear the actual FPGA corl_done interrupt */ data_enable_interrupts()
640 * Complete a DMA transfer from the DATA-FPGA's
663 * If data dumping is still enabled, then clear the FPGA data_dma_cb()
664 * status registers and re-enable FPGA interrupts data_dma_cb()
730 /* Prepare the re-read of the SYS-FPGA block */ data_submit_dma()
737 dev_err(priv->dev, "unable to prep SYS-FPGA DMA\n"); data_submit_dma()
748 dev_err(priv->dev, "unable to submit SYS-FPGA DMA\n"); data_submit_dma()
766 /* detect spurious interrupts via FPGA status */ data_irq()
770 dev_err(priv->dev, "spurious irq detected (FPGA)\n"); data_irq()
896 /* allow the DMA callback to re-enable FPGA interrupts */ data_device_enable()
1106 * FPGA Realtime Data Character Device
1303 /* Check against the FPGA region's physical memory size */ data_mmap()
1332 * DMA Channel #0 is used for the FPGA Programmer, so ignore it dma_filter()
1376 /* Get the physical address of the FPGA registers */ data_of_probe()
1379 dev_err(&op->dev, "Unable to find FPGA physical address\n"); data_of_probe()
1417 /* Drive the GPIO for FPGA IRQ high (no interrupt) */ data_of_probe()
1443 dev_info(&op->dev, "CARMA FPGA Realtime Data Driver Loaded\n"); data_of_probe()
1506 MODULE_DESCRIPTION("CARMA DATA-FPGA Access Driver");
H A Dcarma-fpga-program.c2 * CARMA Board DATA-FPGA Programmer
66 /* FPGA Bitfile */
143 * FPGA Bitfile Helpers
195 * FPGA Register Helpers
278 * FPGA Power Supply Code
291 * Determine if the FPGA power is good for all supplies
305 * Disable the FPGA power supplies
352 * fpga_enable_power_supplies() - enable the DATA-FPGA power supplies
355 * Enable the DATA-FPGA power supplies, waiting up to 1 second for
381 * Determine if the FPGA power supplies are all enabled
395 * Determine if the FPGA's are programmed and running correctly
407 * FPGA Programming Code
470 * fpga_program_cpu() - program the DATA-FPGA's using the CPU
495 /* Write each chunk of the FPGA bitfile to FPGA programmer */ fpga_program_cpu()
520 * fpga_program_dma() - program the DATA-FPGA's using the DMA engine
523 * Program the DATA-FPGA's using the Freescale DMA engine. This requires that
525 * control the entire DMA transaction. The system controller FPGA then
675 * fpga_do_stop() - deconfigure (reset) the DATA-FPGA's
687 /* Pulse the config line to reset the FPGA's */ fpga_do_stop()
719 /* Try to program the FPGA's using DMA */ fpga_do_program()
729 dev_err(priv->dev, "Unable to program FPGA's\n"); fpga_do_program()
736 dev_dbg(priv->dev, "FPGA programming successful\n"); fpga_do_program()
802 /* FPGA bitfiles have an exact size: disallow anything else */ fpga_write()
914 /* Program or Reset the FPGA's */ program_store()
1069 * This driver uses the CTL-CPLD DATA-FPGA power sequencer, and we fpga_of_probe()
1103 /* Reset and stop the FPGA's, just in case */ fpga_of_probe()
1122 dev_info(priv->dev, "CARMA FPGA Programmer: %s rev%s with %s FPGAs\n", fpga_of_probe()
1178 MODULE_DESCRIPTION("CARMA Board DATA-FPGA Programmer");
/linux-4.1.27/drivers/irqchip/
H A Dirq-versatile-fpga.c2 * Support for Versatile FPGA-based IRQ controllers
34 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
87 * Handle each interrupt in a single FPGA IRQ controller. Returns non-zero
107 * Keep iterating over all registered FPGA IRQ controllers until there are
147 pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__); fpga_irq_init()
175 pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs", fpga_irq_init()
/linux-4.1.27/arch/arm/mach-imx/
H A Dmach-qong.c36 /* FPGA defines */
45 /* FPGA control registers */
231 printk(KERN_INFO "Qong FPGA version %d.%d.%d\n", qong_init_fpga()
235 printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based " qong_init_fpga()
240 /* register FPGA-based devices */ qong_init_fpga()
H A Dmach-kzm_arm11_01.c50 * KZM-ARM11-01 Board Control Registers on FPGA
62 * External UART for touch panel on FPGA
68 * KZM-ARM11-01 has an external UART on FPGA
/linux-4.1.27/drivers/gpio/
H A Dgpio-ge.c2 * Driver for GE FPGA based GPIO
16 * Interrupt configuration - interrupts are always generated the FPGA relies on
112 MODULE_DESCRIPTION("GE I/O FPGA GPIO driver");
H A Dgpio-timberdale.c2 * Timberdale FPGA GPIO driver
20 * Timberdale FPGA GPIO
H A Dgpio-generic.c21 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
34 * .this will be used with roll-your-own ASIC/FPGA .` \ /
/linux-4.1.27/arch/sh/boards/mach-se/7343/
H A Dirq.c2 * Hitachi UL SolutionEngine 7343 FPGA IRQ Support.
14 #define DRV_NAME "SE7343-FPGA"
118 * All FPGA IRQs disabled by default init_7343se_IRQ()
H A Dsetup.c166 __raw_writew(0xf900, FPGA_OUT); /* FPGA */ sh7343se_setup()
/linux-4.1.27/drivers/mcb/
H A Dmcb-internal.h30 * @revision: Revison of Chameleon table in FPGA
36 * @filename: Filename of FPGA bitstream
53 * @irq: the position in the FPGA's IRQ controller vector
88 * @irq: the position in the FPGA's IRQ controller vector
/linux-4.1.27/arch/unicore32/include/asm/
H A Dtimex.h18 /* in FPGA, APB clock is 33M, and OST clock is 32K, */
/linux-4.1.27/arch/mn10300/unit-asb2364/include/unit/
H A Dirq.h1 /* ASB2364 FPGA irq numbers
H A Dfpga-regs.h1 /* ASB2364 FPGA registers
H A Dsmsc911x.h26 * Allow the FPGA to be initialised by the SMSC911x driver
/linux-4.1.27/arch/frv/include/asm/
H A Dmb93091-fpga-irqs.h1 /* mb93091-fpga-irqs.h: MB93091 CPU board FPGA IRQs
H A Dmb93093-fpga-irqs.h1 /* mb93093-fpga-irqs.h: MB93093 CPU board FPGA IRQs
H A Ddm9000.h18 #define DM9000_ARCH_IRQ IRQ_CPU_EXTERNAL3 /* XIRQ #3 (shared with FPGA) */
H A Dmb-regs.h144 #define __region_CS2 0x20000000 /* FPGA registers */
/linux-4.1.27/drivers/isdn/hardware/eicon/
H A Ds_4bri.c182 FPGA download
202 DBG_FTL(("FPGA download: start of data header not found")) qBri_check_FPGAsrc()
211 DBG_FTL(("FPGA download: data header corrupted")) qBri_check_FPGAsrc()
233 DBG_FTL(("FPGA download: '%s' file too small (%ld < %ld)", qBri_check_FPGAsrc()
261 DBG_LOG(("FPGA[%s] file %s (%s %s) len %d", qBri_check_FPGAsrc()
319 diva_os_wait(50); /* wait until FPGA finished internal memory clear */ qBri_FPGA_download()
325 DBG_FTL(("FPGA download: acknowledge for FPGA memory clear missing")) qBri_FPGA_download()
331 * put data onto the FPGA qBri_FPGA_download()
337 for (bit = 8; bit-- > 0; val <<= 1) /* put byte onto FPGA */ qBri_FPGA_download()
355 DBG_FTL(("FPGA download: chip remains in busy state (0x%04x)", val)) qBri_FPGA_download()
H A Dxdi_msg.h23 no acknowledge will be genatated, FPGA will be programmed
/linux-4.1.27/drivers/staging/gs_fpgaboot/
H A Dgs_fpgaboot.c46 MODULE_PARM_DESC(file, "Xilinx FPGA firmware file.");
346 pr_info("FPGA DOWNLOAD --->\n"); gs_fpgaboot_init()
348 pr_info("FPGA image file name: %s\n", file); gs_fpgaboot_init()
352 pr_err("FPGA DRIVER INIT FAIL!!\n"); gs_fpgaboot_init()
364 pr_err("FPGA DOWNLOAD FAIL!!\n"); gs_fpgaboot_init()
368 pr_info("FPGA DOWNLOAD DONE <---\n"); gs_fpgaboot_init()
381 pr_info("FPGA image download module removed\n"); gs_fpgaboot_exit()
388 MODULE_DESCRIPTION("Xlinix FPGA firmware download");
H A Dio.c80 * generic bit swap for xilinx SYSTEMMAP FPGA programming
/linux-4.1.27/arch/microblaze/include/asm/
H A Dcpuinfo.h18 /* CPU Version and FPGA Family code conversion table type */
82 /* FPGA family */
/linux-4.1.27/drivers/tty/serial/
H A Dtimbuart.h2 * timbuart.c timberdale FPGA GPIO driver
20 * Timberdale FPGA UART
H A Dtimbuart.c2 * timbuart.c timberdale FPGA UART driver
20 * Timberdale FPGA UART
/linux-4.1.27/include/linux/
H A Dtimb_dma.h2 * timb_dma.h timberdale FPGA DMA driver defines
20 * Timberdale FPGA DMA engine
H A Dtimb_gpio.h2 * timb_gpio.h timberdale FPGA GPIO driver, platform data definition
H A Dfmc.h49 * If the FPGA is already programmed (think Etherbone or the second
226 /* Two more for device sets, all driven by the same FPGA */
/linux-4.1.27/arch/powerpc/platforms/85xx/
H A Dsocrates_fpga_pic.c18 * The FPGA supports 9 interrupt sources, which can be routed to 3
223 .name = "FPGA-PIC",
254 pr_warning("FPGA PIC: invalid irq type, " socrates_fpga_pic_host_xlate()
269 pr_warning("FPGA PIC: invalid irq routing\n"); socrates_fpga_pic_host_xlate()
288 pr_err("FPGA PIC: Unable to allocate host\n"); socrates_fpga_pic_init()
295 pr_warning("FPGA PIC: can't get irq%d.\n", i); socrates_fpga_pic_init()
313 pr_info("FPGA PIC: Setting up Socrates FPGA PIC\n"); socrates_fpga_pic_init()
H A Dge_imp3a.c68 * There is a simple interrupt handler in the main FPGA, this needs ge_imp3a_pic_init()
78 printk(KERN_WARNING "IMP3A: No FPGA PIC\n"); ge_imp3a_pic_init()
154 /* Return the FPGA revision */ ge_imp3a_get_fpga_rev()
188 seq_printf(m, "FPGA Revision\t: %u\n", ge_imp3a_get_fpga_rev()); ge_imp3a_show_cpuinfo()
H A Dmpc85xx_cds.c51 * The CDS board contains an FPGA/CPLD called "Cadmus", which collects
53 * Here is the FPGA/CPLD register map.
319 pr_err("Could not find FPGA node.\n"); mpc85xx_cds_setup_arch()
326 pr_err("Fail to map FPGA area.\n"); mpc85xx_cds_setup_arch()
/linux-4.1.27/arch/powerpc/platforms/52xx/
H A Dmedia5200.c15 * Notable characteristic of the Media5200 is the presence of an FPGA
39 /* FPGA register set */
77 .name = "Media5200 FPGA",
94 /* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs media5200_irq_cascade()
155 /* Now find the FPGA IRQ */ media5200_init_irq()
171 /* Disable all FPGA IRQs */ media5200_init_irq()
188 pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n"); media5200_init_irq()
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb/
H A Dtp.c76 /* FPGA */ t1_tp_intr_enable()
97 /* FPGA */ t1_tp_intr_disable()
129 /* FPGA doesn't support TP interrupts. */ t1_tp_intr_handler()
H A Dfpga_defs.h4 * FPGA specific definitions
13 /* FPGA master interrupt Cause/Enable bits */
/linux-4.1.27/arch/sh/include/mach-se/mach/
H A Dse7780.h50 #define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */
52 /* FPGA register address and bit */
71 /* FPGA INTSEL position */
H A Dse7721.h54 #define PA_FPGA 0xB7000000 /* FPGA base address */
H A Dse7751.h38 #define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
H A Dse.h43 #define PA_BCR 0xb1400000 /* FPGA */
H A Dse7722.h55 #define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */
/linux-4.1.27/arch/arm/mach-orion5x/
H A Dts78xx-setup.c36 * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
376 * FPGA 'hotplug' support code
406 pr_warn("unrecognised FPGA revision 0x%.2x\n", ts78xx_fpga_supports()
464 pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n", ts78xx_fpga_load()
489 * UrJTAG SVN since r1381 can be used to reprogram the FPGA ts78xx_fpga_unload()
492 pr_err("FPGA magic/rev mismatch\n" ts78xx_fpga_unload()
493 "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n", ts78xx_fpga_unload()
523 pr_err("FPGA borked, you must powercycle ASAP\n"); ts78xx_fpga_store()
557 MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */
560 MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
561 MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */
607 /* FPGA init */ ts78xx_init()
/linux-4.1.27/drivers/misc/altera-stapl/
H A Daltera-exprt.h4 * altera FPGA driver
H A Daltera-lpt.c4 * altera FPGA driver
H A Daltera-comp.c4 * altera FPGA driver
H A Daltera-jtag.h4 * altera FPGA driver
/linux-4.1.27/arch/powerpc/platforms/86xx/
H A Dgef_ppc9a.c60 * There is a simple interrupt handler in the main FPGA, this needs gef_ppc9a_init_irq()
65 printk(KERN_WARNING "PPC9A: No FPGA PIC\n"); gef_ppc9a_init_irq()
117 /* Return the FPGA revision */ gef_ppc9a_get_fpga_rev()
152 seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev()); gef_ppc9a_show_cpuinfo()
H A Dgef_sbc310.c60 * There is a simple interrupt handler in the main FPGA, this needs gef_sbc310_init_irq()
65 printk(KERN_WARNING "SBC310: No FPGA PIC\n"); gef_sbc310_init_irq()
125 /* Return the FPGA revision */ gef_sbc310_get_fpga_rev()
143 seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc310_get_fpga_rev()); gef_sbc310_show_cpuinfo()
H A Dgef_sbc610.c60 * There is a simple interrupt handler in the main FPGA, this needs gef_sbc610_init_irq()
65 printk(KERN_WARNING "SBC610: No FPGA PIC\n"); gef_sbc610_init_irq()
117 /* Return the FPGA revision */ gef_sbc610_get_fpga_rev()
134 seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc610_get_fpga_rev()); gef_sbc610_show_cpuinfo()
H A Dmpc8610_hpcd.c305 printk(KERN_ERR "Err: can't map FPGA cfg register!\n"); mpc86xx_hpcd_setup_arch()
/linux-4.1.27/arch/mn10300/include/asm/
H A Dirq.h26 * - the ASB2364 has an FPGA with an IRQ multiplexer on it
/linux-4.1.27/arch/powerpc/boot/
H A Dcuboot-taishan.c35 /* FIXME: sysclk should be derived by reading the FPGA taishan_fixups()
H A Debony.c47 fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH); ebony_flashsel_fixup()
73 // FIXME: sysclk should be derived by reading the FPGA registers ebony_fixups()
H A Dtreeboot-walnut.c33 fatal("Couldn't locate FPGA node\n\r"); walnut_flashsel_fixup()
/linux-4.1.27/arch/arm/mach-omap1/include/mach/
H A Domap1510.h50 * OMAP-1510 FPGA
121 * Innovator/OMAP1510 FPGA HID register bit definitions
132 /* The FPGA IRQ is cascaded through GPIO_13 */
135 /* IRQ Numbers for interrupts muxed through the FPGA */
H A Dirqs.h249 /* External FPGA handles interrupts on Innovator boards */
/linux-4.1.27/arch/arc/plat-arcfpga/
H A Dplatform.c2 * ARC FPGA Platform support code
/linux-4.1.27/drivers/crypto/
H A Dmv_cesa.h34 * FPGA_INT_STATUS looks like a FPGA leftover and is documented only in Errata
35 * 4.12. It looks like that it was part of an IRQ-controller in FPGA and
/linux-4.1.27/drivers/vme/boards/
H A Dvme_vmivme7805.c25 /** Base address to access FPGA register */
69 /* Clear the FPGA VME IF contents */ vmic_probe()
/linux-4.1.27/arch/sh/boards/mach-microdev/
H A Dirq.c79 /* disable interrupts on the FPGA INTC register */ disable_microdev_irq()
105 /* enable interrupts on the FPGA INTC register */ enable_microdev_irq()
127 /* disable interrupts on the FPGA INTC register */ init_microdev_irq()
H A Dfdc37c93xapm.c64 /* General-Purpose base address on CPU-board FPGA */
/linux-4.1.27/drivers/mfd/
H A Dtimberdale.h2 * timberdale.h timberdale FPGA MFD driver defines
20 * Timberdale FPGA
H A Dtimberdale.c2 * timberdale.c timberdale FPGA MFD driver
20 * Timberdale FPGA
697 "version of the FPGA, please update the driver to " timb_probe()
703 dev_err(&dev->dev, "The FPGA image is too old (%d.%d), " timb_probe()
704 "please upgrade the FPGA to at least: %d.%d\n", timb_probe()
730 /* Reset all FPGA PLB peripherals */ timb_probe()
/linux-4.1.27/arch/sh/boards/mach-se/7724/
H A Dirq.c90 .name = "SE7724-FPGA",
129 pr_err("%s: failed hooking irqs for FPGA\n", __func__); init_se7724_IRQ()
/linux-4.1.27/arch/arm/mach-realview/include/mach/
H A Dboard-pb1176.h74 #define REALVIEW_PB1176_GIC_CPU_BASE 0x10040000 /* GIC CPU interface, on FPGA */
75 #define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */
H A Dplatform.h132 * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
/linux-4.1.27/arch/arm/plat-omap/
H A Ddebug-leds.c24 * debug board (all green), accessed through FPGA registers.
27 /* NOTE: most boards don't have a static mapping for the FPGA ... */
/linux-4.1.27/drivers/atm/
H A Dsolos-pci.c67 #define OLD_BUF_SIZE 4096 /* For FPGA versions <= 2*/
69 #define ATMEL_FPGA_PAGE 528 /* FPGA flash page size*/
71 #define ATMEL_FPGA_BLOCK (ATMEL_FPGA_PAGE * 8) /* FPGA block size*/
155 MODULE_FIRMWARE("solos-FPGA.bin");
157 MODULE_FIRMWARE("solos-db-FPGA.bin");
161 MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
163 MODULE_PARM_DESC(db_fpga_upgrade, "Initiate daughter board FPGA upgrade");
640 fw_name = "solos-FPGA.bin"; flash_upgrade()
655 fw_name = "solos-db-FPGA.bin"; flash_upgrade()
661 dev_info(&card->dev->dev, "FPGA version doesn't support" flash_upgrade()
674 dev_info(&card->dev->dev, "FPGA version doesn't support" flash_upgrade()
695 dev_info(&card->dev->dev, "Changing FPGA to Update mode\n"); flash_upgrade()
701 dev_info(&card->dev->dev, "Set FPGA Flash mode to FPGA Chip Erase\n"); flash_upgrade()
703 dev_info(&card->dev->dev, "Set FPGA Flash mode to Solos Chip Erase\n"); flash_upgrade()
717 /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */ flash_upgrade()
743 dev_info(&card->dev->dev, "Returning FPGA to Data mode\n"); flash_upgrade()
1255 dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n", fpga_probe()
1261 "FPGA too old; cannot upgrade flash. Use JTAG.\n"); fpga_probe()
1278 if (1) { /* All known FPGA versions so far */ fpga_probe()
1438 /* Reset FPGA */ fpga_remove()
H A Deni.h114 int asic; /* PCI interface type, 0 for FPGA */
/linux-4.1.27/drivers/watchdog/
H A Dpika_wdt.c2 * PIKA FPGA based Watchdog Timer
70 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- pikawdt_reset()
262 /* -- FPGA: POST Test Results Register 1 (32bit R/W) (Offset: 0x4040) -- pikawdt_init()
300 MODULE_DESCRIPTION("PIKA FPGA based Watchdog Timer");
/linux-4.1.27/include/misc/
H A Daltera.h4 * altera FPGA driver
/linux-4.1.27/arch/sh/boards/mach-sdk7780/
H A Dsetup.c82 "FPGA version: %d (revision %d), datestamp : %d\n", sdk7780_setup()
/linux-4.1.27/arch/blackfin/mach-bf533/boards/
H A DH8606.c318 * Configuration for two 16550 UARTS in FPGA at addresses 0x20200000 and 0x202000010.
320 * suit different FPGA configuration, or to suit real 16550 UARTS connected to the bus
359 * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030,
360 * interrupt output wired to PF9. Change to suit different FPGA configuration
/linux-4.1.27/arch/m68k/coldfire/
H A Dfirebee.c43 .name = "FPGA",
/linux-4.1.27/drivers/net/ethernet/
H A Ddnet.h159 * controller inside the FPGA have.
214 unsigned int capabilities; /* read from FPGA */
H A Dec_bhf.c17 /* This is a driver for EtherCAT master module present on CCAT FPGA.
/linux-4.1.27/arch/sh/include/mach-sdk7786/mach/
H A Dfpga.h70 #define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */
141 * when the FPGA is in I2C slave mode.
/linux-4.1.27/arch/arm/mach-ixp4xx/
H A Domixp-setup.c48 .name = "Recovery FPGA",
56 .name = "Release FPGA",
/linux-4.1.27/arch/arm/mach-omap2/
H A Dboard-flash.c150 * get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get
163 /* we dont have an DEBUG FPGA??? */ get_gpmc0_type()
/linux-4.1.27/sound/pcmcia/pdaudiocf/
H A Dpdaudiocf.h48 #define PDAUDIOCF_RST (1<<2) /* FPGA, AKM + SRAM buffer reset */
58 #define PDAUDIOCF_FPGAREV(x) ((x>>12)&0x0f) /* FPGA revision */
H A Dpdaudiocf_core.c145 snd_iprintf(buffer, "FPGA revision : 0x%x\n", PDAUDIOCF_FPGAREV(tmp)); pdacf_proc_read()
196 /* egde based and FPGA does logical OR for all interrupt sources, we cannot use these */ snd_pdacf_ak4117_create()
222 /* setup the FPGA to match AK4117 setup */ snd_pdacf_ak4117_create()
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-highlander.c2 * Renesas Solutions Highlander FPGA I2C/SMBus support.
228 * The R0P7780LC0011RL FPGA needs a significant delay between highlander_i2c_read()
408 strlcpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name)); highlander_i2c_probe()
468 MODULE_DESCRIPTION("Renesas Highlander FPGA I2C/SMBus adapter");
/linux-4.1.27/drivers/staging/rtl8723au/include/
H A DHalVerDef.h35 FPGA = 2, enumerator in enum:hal_chip_type
/linux-4.1.27/arch/unicore32/kernel/
H A Dgpio.c13 /* in FPGA, no GPIO support */
/linux-4.1.27/arch/mips/include/asm/mach-au1x00/
H A Dgpio.h48 * an external FPGA but you still want them to be accssible in linux
H A Dgpio-au1300.h143 * an external FPGA but you still want them to be accssible in linux
H A Dgpio-au1000.h542 * an external FPGA but you still want them to be accssible in linux
/linux-4.1.27/arch/m32r/include/asm/
H A Dm32r_mp_fpga.h5 * Renesas M32R-MP-FPGA
13 * M32R-MP-FPGA Memory Map
18 * 0x03EF0000 : FPGA
68 * FPGA registers.
/linux-4.1.27/arch/arm/mach-versatile/
H A Dversatile_pb.c58 /* FPGA Primecells */
H A Dpci.c311 * Do not to map Versatile FPGA PCI device into memory space pci_versatile_setup()
/linux-4.1.27/arch/arm/mach-cns3xxx/
H A Dpm.c95 * in the system FPGA. cns3xxx_restart()
/linux-4.1.27/arch/avr32/boards/hammerhead/
H A Dflash.c331 /* Select EXTINT3 for PB28 (Interrupt from FPGA) */ at32_add_device_hh_fpga()
367 /* Setup SMC for FPGA interface */ hammerhead_flash_init()
374 printk(KERN_ERR "hammerhead: failed to set FPGA timing\n"); hammerhead_flash_init()
/linux-4.1.27/drivers/net/hamradio/
H A Dyam.c31 * 0.2 F6FBB 08.06.98 Added delay after FPGA programming
239 #define FPGA_DONE MSR_DSR /* FPGA is configured */
292 * FPGA functions
303 * reset FPGA
316 /* turn off FPGA supply voltage */ fpga_reset()
319 /* turn on FPGA supply voltage again */ fpga_reset()
325 * send one byte to FPGA
440 * download bitstream to FPGA
889 printk(KERN_ERR "%s: cannot init FPGA\n", dev->name); yam_open()
906 /* Reset overruns for all ports - FPGA programming makes overruns */ yam_open()
H A Dbaycom_epp.c31 * Integrated FPGA EPP modem configuration routines
32 * 0.3 11.05.1998 Took FPGA config out and moved it into a separate program
873 printk(KERN_INFO "%s: no FPGA detected, assuming conventional EPP modem\n", bc_drvname); epp_open()
/linux-4.1.27/drivers/media/usb/dvb-usb-v2/
H A Daf9035.h75 20480000, /* FPGA */
H A Dmxl111sf-phy.c214 {0x26, 0x0d, 0x0d}, /* I2S_MODE & BT656_SRC_SEL for FPGA only */ mxl111sf_init_i2s_port()
/linux-4.1.27/drivers/soc/versatile/
H A Dsoc-integrator.c149 dev_info(dev, " FPGA: %s\n", integrator_fpga_str(val)); integrator_soc_init()
/linux-4.1.27/drivers/pcmcia/
H A Dpxa2xx_balloon3.c38 pr_warn("The FPGA code, version 0x%04x, is too old. " balloon3_pcmcia_hw_init()
/linux-4.1.27/arch/microblaze/kernel/cpu/
H A Dmb.c52 "FPGA-Arch: %s\n" show_cpuinfo()
H A Dcpuinfo-static.c126 /* Do various fixups based on CPU version and FPGA family strings */ set_cpuinfo_static()
/linux-4.1.27/arch/arm/mach-pxa/
H A Dballoon3.c476 * FPGA IRQ balloon3_leds_init()
493 .name = "FPGA",
633 pr_warn("The FPGA code, version 0x%04x, is too old. " balloon3_nand_probe()
804 { /* CPLD/FPGA */
/linux-4.1.27/sound/pci/emu10k1/
H A Demu10k1_main.c677 /* The FPGA is a Xilinx Spartan IIE XC2S50E */ snd_emu1010_load_firmware()
678 /* GPIO7 -> FPGA PGMN snd_emu1010_load_firmware()
679 * GPIO6 -> FPGA CCLK snd_emu1010_load_firmware()
680 * GPIO5 -> FPGA DIN snd_emu1010_load_firmware()
681 * FPGA CONFIG OFF -> FPGA PGMN snd_emu1010_load_firmware()
689 udelay(100); /* Allow FPGA memory to clean */ snd_emu1010_load_firmware()
769 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */ emu1010_firmware_thread()
774 /* FPGA failed to be programmed */ emu1010_firmware_thread()
812 * * conversion of 32-bit data coming over EMU32 links from HANA FPGA
820 * FPGA (aka HANA):
869 /* FPGA netlist already present so clear it */ snd_emu10k1_emu1010_init()
877 /* FPGA failed to return to programming mode */ snd_emu10k1_emu1010_init()
879 "emu1010: FPGA failed to return to programming mode\n"); snd_emu10k1_emu1010_init()
921 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */ snd_emu10k1_emu1010_init()
924 /* FPGA failed to be programmed */ snd_emu10k1_emu1010_init()
/linux-4.1.27/drivers/media/usb/dvb-usb/
H A Dgp8psk.c49 info("FPGA Version = %i", fpga_vers); gp8psk_info()
51 info("failed to get FPGA version"); gp8psk_info()
/linux-4.1.27/arch/xtensa/platforms/xtfpga/
H A Dsetup.c314 /* Clock rate varies among FPGA bitstreams; board specific FPGA register xtavnet_init()
/linux-4.1.27/drivers/usb/misc/
H A Demi26.c113 /* 1. We need to put the loader for the FPGA into the EZ-USB */ emi26_load_firmware()
129 /* 2. We upload the FPGA firmware into the EMI emi26_load_firmware()
H A Demi62.c120 /* 1. We need to put the loader for the FPGA into the EZ-USB */ emi62_load_firmware()
136 /* 2. We upload the FPGA firmware into the EMI emi62_load_firmware()
/linux-4.1.27/arch/powerpc/sysdev/
H A Dxilinx_intc.c14 * Xilinx Virtex FPGA designs.
16 * The interrupt sense levels are hard coded into the FPGA design with
/linux-4.1.27/arch/mips/txx9/rbtx4938/
H A Dsetup.c211 rbtx4938_fpga_resource.name = "FPGA Registers"; rbtx4938_mem_setup()
221 printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", rbtx4938_mem_setup()
/linux-4.1.27/arch/arm/mach-realview/
H A Drealview_pb11mp.c152 /* FPGA Primecells */
327 * in the system FPGA realview_pb11mp_restart()
H A Drealview_pba8.c147 /* FPGA Primecells */
275 * in the system FPGA realview_pba8_restart()
H A Drealview_pbx.c170 /* FPGA Primecells */
352 * in the system FPGA realview_pbx_restart()
H A Drealview_eb.c174 /* FPGA Primecells */
429 * in the system FPGA realview_eb_restart()
H A Drealview_pb1176.c158 /* FPGA Primecells */
/linux-4.1.27/sound/usb/usx2y/
H A DusX2Yhwdep.c4 * FPGA Loader + ALSA Startup
132 info->num_dsps = 2; // 0: Prepad Data, 1: FPGA Code snd_usX2Y_hwdep_dsp_status()
/linux-4.1.27/drivers/media/pci/pt3/
H A Dpt3.h36 * register index of the FPGA chip
/linux-4.1.27/drivers/media/radio/
H A Dradio-timb.c2 * radio-timb.c Timberdale FPGA Radio driver
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Ddaqboard2000.c29 The FPGA on the board requires fimware, which is available from
46 a. program the FPGA (windows code sans a lot of error messages)
578 /* Set the + reference dac value in the FPGA */ daqboard2000_activateReferenceDacs()
587 /* Set the - reference dac value in the FPGA */ daqboard2000_activateReferenceDacs()
H A Dni_pcidio.c861 FW_PCI_6534_MAIN, /* loaded into main FPGA */ pci_6534_upload_firmware()
869 /* load main FPGA first, then the two scarabs */ pci_6534_upload_firmware()
H A Damplc_dio200_pci.c322 * The FPGA configuration has the PCI-Express Avalon-MM Bridge dio200_pcie_board_setup()
/linux-4.1.27/drivers/staging/rtl8712/
H A Drtl8712_hal.h128 unsigned short version; /*0x8000 ~ 0x8FFF for FPGA version,
/linux-4.1.27/drivers/staging/rtl8188eu/include/
H A DHalVerDef.h40 FPGA = 2, enumerator in enum:HAL_CHIP_TYPE
/linux-4.1.27/drivers/bluetooth/
H A Dbluecard_cs.c276 /* Tell the FPGA to send the data */ bluecard_write_wakeup()
746 /* Turn FPGA off */ bluecard_open()
752 /* Turn FPGA on */ bluecard_open()
826 /* Turn FPGA off */ bluecard_close()
/linux-4.1.27/arch/sh/boards/mach-r2d/
H A Dsetup.c278 printk(KERN_INFO "FPGA version:%d (revision:%d)\n", rts7751r2d_setup()
/linux-4.1.27/arch/sh/boards/mach-x3proto/
H A Dilsel.c89 * noting descending interrupt levels. Aliasing FPGA and external board
/linux-4.1.27/arch/m32r/platforms/usrv/
H A Dsetup.c207 * INT1# is used for UART, MMC, CF Controller in FPGA. init_IRQ()
/linux-4.1.27/arch/arm/mach-ep93xx/
H A Dvision_ep9307.c44 * Static I/O mappings for the FPGA
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dt4vf_common.h48 * = "a" for T4 FPGA; "b" for T4 FPGA, etc.
/linux-4.1.27/include/sound/
H A Demu10k1.h969 /* EMU1010m HANA FPGA registers */
1004 #define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */
1005 #define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */
1096 #define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio Dock online and FPGA configured */
1097 #define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio Dock online and FPGA not configured */
1101 #define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */
1102 #define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */
1104 #define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */
1105 #define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */
1220 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1224 /* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */
1422 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1424 * Sources are either physical inputs of FPGA,
/linux-4.1.27/drivers/net/ethernet/micrel/
H A Dks8842.c20 * The Micrel KS8842 behind the timberdale FPGA
90 enabled in the KS8842, but not in the FPGA IP, since the IP handles
92 TX interrupts are not needed it is handled by the FPGA the driver is
137 #define MICREL_KS884X 0x01 /* 0=Timeberdale(FPGA), 1=Micrel */
820 /* disable all but RX IRQ, since the FPGA relies on it*/ ks8842_irq()
/linux-4.1.27/drivers/net/ethernet/sfc/
H A Dmcdi_mon.c60 SENSOR(OUT_VAOE, "AOE FPGA supply", IN, -1),
61 SENSOR(AOE_TEMP, "AOE FPGA temp.", TEMP, -1),
H A Dmcdi_pcol.h367 /* enum: FIFO overflow (FPGA) */
900 /* enum: Read an FPGA register */
902 /* enum: Write an FPGA register */
1238 /* Number of packets timestamped by the FPGA */
1295 /* enum: FPGA load failed */
1297 /* enum: FPGA version invalid */
1299 /* enum: FPGA registers incorrect */
1307 /* enum: Mismatched packet count (Siena filter and FPGA) */
1330 /* Number of packets received by FPGA */
3105 /* enum: FPGA image. */
3107 /* enum: FPGA backup image */
3419 /* enum: AOE FPGA power: mV */
3421 /* enum: AOE FPGA temperature: degC */
3423 /* enum: AOE FPGA PSU temperature: degC */
3437 /* enum: AOE FPGA input power: mV */
3439 /* enum: AOE FPGA current: mA */
3441 /* enum: AOE FPGA input current: mA */
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_hw.h224 * Location of Firmware Configuration File in FLASH. Since the FPGA
/linux-4.1.27/drivers/memory/
H A Dmvebu-devbus.c3 * (memory controller for NOR/NAND/SRAM/FPGA devices)
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192se/
H A Dfw.h179 /* 0x8000 ~ 0x8FFF for FPGA version,
/linux-4.1.27/drivers/staging/rtl8192u/
H A Dr8190_rtl8256.c149 /* Check RF block (for FPGA platform only)---- phy_RF8256_Config_ParaFile()
/linux-4.1.27/drivers/pci/host/
H A Dpci-versatile.c175 * Do not to map Versatile FPGA PCI device into memory space versatile_pci_probe()
/linux-4.1.27/arch/powerpc/sysdev/ge/
H A Dge_pic.c2 * Interrupt handling for GE FPGA based PIC
/linux-4.1.27/arch/m32r/platforms/m32700ut/
H A Dsetup.c343 * INT1# is used for UART, MMC, CF Controller in FPGA. init_IRQ()
/linux-4.1.27/arch/m32r/platforms/opsput/
H A Dsetup.c343 * INT1# is used for UART, MMC, CF Controller in FPGA. init_IRQ()
/linux-4.1.27/sound/firewire/fireworks/
H A Dfireworks.c14 * - DSP or/and FPGA for signal processing
/linux-4.1.27/drivers/media/pci/cx23885/
H A Daltera-ci.c56 /* FPGA regs */
83 MODULE_DESCRIPTION("altera FPGA CI module");
/linux-4.1.27/drivers/media/platform/
H A Dtimblogiw.c2 * timblogiw.c timberdale FPGA LogiWin Video In driver
20 * Timberdale FPGA LogiWin Video In
/linux-4.1.27/drivers/dma/
H A Dpch_dma.c1002 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA3_4CH), 4}, /* FPGA */
1007 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA4_4CH), 4}, /* FPGA */
H A Dtimb_dma.c2 * timb_dma.c timberdale FPGA DMA driver
20 * Timberdale FPGA DMA engine
/linux-4.1.27/include/uapi/linux/
H A Dcyclades.h161 __u32 fpga_id; /* FPGA Identification Register */
162 __u32 fpga_version; /* FPGA Version Number Register */
/linux-4.1.27/arch/cris/arch-v32/drivers/mach-fs/
H A Dgpio.c395 /* For FPGA: min 5.0ns (DCC) before CCLK high */ gpio_write()
408 /* For FPGA: min 5.0ns (DCC) before CCLK high */ gpio_write()
/linux-4.1.27/sound/pci/ice1712/
H A Dprodigy192.c29 * - both MCKO1 and MCKO2 of ak4114 are fed to FPGA, which
34 * sampling rate. That means the the FPGA doubles the
/linux-4.1.27/arch/mips/pmcs-msp71xx/
H A Dmsp_prom.c134 return "PMC-Sierra MSP7120 FPGA"; get_system_type()
/linux-4.1.27/arch/mips/txx9/rbtx4939/
H A Dsetup.c529 pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", rbtx4939_setup()
/linux-4.1.27/arch/arm/mach-versatile/include/mach/
H A Dplatform.h156 * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
/linux-4.1.27/arch/arm/mach-davinci/
H A Dboard-mityomapl138.c217 /* FPGA VCC Aux (2.5 or 3.3) LDO */
/linux-4.1.27/drivers/block/
H A Dxsysace.c12 * The SystemACE chip is designed to configure FPGAs by loading an FPGA
15 * MPU interface which can be used to control the FPGA configuration process
77 * - Add FPGA configuration control interface.
/linux-4.1.27/arch/xtensa/kernel/
H A Dsetup.c442 Display reminder for early engr test or demo chips / FPGA bitstreams */ check_s32c1i()
/linux-4.1.27/drivers/gpu/drm/radeon/
H A DObjectID.h80 #define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */
/linux-4.1.27/arch/mips/alchemy/devboards/
H A Ddb1300.c36 /* FPGA (external mux) interrupt sources */

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