Searched refs:Base (Results 1 - 200 of 718) sorted by relevance

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/linux-4.1.27/arch/arm/mach-ks8695/include/mach/
H A Dregs-pci.h23 #define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */
30 #define KS8695_PMBA (0x208) /* Bridge Memory Base Address */
31 #define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */
32 #define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */
33 #define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */
34 #define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */
35 #define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */
36 #define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */
37 #define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */
H A Dregs-mem.h39 #define EXTACON_EBBPTR (0x3ff << 12) /* Base Pointer */
47 #define ROMCON_RBBPTR (0x3ff << 12) /* Base Pointer */
66 #define SDCON_DBBPTR (0x3ff << 12) /* Base Pointer */
H A Dregs-sys.h27 #define SYSCFG_SPRBP (0x3ff << 16) /* Register Bank Base Pointer */
H A Dregs-lan.h28 #define KS8695_LTDLB (0x10) /* Transmit Descriptor List Base Address */
29 #define KS8695_LRDLB (0x14) /* Receive Descriptor List Base Address */
H A Dregs-wan.h28 #define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */
29 #define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */
/linux-4.1.27/arch/m68k/include/asm/
H A Dm5272sim.h45 #define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */
47 #define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */
49 #define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */
51 #define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */
53 #define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */
55 #define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */
57 #define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */
59 #define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */
71 #define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
72 #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
84 #define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
86 #define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
87 #define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */
88 #define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
89 #define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
91 #define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */
97 #define MCFINT_VECBASE 64 /* Base of interrupts */
H A Dm54xxsim.h19 #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
29 #define MCFINTC_ICR0 0x40 /* Base ICR register */
34 #define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */
35 #define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */
36 #define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */
37 #define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */
52 #define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */
53 #define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */
H A Dm520xsim.h23 #define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */
32 #define MCFINTC_ICR0 0x40 /* Base ICR register */
158 #define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
159 #define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */
164 #define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */
165 #define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */
166 #define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */
171 #define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */
177 #define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */
H A Dm5441xsim.h96 #define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */
97 #define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */
98 #define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */
99 #define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */
120 #define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */
121 #define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */
122 #define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */
123 #define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */
124 #define MCFUART_BASE4 0xec060000 /* Base address of UART4 */
125 #define MCFUART_BASE5 0xec064000 /* Base address of UART5 */
126 #define MCFUART_BASE6 0xec068000 /* Base address of UART6 */
127 #define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */
128 #define MCFUART_BASE8 0xec070000 /* Base address of UART8 */
129 #define MCFUART_BASE9 0xec074000 /* Base address of UART9 */
H A Dm5206sim.h93 #define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
94 #define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
99 #define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
100 #define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
103 #define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */
104 #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
106 #define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */
107 #define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */
H A Dm5407sim.h85 #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
86 #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
88 #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
89 #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
97 #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
98 #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
99 #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
100 #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
H A Dm5307sim.h58 #define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
59 #define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */
102 #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
103 #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
111 #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
112 #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
113 #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
114 #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
120 #define MCFUART_BASE0 (MCF_MBAR + 0x200) /* Base address UART0 */
121 #define MCFUART_BASE1 (MCF_MBAR + 0x1c0) /* Base address UART1 */
123 #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
124 #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
H A Dm525xsim.h79 #define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */
96 #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
97 #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
102 #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
103 #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
108 #define MCFQSPI_BASE (MCF_MBAR + 0x400) /* Base address QSPI */
126 #define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base addreess I2C0 */
129 #define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */
135 #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
136 #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
137 #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
138 #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
H A Dm523xsim.h23 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
24 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
34 #define MCFINTC_ICR0 0x40 /* Base ICR register */
61 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
63 #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
H A Dm527xsim.h23 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
24 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
34 #define MCFINTC_ICR0 0x40 /* Base ICR register */
70 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
72 #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
80 #define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */
82 #define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */
H A Dm528xsim.h23 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
24 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
34 #define MCFINTC_ICR0 0x40 /* Base ICR register */
60 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
62 #define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
H A Dm68360_pram.h27 unsigned long mcbase; /* Multichannel Base pointer */
34 unsigned long intbase; /* Multichannel Base address */
50 unsigned short tbase; /* Tx Buffer Descriptors Base Address */
61 unsigned short rbase; /* Rx Buffer Descriptors Base Address */
246 unsigned short rbase; /* Rx BD Base Address */
247 unsigned short tbase; /* Tx BD Base Address */
264 unsigned short rbase; /* Rx BD Base Address */
265 unsigned short tbase; /* Tx BD Base Address */
288 unsigned short rbase; /* rx BD Base Address */
289 unsigned short tbase; /* Tx BD Base Address */
307 unsigned short ibase; /* IDMA BD Base Address */
H A Dm52xxacr.h44 #define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
H A Dm53xxacr.h39 #define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
H A Dm53xxsim.h97 #define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */
98 #define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */
99 #define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */
104 #define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */
110 #define MCFQSPI_BASE 0xFC05C000 /* Base address of QSPI */
120 #define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
121 #define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
122 #define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
123 #define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
H A Dmacints.h34 * Base IRQ number for all Mac68K interrupt sources. Each source
/linux-4.1.27/drivers/ata/
H A Dpata_ninja32.c16 * Base + 0x00 IRQ Status
17 * Base + 0x01 IRQ control
18 * Base + 0x02 Chipset control
19 * Base + 0x03 Unknown
20 * Base + 0x04 VDMA and reset control + wait bits
21 * Base + 0x08 BMIMBA
22 * Base + 0x0C DMA Length
23 * Base + 0x10 Taskfile
24 * Base + 0x18 BMDMA Status ?
25 * Base + 0x1C
26 * Base + 0x1D Bus master control
33 * Base + 0x1E AltStatus
34 * Base + 0x1F timing register
H A Dpata_platform.c88 * - I/O Base (IORESOURCE_IO or IORESOURCE_MEM)
89 * - CTL Base (IORESOURCE_IO or IORESOURCE_MEM)
/linux-4.1.27/include/linux/
H A Dscx200.h15 #define SCx200_DOCCS_BASE 0x78 /* DOCCS Base Address Register */
22 #define SCx200_CB_BASE_FIXED 0x9000 /* Base fixed at 0x9000 according to errata? */
50 #define SCx200_CBA 0x3e /* Configuration Base Address Register */
51 #define SCx200_CBA_SCRATCH 0x64 /* Configuration Base Address Scratchpad */
H A D8250_pci.h19 /* Use the Base address register size to cap number of ports */
H A Dmii.h181 * bits, when in 1000Base-T mode, to ethtool
201 * bits, when in 1000Base-T mode, to ethtool
219 * bits, when in 1000Base-T mode, to ethtool
240 * MII_CTRL1000 register when in 1000Base-X mode.
263 * bits, when in 1000Base-X mode, to ethtool
287 * bits, when in 1000Base-X mode, to ethtool
H A Di2c-mux-gpio.h20 * @base_nr: Base I2C bus number to number adapters from or zero for dynamic
H A Di2c-mux-pinctrl.h25 * @base_bus_num: Base I2C bus number for the child busses. 0 for dynamic.
H A Dnvme.h33 __u64 asq; /* Admin SQ Base Address */
34 __u64 acq; /* Admin CQ Base Address */
H A Dyam.h61 unsigned int iobase; /* IO Base of COM port */
H A Drio_regs.h155 #define RIO_LCSH_BA 0x58 /* [I] LCS High Base Address */
156 #define RIO_LCSL_BA 0x5c /* [I] LCS Base Address */
158 #define RIO_DID_CSR 0x60 /* [III] Base Device ID CSR */
162 #define RIO_HOST_DID_LOCK_CSR 0x68 /* [III] Host Base Device ID Lock CSR */
/linux-4.1.27/arch/arm64/include/asm/
H A Dkvm_asm.h32 #define TTBR0_EL1 6 /* Translation Table Base Register 0 */
33 #define TTBR1_EL1 7 /* Translation Table Base Register 1 */
40 #define VBAR_EL1 14 /* Vector Base Address Register */
65 #define TEEHBR32_EL1 93 /* ThumbEE Handler Base Register */
74 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
76 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
78 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
90 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88e1xxx.h17 #define MII_GBCR 9 /* 1000Base-T control register */
18 #define MII_GBSR 10 /* 1000Base-T status register */
20 /* 1000Base-T control register fields */
27 /* 1000Base-T status register fields */
/linux-4.1.27/drivers/isdn/sc/
H A Dhardware.h35 #define PG0_OFFSET 0x3000 /* Offset from I/O Base for Page 0 register */
36 #define PG1_OFFSET 0x3400 /* Offset from I/O Base for Page 1 register */
37 #define PG2_OFFSET 0x3800 /* Offset from I/O Base for Page 2 register */
38 #define PG3_OFFSET 0x3C00 /* Offset from I/O Base for Page 3 register */
49 #define EXP_BASE 11 /* Shared RAM Base address */
H A Dinit.c78 pr_debug("I/O Base for board %d is 0x%x, %s probe\n", b, io[b], sc_init()
82 * No, I/O Base has been provided sc_init()
103 pr_debug("I/O Base 0x%x fails test\n", sc_init()
109 * Yes, probe for I/O Base sc_init()
157 pr_debug("RAM Base for board %d is 0x%lx, %s probe\n", b, sc_init()
363 pr_info(" %s (%d) - %s %d channels IRQ %d, I/O Base 0x%x, RAM Base 0x%lx\n", sc_init()
H A Dcard.h81 int iobase; /* I/O Base address */
/linux-4.1.27/drivers/isdn/hardware/eicon/
H A Dio.c590 volatile byte __iomem *Base = DIVA_OS_MEM_ATTACH_RAM((PISDN_ADAPTER)a->io); mem_in() local
591 val = READ_BYTE(Base + (unsigned long)addr); mem_in()
592 DIVA_OS_MEM_DETACH_RAM((PISDN_ADAPTER)a->io, Base); mem_in()
598 volatile byte __iomem *Base = DIVA_OS_MEM_ATTACH_RAM((PISDN_ADAPTER)a->io); mem_inw() local
599 val = READ_WORD((Base + (unsigned long)addr)); mem_inw()
600 DIVA_OS_MEM_DETACH_RAM((PISDN_ADAPTER)a->io, Base); mem_inw()
605 volatile byte __iomem *Base = DIVA_OS_MEM_ATTACH_RAM((PISDN_ADAPTER)a->io); mem_in_dw() local
607 *data++ = READ_DWORD((Base + (unsigned long)addr)); mem_in_dw()
610 DIVA_OS_MEM_DETACH_RAM((PISDN_ADAPTER)a->io, Base); mem_in_dw()
614 volatile byte __iomem *Base = DIVA_OS_MEM_ATTACH_RAM((PISDN_ADAPTER)a->io); mem_in_buffer() local
615 memcpy_fromio(buffer, (Base + (unsigned long)addr), length); mem_in_buffer()
616 DIVA_OS_MEM_DETACH_RAM((PISDN_ADAPTER)a->io, Base); mem_in_buffer()
628 volatile byte __iomem *Base = DIVA_OS_MEM_ATTACH_RAM((PISDN_ADAPTER)a->io); mem_out() local
629 WRITE_BYTE(Base + (unsigned long)addr, data); mem_out()
630 DIVA_OS_MEM_DETACH_RAM((PISDN_ADAPTER)a->io, Base); mem_out()
634 volatile byte __iomem *Base = DIVA_OS_MEM_ATTACH_RAM((PISDN_ADAPTER)a->io); mem_outw() local
635 WRITE_WORD((Base + (unsigned long)addr), data); mem_outw()
636 DIVA_OS_MEM_DETACH_RAM((PISDN_ADAPTER)a->io, Base); mem_outw()
640 volatile byte __iomem *Base = DIVA_OS_MEM_ATTACH_RAM((PISDN_ADAPTER)a->io); mem_out_dw() local
642 WRITE_DWORD((Base + (unsigned long)addr), *data); mem_out_dw()
646 DIVA_OS_MEM_DETACH_RAM((PISDN_ADAPTER)a->io, Base); mem_out_dw()
650 volatile byte __iomem *Base = DIVA_OS_MEM_ATTACH_RAM((PISDN_ADAPTER)a->io); mem_out_buffer() local
651 memcpy_toio((Base + (unsigned long)addr), buffer, length); mem_out_buffer()
652 DIVA_OS_MEM_DETACH_RAM((PISDN_ADAPTER)a->io, Base); mem_out_buffer()
656 volatile byte __iomem *Base = DIVA_OS_MEM_ATTACH_RAM((PISDN_ADAPTER)a->io); mem_inc() local
657 byte x = READ_BYTE(Base + (unsigned long)addr); mem_inc()
658 WRITE_BYTE(Base + (unsigned long)addr, x + 1); mem_inc()
659 DIVA_OS_MEM_DETACH_RAM((PISDN_ADAPTER)a->io, Base); mem_inc()
/linux-4.1.27/drivers/acpi/acpica/
H A Drsmemory.c72 * Minimum Base Address
73 * Maximum Base Address
74 * Address Base Alignment
104 * Minimum Base Address
105 * Maximum Base Address
106 * Address Base Alignment
136 * Base Address
H A Drsio.c74 * Minimum Base Address
75 * Maximum Base Address
102 * Base Address
H A Dutstring.c194 /* Invalid Base */ acpi_ut_strtoul64()
211 * Base equal to ACPI_ANY_BASE means 'ToInteger operation case'. acpi_ut_strtoul64()
322 /* Base was set/validated above */ acpi_ut_strtoul64()
/linux-4.1.27/arch/mips/include/asm/
H A Dnile4.h132 #define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
133 #define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
134 #define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
139 #define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */
145 #define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
146 #define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
147 #define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
148 #define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
149 #define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
150 #define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
151 #define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
152 #define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
H A Djazz.h85 * Base address of the Sonic Ethernet adapter in Jazz machines.
90 * Base address of the 53C94 SCSI hostadapter in Jazz machines.
227 #define JAZZ_R4030_TRSTBL_BASE 0xE0000018 /* Translation Table Base */
H A Dmsc01_ic.h32 #define MSC01_IC_BASE_OFS 0x001a0 /* Base address of IC_VEC */
/linux-4.1.27/arch/x86/include/uapi/asm/
H A Dmtrr.h39 unsigned long base; /* Base address */
46 unsigned long base; /* Base address */
54 __u64 base; /* Base address */
60 __u64 base; /* Base address */
/linux-4.1.27/arch/sh/kernel/cpu/sh2/
H A Dex.S39 ! Exception Vector Base
/linux-4.1.27/arch/mips/lasat/
H A Dlasat_models.h17 * Base models
H A Dlasat_board.c241 /* Base model stuff */ lasat_init_board_info()
/linux-4.1.27/arch/arm/mach-s3c24xx/
H A Dsetup-i2c.c6 * S3C24XX Base setup for i2c device
/linux-4.1.27/arch/arm/mach-s3c64xx/
H A Dsetup-fb-24bpp.c8 * Base S3C64XX setup information for 24bpp LCD framebuffer
H A Dsetup-i2c0.c8 * Base S3C64XX I2C bus 0 gpio configuration
H A Dsetup-i2c1.c8 * Base S3C64XX I2C bus 1 gpio configuration
H A Ddev-uart.c8 * Base S3C64XX UART resource and device definitions
/linux-4.1.27/arch/arm/plat-samsung/
H A Ddev-uart.c7 * Base S3C24XX platform device definitions
H A Ds5p-dev-mfc.c4 * Base S5P MFC resource and device definitions
/linux-4.1.27/drivers/staging/vt6655/
H A Dmac.c64 * dwIoBase - Base Address for MAC
87 * dwIoBase - Base Address for MAC
110 * dwIoBase - Base Address for MAC
134 * dwIoBase - Base Address for MAC
155 * dwIoBase - Base Address for MAC
175 * dwIoBase - Base Address for MAC
202 * dwIoBase - Base Address for MAC
232 * dwIoBase - Base Address for MAC
281 * dwIoBase - Base Address for MAC
312 * dwIoBase - Base Address for MAC
344 * dwIoBase - Base Address for MAC
405 * dwIoBase - Base Address for MAC
468 * dwIoBase - Base Address for MAC
503 * dwIoBase - Base Address for MAC
530 * dwIoBase - Base Address for MAC
560 * dwIoBase - Base Address for MAC
598 * dwIoBase - Base Address for MAC
636 * dwIoBase - Base Address for MAC
673 * dwIoBase - Base Address for MAC
720 * dwIoBase - Base Address for MAC
755 * dwIoBase - Base Address for MAC
810 * dwIoBase - Base Address for MAC
877 * dwIoBase - Base Address for MAC
/linux-4.1.27/drivers/misc/mic/common/
H A Dmic_dev.h27 * @pa: Base physical address.
28 * @va: Base ioremap'd virtual address.
/linux-4.1.27/arch/sparc/include/asm/
H A Dvaddrs.h55 #define SUN4M_IOBASE_VADDR 0xfd000000 /* Base for mapping pages */
67 #define DVMA_VADDR 0xfff00000 /* Base area of the DVMA on suns */
/linux-4.1.27/drivers/platform/mips/
H A Dacpi_init.c84 /* PM Status Base */ acpi_registers_setup()
88 /* PM Control Base */ acpi_registers_setup()
92 /* GPM Base */ acpi_registers_setup()
/linux-4.1.27/drivers/media/platform/s5p-g2d/
H A Dg2d-regs.h33 #define SRC_BASE_ADDR_REG 0x0304 /* Src Image Base Address reg */
44 #define DST_BASE_ADDR_REG 0x0404 /* Dest Image Base Address reg */
51 #define PAT_BASE_ADDR_REG 0x0500 /* Pattern Image Base Address reg */
58 #define MASK_BASE_ADDR_REG 0x0520 /* Mask Base Address reg */
/linux-4.1.27/arch/powerpc/platforms/8xx/
H A Dmpc86xads.h32 #define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
H A Dmpc885ads.h34 #define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
/linux-4.1.27/arch/sh/drivers/pci/
H A Dpci-sh7751.h56 #define SH7751_PCICONF2_BCC 0xFF000000 /* Base Class Code */
69 #define SH7751_PCICONF4_BASE 0xFFFFFFFC /* I/O Space Base Addr */
72 #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
77 #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
H A Dpci-sh5.h78 /* Base address of registers */
H A Dpci-sh4.h120 #define SH4_PCIMBR 0x1C4 /* Memory Base Address */
123 #define SH4_PCIIOBR 0x1C8 /* I/O Base Address Register */
/linux-4.1.27/arch/sh/kernel/cpu/sh2a/
H A Dex.S60 ! Exception Vector Base
/linux-4.1.27/arch/arm/include/asm/
H A Dkvm_asm.h28 #define c2_TTBR0 6 /* Translation Table Base Register 0 */
30 #define c2_TTBR1 8 /* Translation Table Base Register 1 */
32 #define c2_TTBCR 10 /* Translation Table Base Control R. */
45 #define c12_VBAR 23 /* Vector Base Address Register */
H A Dhw_breakpoint.h98 /* Base register numbers for the debug registers. */
/linux-4.1.27/drivers/video/fbdev/
H A Dsa1100fb.h15 #define DBAR1 0x0010 /* LCD DMA Base Address Reg. channel 1 */
17 #define DBAR2 0x0018 /* LCD DMA Base Address Reg. channel 2 */
/linux-4.1.27/arch/powerpc/platforms/cell/
H A Dinterrupt.h60 /* Base numbers for the external interrupts */
66 /* Base numbers for the IIC_ISR interrupts */
/linux-4.1.27/drivers/net/ethernet/apple/
H A Dmace.h144 #define PORTSEL_10T 0x02 /* select 10Base-T port */
150 #define LNKFL 0x80 /* reports 10Base-T link failure */
151 #define DLNKTST 0x40 /* disable 10Base-T link test */
152 #define REVPOL 0x20 /* 10Base-T receiver polarity reversed */
155 #define ASEL 0x04 /* auto-select AUI or 10Base-T port */
/linux-4.1.27/drivers/dma/
H A Dfsl_raid.h125 __be32 re_liodn_base; /* LIODN Base Register */
145 __be32 inbring_base_h; /* Inbound Ring Base Address Register - High */
146 __be32 inbring_base_l; /* Inbound Ring Base Address Register - Low */
157 __be32 oubring_base_h; /* Outbound Ring Base Address Register - High */
158 __be32 oubring_base_l; /* Outbound Ring Base Address Register - Low */
/linux-4.1.27/drivers/usb/host/
H A Dohci-tmio.c43 #define CCR_BASE 0x10 /* l USB Control Register Base Address Low */
49 #define CCR_LMW1BL 0x58 /* w Local Memory Window 1 Base Address Low */
50 #define CCR_LMW1BH 0x5A /* w Local Memory Window 1 Base Address High */
53 #define CCR_LMW2BL 0x60 /* w Local Memory Window 2 Base Address Low */
54 #define CCR_LMW2BH 0x62 /* w Local Memory Window 2 Base Address High */
/linux-4.1.27/drivers/media/dvb-frontends/
H A Dstb0899_drv.c290 GETBYTE(stb0899_i2cdev, BYTE1), /* 0xf3 S2 Base Address (MSB) */ _stb0899_read_s2reg()
291 GETBYTE(stb0899_i2cdev, BYTE0), /* 0xfc S2 Base Address (LSB) */ _stb0899_read_s2reg()
292 GETBYTE(stb0899_base_addr, BYTE0), /* 0x00 Base Address (LSB) */ _stb0899_read_s2reg()
293 GETBYTE(stb0899_base_addr, BYTE1), /* 0x04 Base Address (LSB) */ _stb0899_read_s2reg()
294 GETBYTE(stb0899_base_addr, BYTE2), /* 0x00 Base Address (MSB) */ _stb0899_read_s2reg()
295 GETBYTE(stb0899_base_addr, BYTE3), /* 0x00 Base Address (MSB) */ _stb0899_read_s2reg()
333 printk(KERN_ERR "%s ERR(1), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n", _stb0899_read_s2reg()
355 printk(KERN_ERR "%s ERR(2), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n", _stb0899_read_s2reg()
363 printk(KERN_ERR "%s ERR(3), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n", _stb0899_read_s2reg()
370 printk(KERN_DEBUG "%s Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Data=[0x%08x]\n", _stb0899_read_s2reg()
387 /* Base Address Setup */ stb0899_write_s2reg()
389 GETBYTE(stb0899_i2cdev, BYTE1), /* 0xf3 S2 Base Address (MSB) */ stb0899_write_s2reg()
390 GETBYTE(stb0899_i2cdev, BYTE0), /* 0xfc S2 Base Address (LSB) */ stb0899_write_s2reg()
391 GETBYTE(stb0899_base_addr, BYTE0), /* 0x00 Base Address (LSB) */ stb0899_write_s2reg()
392 GETBYTE(stb0899_base_addr, BYTE1), /* 0x04 Base Address (LSB) */ stb0899_write_s2reg()
393 GETBYTE(stb0899_base_addr, BYTE2), /* 0x00 Base Address (MSB) */ stb0899_write_s2reg()
394 GETBYTE(stb0899_base_addr, BYTE3), /* 0x00 Base Address (MSB) */ stb0899_write_s2reg()
427 printk(KERN_DEBUG "%s Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x]\n", stb0899_write_s2reg()
433 printk(KERN_ERR "%s ERR (1), Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x], status=%d\n", stb0899_write_s2reg()
440 printk(KERN_ERR "%s ERR (2), Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x], status=%d\n", stb0899_write_s2reg()
/linux-4.1.27/arch/x86/math-emu/
H A Dpoly_l2.c24 | Base 2 logarithm by a polynomial approximation. |
102 | Base 2 logarithm by a polynomial approximation. |
178 | Base 2 logarithm by a polynomial approximation. |
/linux-4.1.27/arch/arm/boot/compressed/
H A Dhead-sharpsl.S28 mov r1, #0x10000000 @ Base address of TC6393 chip
42 ldr r1, .W100ADDR @ Base address of w100 chip + regs offset
128 mov r1, #0x0c000000 @ Base address of NAND chip
/linux-4.1.27/drivers/net/ethernet/micrel/
H A Dks8695net.h52 * Base Address
55 * Base Address
/linux-4.1.27/drivers/crypto/caam/
H A Dintern.h56 dma_addr_t *inpring; /* Base of input ring, alloc DMA-safe */
60 struct jr_outentry *outring; /* Base of output ring, DMA-safe */
/linux-4.1.27/sound/soc/samsung/
H A Dsmdk_wm8580pcm.c28 * SMDK6410 Base B/D: CFG1-0000, CFG2-1111
143 * After SMDKC110 Base Board's Rev is '0.1', 12MHz External OSC(X1)
/linux-4.1.27/drivers/atm/
H A Diphase.h632 /*-------------------- Base Registers --------------------*/
652 ffreg_t cbr_base; /* CBR Pointer Base */
653 ffreg_t vbr_base; /* VBR Pointer Base */
654 ffreg_t abr_base; /* ABR Pointer Base */
655 ffreg_t ubr_base; /* UBR Pointer Base */
657 ffreg_t vbrwq_base; /* VBR Wait Queue Base */
658 ffreg_t abrwq_base; /* ABR Wait Queue Base */
659 ffreg_t ubrwq_base; /* UBR Wait Queue Base */
660 ffreg_t vct_base; /* Main VC Table Base */
661 ffreg_t vcte_base; /* Extended Main VC Table Base */
676 ffreg_t queue_base; /* Base address for PRQ and TCQ */
677 ffreg_t desc_base; /* Base address of descriptor table */
725 rreg_t raw_base_adr; /* Base addr for raw cell Q */
731 rreg_t desc_base; /* Base address for description table */
732 rreg_t vc_lkup_base; /* Base address for VC lookup table */
733 rreg_t reass_base; /* Base address for reassembler table */
734 rreg_t queue_base; /* Base address for Communication queue */
741 rreg_t vp_lkup_base; /* Base address for VP lookup table */
743 rreg_t abr_lkup_base; /* Base address of ABR VC Table */
990 u32 __iomem *phy; /* Base pointer into phy (SUNI). */
991 u32 __iomem *dma; /* Base pointer into DMA control registers. */
992 u32 __iomem *reg; /* Base pointer to SAR registers. */
/linux-4.1.27/drivers/pci/pcie/
H A Dportdrv.h16 * According to the PCI Express Base Specification 2.0, the indices of
H A Dportdrv_core.c115 * The code below follows the PCI Express Base Specification 2.0 pcie_port_enable_msix()
142 * Base Specification 2.0 stating that bits 31-27 of the Root pcie_port_enable_msix()
249 * as described in PCI Express Base Specification 1.0a sections 7.8.2, 7.8.9 and
/linux-4.1.27/include/linux/regulator/
H A Dtps51632-regulator.h37 * @base_voltage_uV: Base voltage when PWM-DVFS enabled.
/linux-4.1.27/arch/arm/mach-spear/
H A Dspear1310.c24 /* Base addresses */
/linux-4.1.27/arch/arm/kernel/
H A Dthumbee.c28 * Access to the ThumbEE Handler Base register
/linux-4.1.27/arch/arm/mach-omap1/include/mach/
H A Dams-delta-fiq.h23 * Base address of an interrupt handler that the INT_DEFERRED_FIQ belongs to.
H A Domap7xx.h34 * Base addresses
/linux-4.1.27/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac_dma.h32 #define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
33 #define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
/linux-4.1.27/drivers/scsi/dpt/
H A Ddpti_ioctl.h88 int base; /* Base I/O address */
110 uINT baseAddr; // Base I/O address
/linux-4.1.27/drivers/staging/vt6656/
H A Dmac.c93 * dwIoBase - Base Address for MAC
113 * dwIoBase - Base Address for MAC
/linux-4.1.27/arch/x86/include/asm/
H A Dmtrr.h103 compat_ulong_t base; /* Base address */
110 compat_uint_t base; /* Base address */
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dg84.c146 .name = "Base",
198 * Base display object
H A Dg94.c58 * Base display object
H A Dgk110.c29 * Base display object
H A Dgm107.c29 * Base display object
H A Dgm204.c30 * Base display object
H A Dgt200.c74 * Base display object
H A Dgt215.c29 * Base display object
H A Dgk104.c194 * Base display object
/linux-4.1.27/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_kms.h42 * Base class for framebuffers
75 * Base class display unit.
/linux-4.1.27/arch/sh/boards/mach-dreamcast/
H A Dirq.c46 #define ESR_BASE 0x005f6900 /* Base event status register */
47 #define EMR_BASE 0x005f6910 /* Base event mask register */
/linux-4.1.27/arch/sh/boards/mach-microdev/
H A Dfdc37c93xapm.c31 #define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */
32 #define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */
/linux-4.1.27/tools/perf/util/
H A Dprobe-event.h13 char *symbol; /* Base symbol */
29 char *value; /* Base value */
/linux-4.1.27/drivers/net/ethernet/dec/tulip/
H A Dde4x5.h19 #define DE4X5_RRBA iobase+(0x018 << lp->bus) /* RX Ring Base Address Reg */
20 #define DE4X5_TRBA iobase+(0x020 << lp->bus) /* TX Ring Base Address Reg */
60 #define PCI_CBIO iobase+0x0028 /* PCI Base I/O Register */
61 #define PCI_CBMA iobase+0x002c /* PCI Base Memory Address Register */
62 #define PCI_CBER iobase+0x0030 /* PCI Expansion ROM Base Address Reg. */
152 #define CFRV_BC 0xff000000 /* Base Class */
168 ** PCI Configuration Base I/O Address Register (PCI_CBIO)
170 #define CBIO_MASK -128 /* Base I/O Address Mask */
187 ** PCI Configuration Expansion ROM Base Address Register (PCI_CBER)
189 #define CBER_MASK 0xfffffc00 /* Expansion ROM Base Address Mask */
266 ** DC21040 Receive Ring Base Address Register (DE4X5_RRBA)
271 ** DC21040 Transmit Ring Base Address Register (DE4X5_TRBA)
691 #define SICR_AUI 0x00000008 /* 10Base-T (0) or AUI (1) */
700 #define STRR_TAS 0x00008000 /* 10Base-T/AUI Autosensing Enable */
815 #define TP 0x0040 /* 10Base-T (now equiv to _10Mb) */
816 #define TP_NW 0x0002 /* 10Base-T with Nway */
/linux-4.1.27/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe_phy.c32 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
36 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
37 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
96 #define PHY_1000T_CTRL_DEFAULT 0x0300 /* 1000Base-T Control Register */
/linux-4.1.27/drivers/media/platform/vsp1/
H A Dvsp1_entity.h2 * vsp1_entity.h -- R-Car VSP1 Base Entity
H A Dvsp1_entity.c2 * vsp1_entity.c -- R-Car VSP1 Base Entity
/linux-4.1.27/drivers/staging/dgnc/
H A Ddgnc_cls.h22 * Base Structure Entries Usage Meanings to Host *
H A Ddgnc_neo.h24 * Base Structure Entries Usage Meanings to Host *
/linux-4.1.27/drivers/staging/sm750fb/
H A Dsm750_accel.c236 /* 2D Source Base. hw_copyarea()
241 /* 2D Destination Base. hw_copyarea()
353 /* 2D Source Base. hw_imageblit()
358 /* 2D Destination Base. hw_imageblit()
/linux-4.1.27/drivers/gpu/drm/gma500/
H A Dpsb_reg.h415 * WORD 1 - Base Address
448 * WORD 1 - Base Address
476 * WORD 1 - Base Address
493 * WORD 1 - Base Address
/linux-4.1.27/drivers/clk/versatile/
H A Dclk-versatile.c24 /* Base offset for the core module */
/linux-4.1.27/drivers/firmware/
H A Ddcdbas.h2 * dcdbas.h: Definitions for Dell Systems Management Base driver
H A Ddcdbas.c2 * dcdbas.c: Dell Systems Management Base Driver
4 * The Dell Systems Management Base Driver provides a sysfs interface for
44 #define DRIVER_DESCRIPTION "Dell Systems Management Base Driver"
/linux-4.1.27/arch/unicore32/include/mach/
H A Dregs-pci.h9 * PCICFG Bridge Base Reg.
H A DPKUnity.h29 * 0x80010000 - 0x80010250 592B PCI Bridge Base
/linux-4.1.27/arch/metag/tbx/
H A Dtbiroot.S49 GETL D0Re0,D1Re0,[A1LbP] /* Base of root block table */
/linux-4.1.27/drivers/usb/isp1760/
H A Disp1760-udc.h54 * regs: Base address of the UDC registers
/linux-4.1.27/drivers/vme/boards/
H A Dvme_vmivme7805.c25 /** Base address to access FPGA register */
/linux-4.1.27/include/uapi/linux/
H A Dinet_diag.h84 /* Base info structure. It contains socket identity (addrs/ports/cookie)
H A Dcyclades.h189 __u32 loc_addr_base; /* 04h - Local Address Base */
193 __u32 loc_rom_base; /* 14h - Local ROM Base */
196 __u32 loc_base_mst; /* 20h - Local Base for Master PCI */
198 __u32 pci_base_mst; /* 28h - PCI Base for Master PCI */
218 /* Values for the Local Base Address re-map register */
/linux-4.1.27/arch/s390/kernel/
H A Dhead_kdump.S59 basr %r13,0 # Base
/linux-4.1.27/arch/sh/include/mach-common/mach/
H A Dr2d.h45 #define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
/linux-4.1.27/arch/sh/include/mach-se/mach/
H A Dse.h99 /* Base address */
/linux-4.1.27/arch/powerpc/include/asm/
H A Dpte-book3e.h65 /* Base page size */
H A Dreg_booke.h129 #define SPRN_ATB 0x20E /* Alternate Time Base */
130 #define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
131 #define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
679 #define SPRN_TBHU 0x3CC /* Time Base High User-mode */
680 #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
682 #define SPRN_TBHI 0x3DC /* Time Base High */
683 #define SPRN_TBLO 0x3DD /* Time Base Low */
/linux-4.1.27/arch/arm/mach-omap2/
H A Dctrl_module_wkup_44xx.h24 /* Base address */
/linux-4.1.27/arch/arm/mach-u300/
H A Dcore.c128 /* MSL Base */
130 /* APEX Base */
132 /* Video Encoder Base */
134 /* XGAM Base */
/linux-4.1.27/arch/arm/mach-davinci/include/mach/
H A Dcommon.h44 * Base addresses in this structure should be physical and not virtual.
/linux-4.1.27/kernel/gcov/
H A Dgcov.h49 /* Base interface. */
/linux-4.1.27/sound/soc/fsl/
H A Dmpc5200_dma.h45 * @sicr: Base value used in serial interface control register; mode is ORed
/linux-4.1.27/drivers/net/can/cc770/
H A Dcc770.h104 /* Message Control Register 0 (Base Address + 0x0) */
118 /* Message Control Register 1 (Base Address + 0x01) */
135 /* Message Configuration Register (Base Address + 0x06) */
/linux-4.1.27/drivers/net/ethernet/tundra/
H A Dtsi108_eth.h316 u32 buf1; /* Base address of buffer */
342 u32 buf0; /* Base address of buffer */
343 u32 buf1; /* Base address of buffer */
/linux-4.1.27/drivers/edac/
H A Damd64_edac.h115 * is within a range affected by memory hoisting. The DRAM Base
142 * The memory controller for a given node uses its DRAM CS Base and
327 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
366 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
367 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
H A Damd8111_edac.h42 * PCI Bridge Memory Base-Limit Register, DevA:0x1c
H A Damd8131_edac.h53 * PCI-X Bridge Memory Base-Limit Register, DevA:0x1C
/linux-4.1.27/drivers/scsi/
H A Dinitio.h60 #define TUL_PBC 0x0B /* Base Class */
65 #define TUL_PBAD 0x10 /* Base address */
66 #define TUL_PBAD1 0x14 /* Base address */
67 #define TUL_PBAD2 0x18 /* Base address */
68 #define TUL_PBAD3 0x1C /* Base address */
69 #define TUL_PBAD4 0x20 /* Base address */
70 #define TUL_PBAD5 0x24 /* Base address */
/linux-4.1.27/arch/mips/include/asm/mach-pmcs-msp71xx/
H A Dmsp_regs.h225 /* ELB CS0 Base Address Reg */
234 /* ELB CS1 Base Address Reg */
243 /* ELB CS2 Base Address Reg */
252 /* ELB CS3 Base Address Reg */
261 /* ELB CS4 Base Address Reg */
270 /* ELB CS5 Base Address Reg */
/linux-4.1.27/drivers/video/fbdev/mbx/
H A Dreg_bits.h262 /* VBBASE - Video Blending Base Register */
289 /* VUBASE - Video U Base Register */
294 /* VVBASE - Video V Base Register */
323 /* VBBASE - Video Blending Base Register */
350 /* VUBASE - Video U Base Register */
355 /* VVBASE - Video V Base Register */
/linux-4.1.27/arch/alpha/include/asm/
H A Dcore_t2.h183 unsigned long elfmc_pal_base; /* Base address for PALcode. */
288 unsigned long elct_hbase; /* High Base Register */
289 unsigned long elct_wbase1; /* Window Base Register 1 */
291 unsigned long elct_tbase1; /* Translated Base Register 1 */
292 unsigned long elct_wbase2; /* Window Base Register 2 */
294 unsigned long elct_tbase2; /* Translated Base Register 2 */
H A Dmce.h30 unsigned long pal_base; /* Base address for PALcode. */
/linux-4.1.27/drivers/net/wan/
H A Dpci200syn.c56 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
57 u32 loc_rom_base; /* 24h : Local ROM Base */
60 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
H A Dpc300too.c68 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
69 u32 loc_rom_base; /* 24h : Local ROM Base */
72 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
/linux-4.1.27/arch/mips/include/asm/mach-rc32434/
H A Dpci.h219 * PCI Local Base Address [0|1|2|3] Register
226 * PCI Local Base Address Control Register
240 * PCI Local Base Address [0|1|2|3] Mapping Register
/linux-4.1.27/arch/arm/mach-pxa/
H A Dvpac270.c598 [0] = { /* I/O Base address */
603 [1] = { /* CTL Base address */
608 [2] = { /* DMA Base address */
/linux-4.1.27/sound/pci/aw2/
H A Daw2-saa7146.c188 /* Base address for DMA transfert. */ snd_aw2_saa7146_pcm_init_playback()
199 /* Base address for DMA transfert. */ snd_aw2_saa7146_pcm_init_playback()
245 /* Base address for DMA transfert. */ snd_aw2_saa7146_pcm_init_capture()
/linux-4.1.27/drivers/ide/
H A Dfalconide.c28 * Base of the IDE interface
H A Dmacide.c26 #define IDE_BASE 0x50F1A000 /* Base address of IDE controller */
/linux-4.1.27/drivers/net/dsa/
H A Dbcm_sf2.h54 /* Base registers, keep those in order with BCM_SF2_REGS_NAME */
/linux-4.1.27/drivers/net/ethernet/amd/
H A Dariadne.h84 #define CSR24 0x1800 /* - Base Address of Receive Ring */
85 #define CSR25 0x1900 /* - Base Address of Receive Ring */
90 #define CSR30 0x1e00 /* - Base Address of Transmit Ring */
91 #define CSR31 0x1f00 /* - Base Address of transmit Ring */
H A Dariadne.c455 lance->RAP = CSR30; /* Base Address of Transmit Ring */ ariadne_open()
457 lance->RAP = CSR31; /* Base Address of transmit Ring */ ariadne_open()
461 lance->RAP = CSR24; /* Base Address of Receive Ring */ ariadne_open()
463 lance->RAP = CSR25; /* Base Address of Receive Ring */ ariadne_open()
/linux-4.1.27/drivers/misc/mic/host/
H A Dmic_smpt.h35 * @dma_addr: Base DMA address for this SMPT entry.
/linux-4.1.27/drivers/scsi/qla2xxx/
H A Dqla_dfs.c28 seq_printf(s, "Base = %llx\n\n", (unsigned long long) ha->fce_dma); qla2x00_dfs_fce_show()
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Dni_labpc_pci.c54 #define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */
H A Dpcl724.c19 * [0] - IO Base
H A Dmite.h119 MITE_IODWBSR = 0xc0, /* IO Device Window Base Size Register */
120 MITE_IODWBSR_1 = 0xc4, /* IO Device Window Base Size Register 1 */
H A Dpcl812.c42 * [0] - IO Base
58 * [0] - IO Base
70 * [0] - IO Base
82 * [0] - IO Base
90 * [0] - IO Base
96 * [0] - IO Base
99 * [0] - IO Base
104 * [0] - IO Base
H A Dpcm3724.c11 [0] - IO Base
/linux-4.1.27/arch/x86/include/asm/xen/
H A Dcpuid.h67 * EBX: Base address of Xen-specific MSRs.
/linux-4.1.27/arch/x86/realmode/
H A Dinit.c25 printk(KERN_DEBUG "Base memory trampoline at [%p] %llx size %zu\n", reserve_real_mode()
/linux-4.1.27/drivers/clk/
H A Dclk-nspire.c135 pr_info("TI-NSPIRE Base: %uMHz CPU: %uMHz AHB: %uMHz\n", nspire_clk_setup()
/linux-4.1.27/arch/metag/mm/
H A Dmmu-meta1.c85 /* Base of the pgd table plus our 4Meg entry, 4bytes each */ pgd_entry_addr()
/linux-4.1.27/arch/mips/include/asm/netlogic/xlr/
H A Diomap.h100 * Base Address (Virtual) of the PCI Config address space
/linux-4.1.27/arch/cris/include/arch-v32/arch/
H A Dptrace.h32 #define PT_BP 26 /* Base number for BP registers. */
/linux-4.1.27/arch/arm/mach-w90x900/
H A Dgpio.c50 void __iomem *regbase; /* Base of group register*/
/linux-4.1.27/include/linux/mfd/samsung/
H A Dcore.h58 * @irq_base: Base IRQ number for device, required for IRQs
/linux-4.1.27/drivers/net/ethernet/marvell/
H A Dskge.h962 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
963 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
991 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
992 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1136 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1146 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1147 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1161 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1162 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1163 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1164 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1290 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1291 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1302 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1303 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1304 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1305 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1306 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1314 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1315 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1326 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1662 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
H A Dsky2.h1036 HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */
1046 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
1153 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1154 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1254 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1255 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1275 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1276 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1277 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1278 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1279 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1287 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1288 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1299 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1432 PHY_M_10B_TE_ENABLE = 1<<7, /* 10Base-Te Enable (88E8079 and above) */
1615 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1617 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1673 GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */
/linux-4.1.27/drivers/net/ethernet/freescale/
H A Ducc_geth.c368 pr_info("Base address: 0x%08x\n", dump_init_enet_entries()
589 pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs); dump_regs()
700 pr_info("Base address: 0x%08x\n", dump_regs()
704 pr_info("Base address: 0x%08x\n", dump_regs()
734 pr_info("Base address: 0x%08x\n", dump_regs()
738 pr_info("Base address: 0x%08x\n", dump_regs()
746 pr_info("Base address: 0x%08x\n", dump_regs()
753 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram); dump_regs()
823 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram); dump_regs()
910 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg); dump_regs()
913 pr_info("Base address: 0x%08x\n", dump_regs()
921 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler); dump_regs()
927 pr_info("Base address: 0x%08x\n", dump_regs()
934 pr_info("Base address: 0x%08x\n", dump_regs()
941 pr_info("Base address: 0x%08x\n", dump_regs()
945 pr_info("Base address: 0x%08x\n", dump_regs()
964 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl); dump_regs()
967 pr_info("Base address: 0x%08x\n", dump_regs()
983 pr_info("Base address: 0x%08x\n", dump_regs()
997 pr_info("Base address: 0x%08x\n", dump_regs()
3847 * 4 UECs at 1000Base-T simultaneously, we need to allocate ucc_geth_probe()
/linux-4.1.27/drivers/irqchip/
H A Dspear-shirq.c32 * base: Base register address
36 * virq_base: Base virtual interrupt number
/linux-4.1.27/drivers/mmc/host/
H A Dsdhci-pci-o2micro.c267 /* Set Base Clock to 208MZ */ sdhci_pci_o2_probe()
273 /* Enable Base Clk setting change */ sdhci_pci_o2_probe()
/linux-4.1.27/drivers/net/irda/
H A Dali-ircc.h129 #define FIR_IO_BASE_HI 0x02 /* Alias 2, FIR Higher I/O Base Address Register (R/O) */
130 #define FIR_IO_BASE_LO 0x03 /* Alias 3, FIR Lower I/O Base Address Register (R/O) */
/linux-4.1.27/drivers/base/regmap/
H A Dregmap-spmi.c95 * regmap_init_spmi_base(): Create regmap for the Base register space
110 * devm_regmap_init_spmi_base(): Create managed regmap for Base register space
/linux-4.1.27/drivers/clk/keystone/
H A Dgate.c50 * @control_base: Base address for a PSC control
51 * @domain_base: Base address for a PSC domain
/linux-4.1.27/drivers/tty/serial/jsm/
H A Djsm_driver.c146 /* Get the PCI Base Address Registers */ jsm_probe_one()
198 /* get the PCI Base Address Registers */ jsm_probe_one()
/linux-4.1.27/drivers/usb/c67x00/
H A Dc67x00.h169 #define CY_HCD_BUF_ADDR 0x500 /* Base address for host */
176 /* Base address of HCD + 2 x TD_SIZE + 2 x TD_BUF_SIZE */
/linux-4.1.27/drivers/usb/gadget/udc/
H A Dmv_u3d.h135 u32 dcbaapl; /* Device Context Base Address low register */
136 u32 dcbaaph; /* Device Context Base Address high register */
/linux-4.1.27/drivers/watchdog/
H A Dibmasr.c54 #define JUNIPER_BASE_ADDRESS 0x54b /* Base address of Juniper ASR */
58 #define SPRUCE_BASE_ADDRESS 0x118e /* Base address of Spruce ASR */
/linux-4.1.27/arch/arm/mach-integrator/
H A Dintegrator_ap.c56 /* Base address to the AP system controller */
58 /* Base address to the external bus interface */
/linux-4.1.27/arch/arc/include/asm/
H A Darcregs.h13 #define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */
245 /* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
/linux-4.1.27/sound/isa/ad1816a/
H A Dad1816a.c40 "{TerraTec,Base 64},"
85 /* Analog Devices AD1816A - Terratec Base 64 */
/linux-4.1.27/sound/oss/
H A Dmsnd.c3 * msnd.c - Driver Base
401 MODULE_DESCRIPTION ("Turtle Beach MultiSound Driver Base");
/linux-4.1.27/drivers/net/fddi/skfp/h/
H A Dskfbi.h44 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
45 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
49 #define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */
121 /* Byte 2: Base Class (02) */
139 /* PCI_BASE_1ST 32 bit 1st Base address */
140 #define PCI_MEMSIZE 0x800L /* use 2 kB Memory Base */
141 #define PCI_MEMBASE_BITS 0xfffff800L /* Bit 31..11: Memory Base Address */
145 #define PCI_MEM32BIT (0<<1) /* Base addr anywhere in 32 Bit range */
146 #define PCI_MEM1M (1<<1) /* Base addr below 1 MegaByte */
147 #define PCI_MEM64BIT (2<<1) /* Base addr anywhere in 64 Bit range */
153 /* PCI_BASE_ROM 32 bit Expansion ROM Base Address */
199 #define PCI_SKEW_BASE (0xfL<<0) /* Bit 3..0: Skew Ctrl, Base */
352 #define B2_DESC_ADDR_H 0x0150 /* (ML) 32 bit Desciptor Base Addr Reg High */
672 /* B2_DESC_ADDR_H 0x0150 (ML) 32 bit Desciptor Base Addr Reg High */
/linux-4.1.27/drivers/net/ethernet/intel/ixgb/
H A Dixgb_hw.h133 #define IXGB_RDBAL 0x00118 /* RX Descriptor Base Low - RW */
134 #define IXGB_RDBAH 0x0011C /* RX Descriptor Base High - RW */
142 #define IXGB_RA 0x00180 /* Receive Address Array Base - RW */
151 #define IXGB_TDBAL 0x00608 /* TX Descriptor Base Low - RW */
152 #define IXGB_TDBAH 0x0060C /* TX Descriptor Base High - RW */
664 u8 __iomem *hw_addr;/* Base Address of the hardware */
686 u32 bar0; /* Base Address registers */
/linux-4.1.27/drivers/media/platform/s5p-jpeg/
H A Djpeg-regs.h443 * Base address of the luma component DMA buffer
460 * Base address of the chroma(Cb) component DMA buffer
476 * Base address of the chroma(Cr) component DMA buffer
/linux-4.1.27/include/uapi/sound/
H A Demu10k1.h89 #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
240 #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
241 #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
/linux-4.1.27/drivers/isdn/act2000/
H A Dact2000.h152 unsigned short port; /* Base-port-address */
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dt4vf_defs.h47 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
/linux-4.1.27/drivers/media/pci/zoran/
H A Dzr36057.h151 #define ZR36057_JCBA 0x11c /* JPEG Code Base Address */
/linux-4.1.27/drivers/media/platform/exynos4-is/
H A Dfimc-is-regs.h26 /* Boot Base Offset Address Register */
/linux-4.1.27/drivers/mfd/
H A D88pm805.c2 * Base driver for Marvell 88PM805
/linux-4.1.27/drivers/scsi/qla4xxx/
H A Dql4_def.h619 struct isp_reg __iomem *reg; /* Base I/O address */
738 struct device_reg_82xx __iomem *qla4_82xx_reg; /* Base I/O address */
739 unsigned long nx_pcibase; /* Base I/O address */
825 struct device_reg_83xx __iomem *qla4_83xx_reg; /* Base I/O address
/linux-4.1.27/drivers/staging/media/dt3155v4l/
H A Ddt3155v4l.h38 /* DT3155 Base Register offsets (memory mapped) */
/linux-4.1.27/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_flat_memory.c112 * A 64b pointer is compared to the apertures that are defined (Base/Limit), in
163 * An aperture register definition consists of a Base, Limit, Mtype, and
173 * inside an aperture means (address >= Base) AND (address <= Limit).
235 * in the 32b space except at 0 (Private or Shared Base at zero disables
/linux-4.1.27/arch/x86/realmode/rm/
H A Dreboot.S131 .long 0 /* Base - real mode default value */
/linux-4.1.27/arch/sparc/kernel/
H A Dpci_impl.h102 /* Base of PCI Config space, can be per-PBM or shared. */
/linux-4.1.27/drivers/virtio/
H A Dvirtio_pci_common.h65 /* Base of vq notifications (non-legacy mode). */
/linux-4.1.27/arch/s390/include/asm/
H A Dpci.h134 /* Base stuff */
/linux-4.1.27/arch/sh/kernel/cpu/irq/
H A Dintc-sh5.c34 /* Base */
/linux-4.1.27/arch/mips/include/asm/octeon/
H A Dcvmx-sysinfo.h97 * Base address of the LED display (as on EBT3000 board) This
/linux-4.1.27/arch/ia64/include/asm/
H A Dkregs.h34 #define IA64_TR_ALLOC_BASE 2 /* itr&dtr: Base of dynamic TR resource*/

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