/linux-4.4.14/arch/parisc/include/asm/ |
H A D | special_insns.h | 13 #define mtctl(gr, cr) \ macro 14 __asm__ __volatile__("mtctl %0,%1" \ 23 mtctl(val, 15); set_eiem()
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H A D | mmu_context.h | 49 mtctl(__space_to_prot(context), 8); load_context() 56 mtctl(__pa(next->pgd), 25); switch_mm()
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H A D | assembly.h | 178 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r 383 mtctl %r3, %cr27 427 mtctl %r3, %cr27 443 mtctl %r0, %cr17 447 mtctl %r0, %cr18 452 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
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/linux-4.4.14/arch/parisc/kernel/ |
H A D | head.S | 74 mtctl %r4,%cr24 /* Initialize kernel root pointer */ 75 mtctl %r4,%cr25 /* Initialize user root pointer */ 127 mtctl %r6,%cr30 206 mtctl %r6,%cr30 /* restore task thread info */ 222 mtctl %r0,%cr8 223 mtctl %r0,%cr9 224 mtctl %r0,%cr12 225 mtctl %r0,%cr13 238 mtctl %r10,%cr11 253 mtctl %r10,%cr14 265 mtctl %r0,%cr17 /* Clear IIASQ tail */ 266 mtctl %r0,%cr17 /* Clear IIASQ head */ 269 mtctl %r11,%cr18 /* IIAOQ head */ 271 mtctl %r11,%cr18 /* IIAOQ tail */ 274 mtctl %r10,%ipsw 322 mtctl %sp,%cr30 /* store in cr30 */ 327 mtctl %r4,%cr24 /* Initialize kernel root pointer */ 328 mtctl %r4,%cr25 /* Initialize user root pointer */
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H A D | real2.S | 126 # define POP_CR(r, where) LDREG,mb -REG_SZ(where), %r1 ! mtctl %r1, r 173 mtctl %r0, %cr17 /* Clear IIASQ tail */ 174 mtctl %r0, %cr17 /* Clear IIASQ head */ 175 mtctl %r1, %cr18 /* IIAOQ head */ 177 mtctl %r1, %cr18 /* IIAOQ tail */ 179 mtctl %r1, %cr22 207 mtctl %r0, %cr17 /* Clear IIASQ tail */ 208 mtctl %r0, %cr17 /* Clear IIASQ head */ 209 mtctl %r1, %cr18 /* IIAOQ head */ 211 mtctl %r1, %cr18 /* IIAOQ tail */ 213 mtctl %r1, %cr22
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H A D | hpmc.S | 135 mtctl %r4,ipsw 136 mtctl %r0,pcsq 137 mtctl %r0,pcsq 139 mtctl %r4,pcoq 141 mtctl %r4,pcoq 244 mtctl %r4,%cr24 /* Initialize kernel root pointer */ 245 mtctl %r4,%cr25 /* Initialize user root pointer */
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H A D | pacache.S | 66 mtctl %r0, %cr17 /* Clear IIASQ tail */ 67 mtctl %r0, %cr17 /* Clear IIASQ head */ 68 mtctl %r1, %cr18 /* IIAOQ head */ 70 mtctl %r1, %cr18 /* IIAOQ tail */ 72 mtctl %r1, %ipsw 177 mtctl %r0, %cr17 /* Clear IIASQ tail */ 178 mtctl %r0, %cr17 /* Clear IIASQ head */ 179 mtctl %r1, %cr18 /* IIAOQ head */ 181 mtctl %r1, %cr18 /* IIAOQ tail */ 184 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */ 1221 mtctl %r0, %cr17 /* Clear IIASQ tail */ 1222 mtctl %r0, %cr17 /* Clear IIASQ head */ 1223 mtctl %r1, %cr18 /* IIAOQ head */ 1225 mtctl %r1, %cr18 /* IIAOQ tail */ 1227 mtctl %r1, %ipsw 1277 mtctl %r0, %cr17 /* Clear IIASQ tail */ 1278 mtctl %r0, %cr17 /* Clear IIASQ head */ 1279 mtctl %r1, %cr18 /* IIAOQ head */ 1281 mtctl %r1, %cr18 /* IIAOQ tail */ 1283 mtctl %r1, %ipsw
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H A D | time.c | 109 mtctl(next_tick, 16); timer_interrupt() 123 mtctl(next_tick+cpt, 16); timer_interrupt() 222 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ start_cpu_itimer()
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H A D | perf_asm.S | 56 mtctl %r26,ccr ; turn on performance coprocessor 61 mtctl %r26,ccr ; turn off performance coprocessor 82 mtctl %r26,ccr ; turn on performance coprocessor 87 mtctl %r26,ccr ; turn off performance coprocessor
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H A D | entry.S | 73 mtctl %r0, %cr17 /* Clear IIASQ tail */ 74 mtctl %r0, %cr17 /* Clear IIASQ head */ 75 mtctl %r1, %ipsw 77 mtctl %r1, %cr18 /* Set IIAOQ tail */ 79 mtctl %r1, %cr18 /* Set IIAOQ head */ 808 mtctl %r25,%cr30 811 mtctl %r0, %cr0 /* Needed for single stepping */ 1371 mtctl %r8,%ipsw 1747 mtctl %r3, %cr27 1901 mtctl %r2,%cr0 /* for immediate trap */
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H A D | irq.c | 95 mtctl(mask, 23); cpu_ack_irq() 594 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */ init_IRQ()
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H A D | setup.c | 400 mtctl(coproc_cfg.ccr_functional, 10); start_parisc()
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H A D | processor.c | 311 mtctl(coproc_cfg.ccr_functional, 10); /* 10 == Coprocessor Control Reg */ init_per_cpu()
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H A D | signal.c | 379 mtctl(-1, 0); setup_rt_frame()
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H A D | unaligned.c | 185 " mtctl %%r19,11\n" emulate_ldw()
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H A D | syscall.S | 94 mtctl %r26, %cr27 /* move arg0 to the control register */
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