Searched refs:ipg (Results 1 - 56 of 56) sorted by relevance

/linux-4.4.14/drivers/clk/imx/
H A Dclk-imx27.c39 "ahb", "ipg", "per1_div", "per2_div",
80 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); _mx27_clocks_init()
83 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); _mx27_clocks_init()
109 clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0); _mx27_clocks_init()
110 clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1); _mx27_clocks_init()
111 clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2); _mx27_clocks_init()
112 clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3); _mx27_clocks_init()
113 clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4); _mx27_clocks_init()
114 clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5); _mx27_clocks_init()
115 clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6); _mx27_clocks_init()
116 clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7); _mx27_clocks_init()
117 clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8); _mx27_clocks_init()
118 clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9); _mx27_clocks_init()
119 clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11); _mx27_clocks_init()
120 clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12); _mx27_clocks_init()
121 clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13); _mx27_clocks_init()
122 clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14); _mx27_clocks_init()
123 clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15); _mx27_clocks_init()
124 clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16); _mx27_clocks_init()
125 clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17); _mx27_clocks_init()
126 clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18); _mx27_clocks_init()
127 clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19); _mx27_clocks_init()
128 clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20); _mx27_clocks_init()
129 clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21); _mx27_clocks_init()
130 clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22); _mx27_clocks_init()
131 clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23); _mx27_clocks_init()
132 clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24); _mx27_clocks_init()
133 clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25); _mx27_clocks_init()
134 clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26); _mx27_clocks_init()
135 clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27); _mx27_clocks_init()
136 clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28); _mx27_clocks_init()
137 clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29); _mx27_clocks_init()
138 clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30); _mx27_clocks_init()
139 clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31); _mx27_clocks_init()
162 clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24); _mx27_clocks_init()
163 clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25); _mx27_clocks_init()
164 clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26); _mx27_clocks_init()
165 clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27); _mx27_clocks_init()
166 clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28); _mx27_clocks_init()
167 clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29); _mx27_clocks_init()
168 clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30); _mx27_clocks_init()
169 clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31); _mx27_clocks_init()
188 clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); mx27_clocks_init()
190 clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); mx27_clocks_init()
192 clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); mx27_clocks_init()
194 clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); mx27_clocks_init()
196 clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4"); mx27_clocks_init()
198 clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5"); mx27_clocks_init()
200 clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); mx27_clocks_init()
203 clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0"); mx27_clocks_init()
205 clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1"); mx27_clocks_init()
207 clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2"); mx27_clocks_init()
209 clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0"); mx27_clocks_init()
211 clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1"); mx27_clocks_init()
213 clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2"); mx27_clocks_init()
215 clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); mx27_clocks_init()
220 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27"); mx27_clocks_init()
223 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0"); mx27_clocks_init()
226 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1"); mx27_clocks_init()
229 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2"); mx27_clocks_init()
237 clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma"); mx27_clocks_init()
238 clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0"); mx27_clocks_init()
246 clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0"); mx27_clocks_init()
248 clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0"); mx27_clocks_init()
H A Dclk-imx21.c60 clk[IMX21_CLK_IPG] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1); _mx21_clocks_init()
82 clk[IMX21_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0); _mx21_clocks_init()
83 clk[IMX21_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1); _mx21_clocks_init()
84 clk[IMX21_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2); _mx21_clocks_init()
85 clk[IMX21_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3); _mx21_clocks_init()
86 clk[IMX21_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4); _mx21_clocks_init()
87 clk[IMX21_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5); _mx21_clocks_init()
88 clk[IMX21_CLK_SSI1_GATE] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6); _mx21_clocks_init()
89 clk[IMX21_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7); _mx21_clocks_init()
90 clk[IMX21_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9); _mx21_clocks_init()
91 clk[IMX21_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10); _mx21_clocks_init()
92 clk[IMX21_CLK_GPIO_GATE] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11); _mx21_clocks_init()
93 clk[IMX21_CLK_I2C_GATE] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12); _mx21_clocks_init()
94 clk[IMX21_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13); _mx21_clocks_init()
96 clk[IMX21_CLK_EMMA_GATE] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15); _mx21_clocks_init()
97 clk[IMX21_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16); _mx21_clocks_init()
98 clk[IMX21_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17); _mx21_clocks_init()
99 clk[IMX21_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18); _mx21_clocks_init()
112 clk[IMX21_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23); _mx21_clocks_init()
113 clk[IMX21_CLK_WDOG_GATE] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24); _mx21_clocks_init()
114 clk[IMX21_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25); _mx21_clocks_init()
115 clk[IMX21_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26); _mx21_clocks_init()
116 clk[IMX21_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27); _mx21_clocks_init()
117 clk[IMX21_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28); _mx21_clocks_init()
118 clk[IMX21_CLK_RTC_GATE] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29); _mx21_clocks_init()
119 clk[IMX21_CLK_KPP_GATE] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30); _mx21_clocks_init()
120 clk[IMX21_CLK_OWIRE_GATE] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31); _mx21_clocks_init()
132 clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); mx21_clocks_init()
134 clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); mx21_clocks_init()
136 clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); mx21_clocks_init()
138 clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); mx21_clocks_init()
139 clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); mx21_clocks_init()
142 clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0"); mx21_clocks_init()
144 clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1"); mx21_clocks_init()
146 clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2"); mx21_clocks_init()
148 clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); mx21_clocks_init()
154 clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma"); mx21_clocks_init()
H A Dclk-imx35.c69 ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg, enumerator in enum:mx35_clks
88 &clk[ipg],
143 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); _mx35_clocks_init()
175 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); _mx35_clocks_init()
176 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); _mx35_clocks_init()
177 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); _mx35_clocks_init()
178 clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6); _mx35_clocks_init()
179 clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8); _mx35_clocks_init()
180 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10); _mx35_clocks_init()
181 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12); _mx35_clocks_init()
182 clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14); _mx35_clocks_init()
183 clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16); _mx35_clocks_init()
184 clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18); _mx35_clocks_init()
185 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20); _mx35_clocks_init()
186 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22); _mx35_clocks_init()
187 clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24); _mx35_clocks_init()
192 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0); _mx35_clocks_init()
193 clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2); _mx35_clocks_init()
194 clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4); _mx35_clocks_init()
195 clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6); _mx35_clocks_init()
196 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8); _mx35_clocks_init()
200 clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16); _mx35_clocks_init()
202 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20); _mx35_clocks_init()
207 clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30); _mx35_clocks_init()
209 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0); _mx35_clocks_init()
211 clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4); _mx35_clocks_init()
213 clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8); _mx35_clocks_init()
221 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24); _mx35_clocks_init()
223 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); _mx35_clocks_init()
226 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); _mx35_clocks_init()
261 clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0"); mx35_clocks_init()
263 clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1"); mx35_clocks_init()
267 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0"); mx35_clocks_init()
270 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1"); mx35_clocks_init()
273 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2"); mx35_clocks_init()
278 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); mx35_clocks_init()
291 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); mx35_clocks_init()
293 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); mx35_clocks_init()
295 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); mx35_clocks_init()
298 clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc"); mx35_clocks_init()
300 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); mx35_clocks_init()
303 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); mx35_clocks_init()
306 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); mx35_clocks_init()
309 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); mx35_clocks_init()
H A Dclk-imx31.c46 static const char *per_sel[] = { "per_div", "ipg", };
51 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator in enum:mx31_clks
66 &clk[ipg],
93 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); _mx31_clocks_init()
108 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10); _mx31_clocks_init()
109 clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12); _mx31_clocks_init()
111 clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16); _mx31_clocks_init()
112 clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18); _mx31_clocks_init()
123 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8); _mx31_clocks_init()
124 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10); _mx31_clocks_init()
129 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20); _mx31_clocks_init()
136 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2); _mx31_clocks_init()
137 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4); _mx31_clocks_init()
167 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); mx31_clocks_init()
174 clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc"); mx31_clocks_init()
183 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); mx31_clocks_init()
186 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); mx31_clocks_init()
189 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); mx31_clocks_init()
192 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); mx31_clocks_init()
196 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); mx31_clocks_init()
198 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); mx31_clocks_init()
200 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); mx31_clocks_init()
202 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3"); mx31_clocks_init()
204 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4"); mx31_clocks_init()
H A Dclk-imx25.c61 "ipg", "dummy", "dummy", "dummy",
66 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator in enum:mx25_clks
113 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); __mx25_clocks_init()
180 clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2); __mx25_clocks_init()
181 clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3); __mx25_clocks_init()
182 clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4); __mx25_clocks_init()
183 clk[cspi1_ipg] = imx_clk_gate("cspi1_ipg", "ipg", ccm(CCM_CGCR1), 5); __mx25_clocks_init()
184 clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6); __mx25_clocks_init()
185 clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7); __mx25_clocks_init()
186 clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8); __mx25_clocks_init()
187 clk[ect_ipg] = imx_clk_gate("ect_ipg", "ipg", ccm(CCM_CGCR1), 9); __mx25_clocks_init()
188 clk[epit1_ipg] = imx_clk_gate("epit1_ipg", "ipg", ccm(CCM_CGCR1), 10); __mx25_clocks_init()
189 clk[epit2_ipg] = imx_clk_gate("epit2_ipg", "ipg", ccm(CCM_CGCR1), 11); __mx25_clocks_init()
191 clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13); __mx25_clocks_init()
192 clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14); __mx25_clocks_init()
193 clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15); __mx25_clocks_init()
197 clk[gpt1_ipg] = imx_clk_gate("gpt1_ipg", "ipg", ccm(CCM_CGCR1), 19); __mx25_clocks_init()
198 clk[gpt2_ipg] = imx_clk_gate("gpt2_ipg", "ipg", ccm(CCM_CGCR1), 20); __mx25_clocks_init()
199 clk[gpt3_ipg] = imx_clk_gate("gpt3_ipg", "ipg", ccm(CCM_CGCR1), 21); __mx25_clocks_init()
200 clk[gpt4_ipg] = imx_clk_gate("gpt4_ipg", "ipg", ccm(CCM_CGCR1), 22); __mx25_clocks_init()
204 clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26); __mx25_clocks_init()
207 clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28); __mx25_clocks_init()
208 clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29); __mx25_clocks_init()
210 clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31); __mx25_clocks_init()
211 clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2), 0); __mx25_clocks_init()
212 clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2), 1); __mx25_clocks_init()
213 clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2), 2); __mx25_clocks_init()
214 clk[rngb_ipg] = imx_clk_gate("rngb_ipg", "ipg", ccm(CCM_CGCR2), 3); __mx25_clocks_init()
216 clk[scc_ipg] = imx_clk_gate("scc_ipg", "ipg", ccm(CCM_CGCR2), 5); __mx25_clocks_init()
217 clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2), 6); __mx25_clocks_init()
218 clk[sim1_ipg] = imx_clk_gate("sim1_ipg", "ipg", ccm(CCM_CGCR2), 7); __mx25_clocks_init()
219 clk[sim2_ipg] = imx_clk_gate("sim2_ipg", "ipg", ccm(CCM_CGCR2), 8); __mx25_clocks_init()
220 clk[slcdc_ipg] = imx_clk_gate("slcdc_ipg", "ipg", ccm(CCM_CGCR2), 9); __mx25_clocks_init()
221 clk[spba_ipg] = imx_clk_gate("spba_ipg", "ipg", ccm(CCM_CGCR2), 10); __mx25_clocks_init()
222 clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11); __mx25_clocks_init()
223 clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12); __mx25_clocks_init()
224 clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13); __mx25_clocks_init()
225 clk[uart1_ipg] = imx_clk_gate("uart1_ipg", "ipg", ccm(CCM_CGCR2), 14); __mx25_clocks_init()
226 clk[uart2_ipg] = imx_clk_gate("uart2_ipg", "ipg", ccm(CCM_CGCR2), 15); __mx25_clocks_init()
227 clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16); __mx25_clocks_init()
228 clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17); __mx25_clocks_init()
229 clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18); __mx25_clocks_init()
231 clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19); __mx25_clocks_init()
241 * Let's initially set up CLKO parent as ipg, since this configuration __mx25_clocks_init()
244 clk_set_parent(clk[cko_sel], clk[ipg]); __mx25_clocks_init()
H A Dclk-imx51-imx53.c76 static const char *per_root_sel[] = { "per_podf", "ipg", };
99 static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
104 "ipg", "per_root", "ckil", "dummy",};
173 clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0); mx5_clocks_common_init()
174 clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2); mx5_clocks_common_init()
213 clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); mx5_clocks_common_init()
214 clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); mx5_clocks_common_init()
216 clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10); mx5_clocks_common_init()
218 clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14); mx5_clocks_common_init()
222 clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); mx5_clocks_common_init()
224 clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); mx5_clocks_common_init()
226 clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); mx5_clocks_common_init()
228 clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); mx5_clocks_common_init()
229 clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); mx5_clocks_common_init()
231 clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0); mx5_clocks_common_init()
232 clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4); mx5_clocks_common_init()
233 clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8); mx5_clocks_common_init()
234 clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12); mx5_clocks_common_init()
235 clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16); mx5_clocks_common_init()
236 clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20); mx5_clocks_common_init()
237 clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24); mx5_clocks_common_init()
238 clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18); mx5_clocks_common_init()
240 clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22); mx5_clocks_common_init()
242 clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26); mx5_clocks_common_init()
243 clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30); mx5_clocks_common_init()
259 clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8); mx5_clocks_common_init()
261 clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12); mx5_clocks_common_init()
286 clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); mx5_clocks_common_init()
288 clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); mx5_clocks_common_init()
292 clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); mx5_clocks_common_init()
299 clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); mx5_clocks_common_init()
300 clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14); mx5_clocks_common_init()
433 clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22); mx51_clocks_init()
434 clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6); mx51_clocks_init()
435 clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); mx51_clocks_init()
436 clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); mx51_clocks_init()
437 clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); mx51_clocks_init()
539 clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); mx53_clocks_init()
542 clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); mx53_clocks_init()
544 clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2); mx53_clocks_init()
H A Dclk-imx1.c87 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0"); mx1_clocks_init()
89 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma"); mx1_clocks_init()
91 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0"); mx1_clocks_init()
93 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1"); mx1_clocks_init()
95 clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2"); mx1_clocks_init()
98 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0"); mx1_clocks_init()
100 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1"); mx1_clocks_init()
102 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0"); mx1_clocks_init()
H A Dclk-imx6ul.c63 static const char *perclk_sels[] = { "ipg", "osc", };
264 clks[IMX6UL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); imx6ul_clocks_init()
303 clks[IMX6UL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); imx6ul_clocks_init()
304 clks[IMX6UL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); imx6ul_clocks_init()
306 clks[IMX6UL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); imx6ul_clocks_init()
310 clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28); imx6ul_clocks_init()
319 clks[IMX6UL_CLK_ADC2] = imx_clk_gate2("adc2", "ipg", base + 0x6c, 8); imx6ul_clocks_init()
320 clks[IMX6UL_CLK_UART3_IPG] = imx_clk_gate2("uart3_ipg", "ipg", base + 0x6c, 10); imx6ul_clocks_init()
324 clks[IMX6UL_CLK_ADC1] = imx_clk_gate2("adc1", "ipg", base + 0x6c, 16); imx6ul_clocks_init()
327 clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24); imx6ul_clocks_init()
335 clks[IMX6UL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); imx6ul_clocks_init()
341 clks[IMX6UL_CLK_UART5_IPG] = imx_clk_gate2("uart5_ipg", "ipg", base + 0x74, 2); imx6ul_clocks_init()
343 clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4); imx6ul_clocks_init()
345 clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6); imx6ul_clocks_init()
349 clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16); imx6ul_clocks_init()
351 clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24); imx6ul_clocks_init()
368 clks[IMX6UL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10); imx6ul_clocks_init()
369 clks[IMX6UL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); imx6ul_clocks_init()
371 clks[IMX6UL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio); imx6ul_clocks_init()
373 clks[IMX6UL_CLK_SAI3_IPG] = imx_clk_gate2_shared("sai3_ipg", "ipg", base + 0x7c, 22, &share_count_sai3); imx6ul_clocks_init()
374 clks[IMX6UL_CLK_UART1_IPG] = imx_clk_gate2("uart1_ipg", "ipg", base + 0x7c, 24); imx6ul_clocks_init()
376 clks[IMX6UL_CLK_UART7_IPG] = imx_clk_gate2("uart7_ipg", "ipg", base + 0x7c, 26); imx6ul_clocks_init()
379 clks[IMX6UL_CLK_SAI1_IPG] = imx_clk_gate2_shared("sai1_ipg", "ipg", base + 0x7c, 28, &share_count_sai1); imx6ul_clocks_init()
381 clks[IMX6UL_CLK_SAI2_IPG] = imx_clk_gate2_shared("sai2_ipg", "ipg", base + 0x7c, 30, &share_count_sai2); imx6ul_clocks_init()
384 clks[IMX6UL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); imx6ul_clocks_init()
391 clks[IMX6UL_CLK_UART8_IPG] = imx_clk_gate2("uart8_ipg", "ipg", base + 0x80, 14); imx6ul_clocks_init()
393 clks[IMX6UL_CLK_WDOG3] = imx_clk_gate2("wdog3", "ipg", base + 0x80, 20); imx6ul_clocks_init()
H A Dclk-imx6sx.c47 static const char *perclk_sels[] = { "ipg", "osc", };
68 "epdc_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
327 clks[IMX6SX_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); imx6sx_clocks_init()
389 clks[IMX6SX_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); imx6sx_clocks_init()
390 clks[IMX6SX_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); imx6sx_clocks_init()
392 clks[IMX6SX_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); imx6sx_clocks_init()
409 clks[IMX6SX_CLK_WAKEUP] = imx_clk_gate2("wakeup", "ipg", base + 0x6c, 18); imx6sx_clocks_init()
420 clks[IMX6SX_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); imx6sx_clocks_init()
431 clks[IMX6SX_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4); imx6sx_clocks_init()
440 clks[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24); imx6sx_clocks_init()
460 clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); imx6sx_clocks_init()
463 clks[IMX6SX_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio); imx6sx_clocks_init()
464 clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); imx6sx_clocks_init()
465 clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); imx6sx_clocks_init()
466 clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); imx6sx_clocks_init()
470 clks[IMX6SX_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); imx6sx_clocks_init()
472 clks[IMX6SX_CLK_SAI1_IPG] = imx_clk_gate2("sai1_ipg", "ipg", base + 0x7c, 28); imx6sx_clocks_init()
473 clks[IMX6SX_CLK_SAI2_IPG] = imx_clk_gate2("sai2_ipg", "ipg", base + 0x7c, 30); imx6sx_clocks_init()
478 clks[IMX6SX_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); imx6sx_clocks_init()
H A Dclk-imx6sl.c49 static const char *perclk_sels[] = { "ipg", "osc", };
336 clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); imx6sl_clocks_init()
377 clks[IMX6SL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); imx6sl_clocks_init()
387 clks[IMX6SL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); imx6sl_clocks_init()
399 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); imx6sl_clocks_init()
400 clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); imx6sl_clocks_init()
402 clks[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); imx6sl_clocks_init()
403 clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); imx6sl_clocks_init()
404 clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); imx6sl_clocks_init()
405 clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); imx6sl_clocks_init()
409 clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24); imx6sl_clocks_init()
411 clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); imx6sl_clocks_init()
H A Dclk-imx6q.c58 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
336 clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); imx6q_clocks_init()
337 clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); imx6q_clocks_init()
393 clk[IMX6QDL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); imx6q_clocks_init()
394 clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); imx6q_clocks_init()
396 clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); imx6q_clocks_init()
406 clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); imx6q_clocks_init()
410 clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); imx6q_clocks_init()
426 clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); imx6q_clocks_init()
439 clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg); imx6q_clocks_init()
465 clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); imx6q_clocks_init()
467 clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); imx6q_clocks_init()
468 clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); imx6q_clocks_init()
469 clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); imx6q_clocks_init()
470 clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); imx6q_clocks_init()
474 clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); imx6q_clocks_init()
476 clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); imx6q_clocks_init()
/linux-4.4.14/drivers/usb/gadget/udc/
H A Dfsl_mxc_udc.c40 mxc_ipg_clk = devm_clk_get(&pdev->dev, "ipg"); fsl_udc_clk_init()
42 dev_err(&pdev->dev, "clk_get(\"ipg\") failed\n"); fsl_udc_clk_init()
/linux-4.4.14/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c749 * between 'per' and 'ipg' is broken; mpc512x_clk_setup_clock_tree()
1039 NODE_CHK("ipg", clks[MPC512x_CLK_PSC0 + idx], 0, PSC); mpc512x_select_psc_compat()
1045 NODE_CHK("ipg", clks[MPC512x_CLK_PSC_FIFO], 1, PSCFIFO);
1050 NODE_CHK("ipg", clks[MPC512x_CLK_NFC], 0, NFC);
1058 NODE_CHK("ipg", clks[MPC512x_CLK_BDLC], 0, CAN);
1065 * potential for a name conflict (in contrast to 'ipg' and 'mclk')
1075 NODE_CHK("ipg", clks[MPC512x_CLK_I2C], 0, I2C);
1081 * which we cannot register an alias -- a _global_ 'ipg' alias that
1090 * details, adjusting s/NULL/"ipg"/ in i2c-mpc.c would make this
1098 NODE_CHK("ipg", clks[MPC512x_CLK_DIU], 1, DIU);
1103 NODE_CHK("ipg", clks[MPC512x_CLK_VIU], 0, VIU);
1108 * "per" string for the clock lookup in contrast to the "ipg" name
1139 NODE_CHK("ipg", clks[MPC512x_CLK_USB1 + idx], 0, USB);
1144 NODE_CHK("ipg", clks[MPC512x_CLK_PATA], 0, PATA);
H A Dmpc512x_shared.c89 clk_diu = clk_get_sys(np->name, "ipg"); mpc512x_set_pixel_clock()
/linux-4.4.14/drivers/pwm/
H A Dpwm-imx.c296 imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); imx_pwm_probe()
298 dev_err(&pdev->dev, "getting ipg clock failed with %ld\n", imx_pwm_probe()
/linux-4.4.14/drivers/net/ethernet/amd/
H A Damd8111e.c1214 /* Delete ipg timer */ amd8111e_close()
1252 /* Start ipg timer */ amd8111e_open()
1684 /* Restart ipg timer */ amd8111e_resume()
1703 ipg_data->ipg = DEFAULT_IPG; amd8111e_config_ipg()
1712 ipg_data->ipg = MIN_IPG - IPG_STEP; amd8111e_config_ipg()
1734 ipg_data->ipg = ipg_data->current_ipg; amd8111e_config_ipg()
1742 tmp_ipg = ipg_data->ipg; amd8111e_config_ipg()
1903 /* Initialize software ipg timer */ amd8111e_probe_one()
1910 lp->ipg_data.ipg = DEFAULT_IPG; amd8111e_probe_one()
H A Damd8111e.h603 /* ipg parameters */
736 unsigned int ipg; member in struct:ipg_info
/linux-4.4.14/drivers/usb/host/
H A Dehci-mxc.c85 priv->usbclk = devm_clk_get(&pdev->dev, "ipg"); ehci_mxc_drv_probe()
H A Dfsl-mph-dr-of.c294 clk = devm_clk_get(pdev->dev.parent, "ipg"); fsl_usb2_mpc5121_init()
/linux-4.4.14/drivers/usb/chipidea/
H A Dci_hdrc_imx.c149 data->clk_ipg = devm_clk_get(dev, "ipg"); imx_get_clks()
192 "Failed to prepare/enable ipg clk, err=%d\n", imx_prepare_enable_clks()
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb3/
H A Dxgmac.c348 int ipg; t3_mac_set_mtu() local
413 ipg = (adap->params.rev == T3_REV_C) ? 0 : 1; t3_mac_set_mtu()
416 V_TXFIFOTHRESH(thres) | V_TXIPG(ipg)); t3_mac_set_mtu()
/linux-4.4.14/drivers/crypto/caam/
H A Dctrl.c437 clk = caam_drv_identify_clk(&pdev->dev, "ipg"); caam_probe()
441 "can't identify CAAM ipg clk: %d\n", ret); caam_probe()
475 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret); caam_probe()
/linux-4.4.14/drivers/rtc/
H A Drtc-mxc.c393 pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); mxc_rtc_probe()
395 dev_err(&pdev->dev, "unable to get ipg clock!\n"); mxc_rtc_probe()
/linux-4.4.14/drivers/clocksource/
H A Dtimer-imx-gpt.c461 imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); mxc_timer_init()
488 imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); mxc_timer_init_dt()
/linux-4.4.14/drivers/net/ethernet/agere/
H A Det131x.h900 * 30-24: non B2B ipg 1
902 * 22-16: non B2B ipg 2
904 * 7-0: B2B ipg
1050 u32 ipg; /* 0x5008 */ member in struct:mac_regs
H A Det131x.c810 u32 ipg; et1310_config_mac_regs1() local
821 ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */ et1310_config_mac_regs1()
822 ipg |= 0x50 << 8; /* ifg enforce 0x50 */ et1310_config_mac_regs1()
823 writel(ipg, &macregs->ipg); et1310_config_mac_regs1()
/linux-4.4.14/fs/ufs/
H A Dialloc.c257 UFSD("start = %u, bit = %u, ipg = %u\n", start, bit, uspi->s_ipg); ufs_new_inode()
H A Dsuper.c204 pr_debug(" ipg: %u\n", fs32_to_cpu(sb, usb1->fs_ipg)); ufs_print_super_stuff()
/linux-4.4.14/drivers/staging/lustre/lnet/klnds/o2iblnd/
H A Do2iblnd.c1162 int ipg; kiblnd_map_rx_descs() local
1165 for (pg_off = ipg = i = 0; i < IBLND_RX_MSGS(conn->ibc_version); i++) { kiblnd_map_rx_descs()
1166 pg = conn->ibc_rx_pages->ibp_pages[ipg]; kiblnd_map_rx_descs()
1189 ipg++; kiblnd_map_rx_descs()
1190 LASSERT(ipg <= IBLND_RX_MSG_PAGES(conn->ibc_version)); kiblnd_map_rx_descs()
/linux-4.4.14/sound/soc/fsl/
H A Dfsl_ssi.c1285 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg"); fsl_ssi_imx_probe()
1430 ret = of_property_match_string(np, "clock-names", "ipg"); fsl_ssi_probe()
1438 "ipg", iomem, &fsl_ssi_regconfig); fsl_ssi_probe()
H A Dfsl_asrc.c856 asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); fsl_asrc_probe()
858 dev_err(&pdev->dev, "failed to get ipg clock\n"); fsl_asrc_probe()
/linux-4.4.14/drivers/tty/serial/
H A Dimx.c1765 /* For setting the registers, we only need to enable the ipg clock. */ imx_console_setup()
1951 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); serial_imx_probe()
1954 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); serial_imx_probe()
1967 /* For register access, we only need to enable the ipg clock. */ serial_imx_probe()
H A Dmpc52xx_uart.c590 clk = clk_get_sys(np->name, "ipg"); mpc512x_psc_fifoc_init()
685 clk = devm_clk_get(port->dev, "ipg"); mpc512x_psc_alloc_clock()
H A Dfsl_lpuart.c1840 sport->clk = devm_clk_get(&pdev->dev, "ipg"); lpuart_probe()
/linux-4.4.14/drivers/spi/
H A Dspi-mpc512x-psc.c550 clk = devm_clk_get(dev, "ipg"); mpc512x_psc_spi_do_probe()
H A Dspi-imx.c1171 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); spi_imx_probe()
/linux-4.4.14/drivers/net/can/mscan/
H A Dmpc5xxx_can.c241 clk_ipg = devm_clk_get(&ofdev->dev, "ipg"); mpc512x_can_get_clock()
/linux-4.4.14/drivers/net/can/
H A Dflexcan.c1174 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); flexcan_probe()
1176 dev_err(&pdev->dev, "no ipg clock defined\n"); flexcan_probe()
/linux-4.4.14/drivers/crypto/
H A Dsahara.c1442 dev->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); sahara_probe()
1444 dev_err(&pdev->dev, "Could not get ipg clock\n"); sahara_probe()
/linux-4.4.14/drivers/mtd/nand/
H A Dmpc5121_nfc.c732 clk = devm_clk_get(dev, "ipg"); mpc5121_nfc_probe()
/linux-4.4.14/drivers/iio/adc/
H A Dvf610_adc.c224 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock, vf610_adc_calculate_rates()
/linux-4.4.14/drivers/media/platform/
H A Dmx2_emmaprp.c907 pcdev->clk_emma_ipg = devm_clk_get(&pdev->dev, "ipg"); emmaprp_probe()
H A Dfsl-viu.c1504 clk = devm_clk_get(&op->dev, "ipg"); viu_of_probe()
/linux-4.4.14/drivers/video/fbdev/
H A Dimxfb.c899 fbi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); imxfb_probe()
/linux-4.4.14/drivers/mmc/host/
H A Dmxcmmc.c1092 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); mxcmci_probe()
H A Dsdhci-esdhc-imx.c1116 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); sdhci_esdhc_imx_probe()
/linux-4.4.14/drivers/media/platform/soc_camera/
H A Dmx2_camera.c1473 pcdev->clk_emma_ipg = devm_clk_get(pcdev->dev, "emma-ipg"); mx27_camera_emma_init()
/linux-4.4.14/drivers/dma/
H A Dimx-dma.c1078 imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg"); imxdma_probe()
H A Dimx-sdma.c1702 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); sdma_probe()
/linux-4.4.14/drivers/net/ethernet/broadcom/bnxt/
H A Dbnxt_hsi.h1576 u8 ipg; member in struct:hwrm_port_mac_cfg_input
1595 u8 ipg; member in struct:hwrm_port_mac_cfg_output
/linux-4.4.14/drivers/net/ethernet/dlink/
H A Ddl2k.c258 /* PHY magic taken from ipg driver, undocumented registers */ rio_probe1()
/linux-4.4.14/fs/ext2/
H A Dsuper.c655 "bpg=%lu, ipg=%lu, mo=%04lx]", ext2_setup_super()
/linux-4.4.14/drivers/net/ethernet/freescale/
H A Dfec_main.c3401 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); fec_probe()
/linux-4.4.14/net/sctp/
H A Dsocket.c6133 * a fastreuse flag (FIXME: NPI ipg).
6270 * sockets FIXME: Blurry, NPI (ipg). sctp_get_port_local()
/linux-4.4.14/fs/ext4/
H A Dsuper.c1953 "bpg=%lu, ipg=%lu, mo=%04x, mo2=%04x]\n", ext4_setup_super()
/linux-4.4.14/include/linux/mlx5/
H A Dmlx5_ifc.h6381 u8 ipg[0x4]; member in struct:mlx5_ifc_pipg_reg_bits

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