51 	dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg,  enumerator
66 	&clk[ipg],
93 	clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);  in _mx31_clocks_init()
167 	clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");  in mx31_clocks_init()
183 	clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");  in mx31_clocks_init()
186 	clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");  in mx31_clocks_init()
189 	clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");  in mx31_clocks_init()
192 	clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");  in mx31_clocks_init()
196 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");  in mx31_clocks_init()
198 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");  in mx31_clocks_init()
200 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");  in mx31_clocks_init()
202 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");  in mx31_clocks_init()
204 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");  in mx31_clocks_init()