Searched refs:Reset (Results 1 - 200 of 2379) sorted by relevance

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/linux-4.4.14/arch/unicore32/include/mach/
H A D	regs-resetc.h	2 * PKUnity Reset Controller (RC) Registers 5 * Software Reset Register 9 * Reset Status Register 14 * Software Reset Bit 19 * Hardware Reset 23 * Software Reset 27 * Watchdog Reset 31 * Sleep Mode Reset
H A D	regs-pm.h	61 * PM Software Reset Reg PM_SWRESET
H A D	regs-sdc.h	9 * Software Reset Reg SDC_SRR
/linux-4.4.14/arch/arm/mach-sa1100/include/mach/
H A D	reset.h	6 #define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */ 7 #define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */ 9 #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */
H A D	assabet.h	41 #define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */ 42 #define ASSABET_BCR_NGFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */
/linux-4.4.14/drivers/net/ethernet/intel/i40e/
H A D	i40e_register.h	30 #define I40E_GL_ARQBAH 0x000801C0 /* Reset: EMPR */ 33 #define I40E_GL_ARQBAL 0x000800C0 /* Reset: EMPR */ 36 #define I40E_GL_ARQH 0x000803C0 /* Reset: EMPR */ 39 #define I40E_GL_ARQT 0x000804C0 /* Reset: EMPR */ 42 #define I40E_GL_ATQBAH 0x00080140 /* Reset: EMPR */ 45 #define I40E_GL_ATQBAL 0x00080040 /* Reset: EMPR */ 48 #define I40E_GL_ATQH 0x00080340 /* Reset: EMPR */ 51 #define I40E_GL_ATQLEN 0x00080240 /* Reset: EMPR */ 62 #define I40E_GL_ATQT 0x00080440 /* Reset: EMPR */ 65 #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */ 68 #define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */ 71 #define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */ 74 #define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */ 85 #define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */ 88 #define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */ 91 #define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */ 94 #define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */ 97 #define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */ 108 #define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */ 111 #define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 115 #define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 119 #define I40E_VF_ARQH(_VF) (0x00082400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 123 #define I40E_VF_ARQLEN(_VF) (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 135 #define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 139 #define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 143 #define I40E_VF_ATQBAL(_VF) (0x00080800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 147 #define I40E_VF_ATQH(_VF) (0x00082000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 151 #define I40E_VF_ATQLEN(_VF) (0x00081800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 163 #define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 167 #define I40E_PRT_L2TAGSEN 0x001C0B20 /* Reset: CORER */ 170 #define I40E_PFCM_LAN_ERRDATA 0x0010C080 /* Reset: PFR */ 177 #define I40E_PFCM_LAN_ERRINFO 0x0010C000 /* Reset: PFR */ 188 #define I40E_PFCM_LANCTXCTL 0x0010C300 /* Reset: CORER */ 197 #define I40E_PFCM_LANCTXDATA(_i) (0x0010C100 + ((_i) * 128)) /* _i=0...3 */ /* Reset: CORER */ 201 #define I40E_PFCM_LANCTXSTAT 0x0010C380 /* Reset: CORER */ 206 #define I40E_VFCM_PE_ERRDATA1(_VF) (0x00138800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 214 #define I40E_VFCM_PE_ERRINFO1(_VF) (0x00138400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 226 #define I40E_GLDCB_GENC 0x00083044 /* Reset: CORER */ 229 #define I40E_GLDCB_RUPTI 0x00122618 /* Reset: CORER */ 232 #define I40E_PRTDCB_FCCFG 0x001E4640 /* Reset: GLOBR */ 235 #define I40E_PRTDCB_FCRTV 0x001E4600 /* Reset: GLOBR */ 238 #define I40E_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: GLOBR */ 244 #define I40E_PRTDCB_GENC 0x00083000 /* Reset: CORER */ 255 #define I40E_PRTDCB_GENS 0x00083020 /* Reset: CORER */ 258 #define I40E_PRTDCB_MFLCN 0x001E2400 /* Reset: GLOBR */ 269 #define I40E_PRTDCB_RETSC 0x001223E0 /* Reset: CORER */ 278 #define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 286 #define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */ 293 #define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */ 296 #define I40E_PRTDCB_RUP2TC 0x001C09A0 /* Reset: CORER */ 313 #define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 317 #define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */ 320 #define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 324 #define I40E_PRTDCB_TCPMC 0x000A21A0 /* Reset: CORER */ 331 #define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 335 #define I40E_PRTDCB_TDPMC 0x000A0180 /* Reset: CORER */ 340 #define I40E_PRTDCB_TETSC_TCB 0x000AE060 /* Reset: CORER */ 345 #define I40E_PRTDCB_TETSC_TPB 0x00098060 /* Reset: CORER */ 350 #define I40E_PRTDCB_TFCS 0x001E4560 /* Reset: GLOBR */ 369 #define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */ 373 #define I40E_GLFCOE_RCTL 0x00269B94 /* Reset: CORER */ 382 #define I40E_GL_FWSTS 0x00083048 /* Reset: POR */ 389 #define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */ 402 #define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */ 430 #define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */ 437 #define I40E_GLGEN_GPIO_STAT 0x0008817C /* Reset: POR */ 440 #define I40E_GLGEN_GPIO_TRANSIT 0x00088180 /* Reset: POR */ 443 #define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 459 #define I40E_GLGEN_I2CPARAMS(_i) (0x000881AC + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 483 #define I40E_GLGEN_LED_CTL 0x00088178 /* Reset: POR */ 486 #define I40E_GLGEN_MDIO_CTRL(_i) (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 496 #define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 514 #define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 530 #define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 536 #define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */ 541 #define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */ 554 #define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */ 559 #define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */ 566 #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */ 579 #define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */ 583 #define I40E_GLVFGEN_TIMER 0x000881BC /* Reset: CORER */ 586 #define I40E_PFGEN_CTRL 0x00092400 /* Reset: PFR */ 589 #define I40E_PFGEN_DRUN 0x00092500 /* Reset: CORER */ 592 #define I40E_PFGEN_PORTNUM 0x001C0480 /* Reset: CORER */ 595 #define I40E_PFGEN_STATE 0x00088000 /* Reset: CORER */ 604 #define I40E_PRTGEN_CNF 0x000B8120 /* Reset: POR */ 611 #define I40E_PRTGEN_CNF2 0x000B8160 /* Reset: POR */ 614 #define I40E_PRTGEN_STATUS 0x000B8100 /* Reset: POR */ 619 #define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 623 #define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 627 #define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 631 #define I40E_VSIGEN_RSTAT(_VSI) (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */ 635 #define I40E_VSIGEN_RTRIG(_VSI) (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */ 639 #define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 643 #define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 647 #define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 /* Reset: CORER */ 650 #define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 654 #define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 658 #define I40E_GLHMC_FCOEFMAX 0x000C20D0 /* Reset: CORER */ 661 #define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 /* Reset: CORER */ 664 #define I40E_GLHMC_FCOEMAX 0x000C2014 /* Reset: CORER */ 667 #define I40E_GLHMC_FSIAVBASE(_i) (0x000C5600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 671 #define I40E_GLHMC_FSIAVCNT(_i) (0x000C5700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 677 #define I40E_GLHMC_FSIAVMAX 0x000C2068 /* Reset: CORER */ 680 #define I40E_GLHMC_FSIAVOBJSZ 0x000C2064 /* Reset: CORER */ 683 #define I40E_GLHMC_FSIMCBASE(_i) (0x000C6000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 687 #define I40E_GLHMC_FSIMCCNT(_i) (0x000C6100 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 691 #define I40E_GLHMC_FSIMCMAX 0x000C2060 /* Reset: CORER */ 694 #define I40E_GLHMC_FSIMCOBJSZ 0x000C205c /* Reset: CORER */ 697 #define I40E_GLHMC_LANQMAX 0x000C2008 /* Reset: CORER */ 700 #define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 704 #define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 708 #define I40E_GLHMC_LANRXOBJSZ 0x000C200c /* Reset: CORER */ 711 #define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 717 #define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 721 #define I40E_GLHMC_LANTXOBJSZ 0x000C2004 /* Reset: CORER */ 724 #define I40E_GLHMC_PFASSIGN(_i) (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 728 #define I40E_GLHMC_SDPART(_i) (0x000C0800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 734 #define I40E_PFHMC_ERRORDATA 0x000C0500 /* Reset: PFR */ 737 #define I40E_PFHMC_ERRORINFO 0x000C0400 /* Reset: PFR */ 748 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */ 753 #define I40E_PFHMC_SDCMD 0x000C0000 /* Reset: PFR */ 758 #define I40E_PFHMC_SDDATAHIGH 0x000C0200 /* Reset: PFR */ 761 #define I40E_PFHMC_SDDATALOW 0x000C0100 /* Reset: PFR */ 770 #define I40E_GL_GP_FUSE(_i) (0x0009400C + ((_i) * 4)) /* _i=0...28 */ /* Reset: POR */ 774 #define I40E_GL_UFUSE 0x00094008 /* Reset: POR */ 783 #define I40E_EMPINT_GPIO_ENA 0x00088188 /* Reset: POR */ 844 #define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 /* Reset: CORER */ 849 #define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */ 860 #define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 876 #define I40E_GLINT_CTL 0x0003F800 /* Reset: CORER */ 883 #define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */ 900 #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 918 #define I40E_PFINT_GPIO_ENA 0x00088080 /* Reset: CORER */ 979 #define I40E_PFINT_ICR0 0x00038780 /* Reset: CORER */ 1024 #define I40E_PFINT_ICR0_ENA 0x00038800 /* Reset: CORER */ 1051 #define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */ 1055 #define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */ 1059 #define I40E_PFINT_LNKLST0 0x00038500 /* Reset: PFR */ 1064 #define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 1070 #define I40E_PFINT_RATE0 0x00038580 /* Reset: PFR */ 1075 #define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 1081 #define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */ 1084 #define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 1100 #define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 1116 #define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 1134 #define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 1152 #define I40E_VFINT_ICR0(_VF) (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 1170 #define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 1178 #define I40E_VFINT_ITR0(_i, _VF) (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ /* Reset: VFR */ 1182 #define I40E_VFINT_ITRN(_i, _INTVF) (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */ /* Reset: VFR */ 1186 #define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 1190 #define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 1202 #define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 1218 #define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 1224 #define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 1230 #define I40E_VPINT_RATE0(_VF) (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 1236 #define I40E_VPINT_RATEN(_INTVF) (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 1242 #define I40E_GL_RDPU_CNTRL 0x00051060 /* Reset: CORER */ 1247 #define I40E_GLLAN_RCTL_0 0x0012A500 /* Reset: CORER */ 1250 #define I40E_GLLAN_TSOMSK_F 0x000442D8 /* Reset: CORER */ 1253 #define I40E_GLLAN_TSOMSK_L 0x000442E0 /* Reset: CORER */ 1256 #define I40E_GLLAN_TSOMSK_M 0x000442DC /* Reset: CORER */ 1259 #define I40E_GLLAN_TXPRE_QDIS(_i) (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */ 1269 #define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */ 1276 #define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 1284 #define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 1288 #define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 1296 #define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 1304 #define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 1310 #define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 1314 #define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 1318 #define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */ 1322 #define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */ 1328 #define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */ 1334 #define I40E_PRTGL_SAH 0x001E2140 /* Reset: GLOBR */ 1339 #define I40E_PRTGL_SAL 0x001E2120 /* Reset: GLOBR */ 1342 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E30E0 /* Reset: GLOBR */ 1345 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260 /* Reset: GLOBR */ 1348 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0 /* Reset: GLOBR */ 1351 #define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E3360 /* Reset: GLOBR */ 1354 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3110 /* Reset: GLOBR */ 1357 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3120 /* Reset: GLOBR */ 1360 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0 /* Reset: GLOBR */ 1363 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3140 /* Reset: GLOBR */ 1366 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E3150 /* Reset: GLOBR */ 1369 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0 /* Reset: GLOBR */ 1372 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E3370 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */ 1376 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */ 1380 #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E34B0 /* Reset: GLOBR */ 1383 #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E34C0 /* Reset: GLOBR */ 1386 #define I40E_PRTMAC_PCS_XAUI_SWAP_A 0x0008C480 /* Reset: GLOBR */ 1403 #define I40E_PRTMAC_PCS_XAUI_SWAP_B 0x0008C484 /* Reset: GLOBR */ 1420 #define I40E_GL_FWRESETCNT 0x00083100 /* Reset: POR */ 1423 #define I40E_GL_MNG_FWSM 0x000B6134 /* Reset: POR */ 1444 #define I40E_GL_MNG_HWARB_CTRL 0x000B6130 /* Reset: POR */ 1447 #define I40E_PRT_MNG_FTFT_DATA(_i) (0x000852A0 + ((_i) * 32)) /* _i=0...31 */ /* Reset: POR */ 1451 #define I40E_PRT_MNG_FTFT_LENGTH 0x00085260 /* Reset: POR */ 1454 #define I40E_PRT_MNG_FTFT_MASK(_i) (0x00085160 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */ 1458 #define I40E_PRT_MNG_MANC 0x00256A20 /* Reset: POR */ 1475 #define I40E_PRT_MNG_MAVTV(_i) (0x00255900 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */ 1479 #define I40E_PRT_MNG_MDEF(_i) (0x00255D00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */ 1507 #define I40E_PRT_MNG_MDEF_EXT(_i) (0x00255F00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */ 1531 #define I40E_PRT_MNG_MDEFVSI(_i) (0x00256580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 1537 #define I40E_PRT_MNG_METF(_i) (0x00256780 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 1543 #define I40E_PRT_MNG_MFUTP(_i) (0x00254E00 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */ 1553 #define I40E_PRT_MNG_MIPAF4(_i) (0x00256280 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 1557 #define I40E_PRT_MNG_MIPAF6(_i) (0x00254200 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */ 1561 #define I40E_PRT_MNG_MMAH(_i) (0x00256380 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 1565 #define I40E_PRT_MNG_MMAL(_i) (0x00256480 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 1569 #define I40E_PRT_MNG_MNGONLY 0x00256A60 /* Reset: POR */ 1572 #define I40E_PRT_MNG_MSFM 0x00256AA0 /* Reset: POR */ 1589 #define I40E_MSIX_PBA(_i) (0x00001000 + ((_i) * 4)) /* _i=0...5 */ /* Reset: FLR */ 1593 #define I40E_MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */ 1599 #define I40E_MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */ 1603 #define I40E_MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */ 1607 #define I40E_MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */ 1611 #define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */ 1615 #define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 1621 #define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 1625 #define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 1629 #define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 1633 #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 1654 #define I40E_GLNVM_FLASHID 0x000B6104 /* Reset: POR */ 1659 #define I40E_GLNVM_GENS 0x000B6100 /* Reset: POR */ 1670 #define I40E_GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset: POR */ 1674 #define I40E_GLNVM_SRCTL 0x000B6110 /* Reset: POR */ 1685 #define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */ 1690 #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 1711 #define I40E_GLPCI_BYTCTH 0x0009C484 /* Reset: PCIR */ 1714 #define I40E_GLPCI_BYTCTL 0x0009C488 /* Reset: PCIR */ 1717 #define I40E_GLPCI_CAPCTRL 0x000BE4A4 /* Reset: PCIR */ 1720 #define I40E_GLPCI_CAPSUP 0x000BE4A8 /* Reset: PCIR */ 1749 #define I40E_GLPCI_CNF 0x000BE4C0 /* Reset: POR */ 1754 #define I40E_GLPCI_CNF2 0x000BE494 /* Reset: PCIR */ 1763 #define I40E_GLPCI_DREVID 0x0009C480 /* Reset: PCIR */ 1766 #define I40E_GLPCI_GSCL_1 0x0009C48C /* Reset: PCIR */ 1799 #define I40E_GLPCI_GSCL_2 0x0009C490 /* Reset: PCIR */ 1808 #define I40E_GLPCI_GSCL_5_8(_i) (0x0009C494 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */ 1814 #define I40E_GLPCI_GSCN_0_3(_i) (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */ 1818 #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */ 1833 #define I40E_GLPCI_LINKCAP 0x000BE4AC /* Reset: PCIR */ 1840 #define I40E_GLPCI_PCIERR 0x000BE4FC /* Reset: PCIR */ 1843 #define I40E_GLPCI_PKTCT 0x0009C4BC /* Reset: PCIR */ 1846 #define I40E_GLPCI_PM_MUX_NPQ 0x0009C4F4 /* Reset: PCIR */ 1851 #define I40E_GLPCI_PM_MUX_PFB 0x0009C4F0 /* Reset: PCIR */ 1856 #define I40E_GLPCI_PMSUP 0x000BE4B0 /* Reset: PCIR */ 1871 #define I40E_GLPCI_PQ_MAX_USED_SPC 0x0009C4EC /* Reset: PCIR */ 1876 #define I40E_GLPCI_PWRDATA 0x000BE490 /* Reset: PCIR */ 1885 #define I40E_GLPCI_REVID 0x000BE4B4 /* Reset: PCIR */ 1888 #define I40E_GLPCI_SERH 0x000BE49C /* Reset: PCIR */ 1891 #define I40E_GLPCI_SERL 0x000BE498 /* Reset: PCIR */ 1894 #define I40E_GLPCI_SPARE_BITS_0 0x0009C4F8 /* Reset: PCIR */ 1897 #define I40E_GLPCI_SPARE_BITS_1 0x0009C4FC /* Reset: PCIR */ 1900 #define I40E_GLPCI_SUBVENID 0x000BE48C /* Reset: PCIR */ 1903 #define I40E_GLPCI_UPADD 0x000BE4F8 /* Reset: PCIR */ 1906 #define I40E_GLPCI_VENDORID 0x000BE518 /* Reset: PCIR */ 1909 #define I40E_GLPCI_VFSUP 0x000BE4B8 /* Reset: PCIR */ 1914 #define I40E_GLTPH_CTRL 0x000BE480 /* Reset: PCIR */ 1919 #define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */ 1926 #define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */ 1931 #define I40E_PF_PCI_CIAD 0x0009C100 /* Reset: FLR */ 1934 #define I40E_PFPCI_CLASS 0x000BE400 /* Reset: PCIR */ 1941 #define I40E_PFPCI_CNF 0x000BE000 /* Reset: PCIR */ 1950 #define I40E_PFPCI_DEVID 0x000BE080 /* Reset: PCIR */ 1955 #define I40E_PFPCI_FACTPS 0x0009C180 /* Reset: FLR */ 1960 #define I40E_PFPCI_FUNC 0x000BE200 /* Reset: POR */ 1967 #define I40E_PFPCI_FUNC2 0x000BE180 /* Reset: PCIR */ 1970 #define I40E_PFPCI_ICAUSE 0x0009C200 /* Reset: PFR */ 1973 #define I40E_PFPCI_IENA 0x0009C280 /* Reset: PFR */ 1976 #define I40E_PFPCI_PF_FLUSH_DONE 0x0009C800 /* Reset: PCIR */ 1979 #define I40E_PFPCI_PM 0x000BE300 /* Reset: POR */ 1982 #define I40E_PFPCI_STATUS1 0x000BE280 /* Reset: POR */ 1985 #define I40E_PFPCI_SUBSYSID 0x000BE100 /* Reset: PCIR */ 1990 #define I40E_PFPCI_VF_FLUSH_DONE 0x0000E400 /* Reset: PCIR */ 1993 #define I40E_PFPCI_VF_FLUSH_DONE1(_VF) (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: PCIR */ 1997 #define I40E_PFPCI_VM_FLUSH_DONE 0x0009C880 /* Reset: PCIR */ 2000 #define I40E_PFPCI_VMINDEX 0x0009C300 /* Reset: PCIR */ 2003 #define I40E_PFPCI_VMPEND 0x0009C380 /* Reset: PCIR */ 2006 #define I40E_PRTPM_EEE_STAT 0x001E4320 /* Reset: GLOBR */ 2013 #define I40E_PRTPM_EEEC 0x001E4380 /* Reset: GLOBR */ 2020 #define I40E_PRTPM_EEEFWD 0x001E4400 /* Reset: GLOBR */ 2023 #define I40E_PRTPM_EEER 0x001E4360 /* Reset: GLOBR */ 2028 #define I40E_PRTPM_EEETXC 0x001E43E0 /* Reset: GLOBR */ 2031 #define I40E_PRTPM_GC 0x000B8140 /* Reset: POR */ 2042 #define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */ 2045 #define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */ 2048 #define I40E_GLRPB_DPSS 0x000AC828 /* Reset: CORER */ 2051 #define I40E_GLRPB_GHW 0x000AC830 /* Reset: CORER */ 2054 #define I40E_GLRPB_GLW 0x000AC834 /* Reset: CORER */ 2057 #define I40E_GLRPB_PHW 0x000AC844 /* Reset: CORER */ 2060 #define I40E_GLRPB_PLW 0x000AC848 /* Reset: CORER */ 2063 #define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 2067 #define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 2071 #define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 2075 #define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 2079 #define I40E_PRTRPB_SHW 0x000AC580 /* Reset: CORER */ 2082 #define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 2086 #define I40E_PRTRPB_SLW 0x000AC6A0 /* Reset: CORER */ 2089 #define I40E_PRTRPB_SPS 0x000AC7C0 /* Reset: CORER */ 2092 #define I40E_GLQF_CTL 0x00269BA4 /* Reset: CORER */ 2117 #define I40E_GLQF_FDCNT_0 0x00269BAC /* Reset: CORER */ 2122 #define I40E_GLQF_HKEY(_i) (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ 2132 #define I40E_GLQF_HSYM(_i) (0x00269D00 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */ 2136 #define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */ 2140 #define I40E_GLQF_SWAP(_i, _j) (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */ 2154 #define I40E_PFQF_CTL_0 0x001C0AC0 /* Reset: CORER */ 2175 #define I40E_PFQF_CTL_1 0x00245D80 /* Reset: CORER */ 2178 #define I40E_PFQF_FDALLOC 0x00246280 /* Reset: CORER */ 2183 #define I40E_PFQF_FDSTAT 0x00246380 /* Reset: CORER */ 2188 #define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */ 2192 #define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ /* Reset: CORER */ 2202 #define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */ 2212 #define I40E_PRTQF_CTL_0 0x00256E60 /* Reset: CORER */ 2215 #define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 */ /* Reset: CORER */ 2219 #define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 2225 #define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */ 2233 #define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */ /* Reset: CORER */ 2237 #define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ /* Reset: CORER */ 2247 #define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */ 2257 #define I40E_VFQF_HREGION1(_i, _VF) (0x0022E000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...7, _VF=0...127 */ /* Reset: CORER */ 2291 #define I40E_VPQF_CTL(_VF) (0x001C0000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2301 #define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */ 2315 #define I40E_VSIQF_TCREGION(_i, _VSI) (0x00206000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...3, _VSI=0...383 */ /* Reset: PFR */ 2325 #define I40E_GL_FCOECRC(_i) (0x00314d80 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2329 #define I40E_GL_FCOEDDPC(_i) (0x00314480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2333 #define I40E_GL_FCOEDIFEC(_i) (0x00318480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2337 #define I40E_GL_FCOEDIFTCL(_i) (0x00354000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2341 #define I40E_GL_FCOEDIXEC(_i) (0x0034c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2345 #define I40E_GL_FCOEDIXVC(_i) (0x00350000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2349 #define I40E_GL_FCOEDWRCH(_i) (0x00320004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2353 #define I40E_GL_FCOEDWRCL(_i) (0x00320000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2357 #define I40E_GL_FCOEDWTCH(_i) (0x00348084 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2361 #define I40E_GL_FCOEDWTCL(_i) (0x00348080 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2365 #define I40E_GL_FCOELAST(_i) (0x00314000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2369 #define I40E_GL_FCOEPRC(_i) (0x00315200 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2373 #define I40E_GL_FCOEPTC(_i) (0x00344C00 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2377 #define I40E_GL_FCOERPDC(_i) (0x00324000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2381 #define I40E_GL_RXERR1_L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2385 #define I40E_GL_RXERR2_L(_i) (0x0031c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2389 #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2393 #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2397 #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2401 #define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2405 #define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2409 #define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2413 #define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2417 #define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2421 #define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2425 #define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2429 #define I40E_GLPRT_LDPC(_i) (0x00300620 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2433 #define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2437 #define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2441 #define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2445 #define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2449 #define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2453 #define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2457 #define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2461 #define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2465 #define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2469 #define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2473 #define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2477 #define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2481 #define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2485 #define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2489 #define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2493 #define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2497 #define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2501 #define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2505 #define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2509 #define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2513 #define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2517 #define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2521 #define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2525 #define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2529 #define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2533 #define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2537 #define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2541 #define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2545 #define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2549 #define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2553 #define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2557 #define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2561 #define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2565 #define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2569 #define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2573 #define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2577 #define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2581 #define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2585 #define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 2589 #define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 2593 #define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 2597 #define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 2601 #define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2605 #define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2609 #define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2613 #define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2617 #define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2621 #define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2625 #define I40E_GLPRT_RUPP(_i) (0x00300660 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2629 #define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 2633 #define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2637 #define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2641 #define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2645 #define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2649 #define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2653 #define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2657 #define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2661 #define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2665 #define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2669 #define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2673 #define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2677 #define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2681 #define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2685 #define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2689 #define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2693 #define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2697 #define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2701 #define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2705 #define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2709 #define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2713 #define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2717 #define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2721 #define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2725 #define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2729 #define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2733 #define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2737 #define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2741 #define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2745 #define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2749 #define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2753 #define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2757 #define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2761 #define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2765 #define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2769 #define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2773 #define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2777 #define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2781 #define I40E_GLV_TEPC(_VSI) (0x00344000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */ 2785 #define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2789 #define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2793 #define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2797 #define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2801 #define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2805 #define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2809 #define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2813 #define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2817 #define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2821 #define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2825 #define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2829 #define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2833 #define I40E_GLVEBVL_BPCH(_i) (0x00374804 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2837 #define I40E_GLVEBVL_BPCL(_i) (0x00374800 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2841 #define I40E_GLVEBVL_GORCH(_i) (0x00360004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2845 #define I40E_GLVEBVL_GORCL(_i) (0x00360000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2849 #define I40E_GLVEBVL_GOTCH(_i) (0x00330004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2853 #define I40E_GLVEBVL_GOTCL(_i) (0x00330000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2857 #define I40E_GLVEBVL_MPCH(_i) (0x00374404 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2861 #define I40E_GLVEBVL_MPCL(_i) (0x00374400 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2865 #define I40E_GLVEBVL_UPCH(_i) (0x00374004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2869 #define I40E_GLVEBVL_UPCL(_i) (0x00374000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2873 #define I40E_GL_MTG_FLU_MSK_H 0x00269F4C /* Reset: CORER */ 2876 #define I40E_GL_SWR_DEF_ACT(_i) (0x00270200 + ((_i) * 4)) /* _i=0...35 */ /* Reset: CORER */ 2880 #define I40E_GL_SWR_DEF_ACT_EN(_i) (0x0026CFB8 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 2884 #define I40E_PRTTSYN_ADJ 0x001E4280 /* Reset: GLOBR */ 2889 #define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2901 #define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2907 #define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2911 #define I40E_PRTTSYN_CTL0 0x001E4200 /* Reset: GLOBR */ 2926 #define I40E_PRTTSYN_CTL1 0x00085020 /* Reset: CORER */ 2941 #define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2945 #define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2949 #define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */ 2952 #define I40E_PRTTSYN_INC_L 0x001E4040 /* Reset: GLOBR */ 2955 #define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 2959 #define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 2963 #define I40E_PRTTSYN_STAT_0 0x001E4220 /* Reset: GLOBR */ 2974 #define I40E_PRTTSYN_STAT_1 0x00085140 /* Reset: CORER */ 2983 #define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2987 #define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2991 #define I40E_PRTTSYN_TIME_H 0x001E4120 /* Reset: GLOBR */ 2994 #define I40E_PRTTSYN_TIME_L 0x001E4100 /* Reset: GLOBR */ 2997 #define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */ 3000 #define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */ 3003 #define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */ 3012 #define I40E_GL_MDET_TX 0x000E6480 /* Reset: CORER */ 3023 #define I40E_PF_MDET_RX 0x0012A400 /* Reset: CORER */ 3026 #define I40E_PF_MDET_TX 0x000E6400 /* Reset: CORER */ 3029 #define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */ 3036 #define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 3040 #define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 3044 #define I40E_GLPM_WUMC 0x0006C800 /* Reset: POR */ 3055 #define I40E_PFPM_APM 0x000B8080 /* Reset: POR */ 3058 #define I40E_PFPM_FHFT_LENGTH(_i) (0x0006A000 + ((_i) * 128)) /* _i=0...7 */ /* Reset: POR */ 3062 #define I40E_PFPM_WUC 0x0006B200 /* Reset: POR */ 3065 #define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */ 3106 #define I40E_PFPM_WUS 0x0006B600 /* Reset: POR */ 3133 #define I40E_PRTPM_FHFHR 0x0006C000 /* Reset: POR */ 3138 #define I40E_PRTPM_SAH(_i) (0x001E44C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */ 3148 #define I40E_PRTPM_SAL(_i) (0x001E4440 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */ 3152 #define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */ 3155 #define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */ 3158 #define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */ 3161 #define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */ 3172 #define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ 3175 #define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ 3178 #define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ 3181 #define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */ 3184 #define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */ 3195 #define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ 3198 #define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ 3201 #define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ 3218 #define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */ 3236 #define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */ 3243 #define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */ 3260 #define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ 3264 #define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */ 3268 #define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */ 3271 #define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3275 #define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */ 3279 #define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */ 3282 #define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 3288 #define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 3292 #define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 3296 #define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 3300 #define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */ 3307 #define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */ 3318 #define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 3322 #define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ 3332 #define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3342 #define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */ 3377 #define I40E_MNGSB_FDCRC 0x000B7050 /* Reset: POR */ 3380 #define I40E_MNGSB_FDCS 0x000B7040 /* Reset: POR */ 3389 #define I40E_MNGSB_FDS 0x000B7048 /* Reset: POR */ 3395 #define I40E_GL_VF_CTRL_RX(_VF) (0x00083600 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 3399 #define I40E_GL_VF_CTRL_TX(_VF) (0x00083400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 3404 #define I40E_GLCM_LAN_CACHESIZE 0x0010C4D8 /* Reset: CORER */ 3411 #define I40E_GLCM_PE_CACHESIZE 0x00138FE4 /* Reset: CORER */ 3418 #define I40E_PFCM_PE_ERRDATA 0x00138D00 /* Reset: PFR */ 3425 #define I40E_PFCM_PE_ERRINFO 0x00138C80 /* Reset: PFR */ 3437 #define I40E_PRTDCB_TFMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 3443 #define I40E_GLFOC_CACHESIZE 0x000AA0DC /* Reset: CORER */ 3450 #define I40E_GLHMC_APBVTINUSEBASE(_i) (0x000C4a00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3454 #define I40E_GLHMC_CEQPART(_i) (0x001312C0 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3460 #define I40E_GLHMC_DBCQMAX 0x000C20F0 /* Reset: CORER */ 3463 #define I40E_GLHMC_DBCQPART(_i) (0x00131240 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3469 #define I40E_GLHMC_DBQPMAX 0x000C20EC /* Reset: CORER */ 3472 #define I40E_GLHMC_DBQPPART(_i) (0x00138D80 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3478 #define I40E_GLHMC_PEARPBASE(_i) (0x000C4800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3482 #define I40E_GLHMC_PEARPCNT(_i) (0x000C4900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3486 #define I40E_GLHMC_PEARPMAX 0x000C2038 /* Reset: CORER */ 3489 #define I40E_GLHMC_PEARPOBJSZ 0x000C2034 /* Reset: CORER */ 3492 #define I40E_GLHMC_PECQBASE(_i) (0x000C4200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3496 #define I40E_GLHMC_PECQCNT(_i) (0x000C4300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3500 #define I40E_GLHMC_PECQOBJSZ 0x000C2020 /* Reset: CORER */ 3503 #define I40E_GLHMC_PEHTCNT(_i) (0x000C4700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3507 #define I40E_GLHMC_PEHTEBASE(_i) (0x000C4600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3511 #define I40E_GLHMC_PEHTEOBJSZ 0x000C202c /* Reset: CORER */ 3514 #define I40E_GLHMC_PEHTMAX 0x000C2030 /* Reset: CORER */ 3517 #define I40E_GLHMC_PEMRBASE(_i) (0x000C4c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3521 #define I40E_GLHMC_PEMRCNT(_i) (0x000C4d00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3525 #define I40E_GLHMC_PEMRMAX 0x000C2040 /* Reset: CORER */ 3528 #define I40E_GLHMC_PEMROBJSZ 0x000C203c /* Reset: CORER */ 3531 #define I40E_GLHMC_PEPBLBASE(_i) (0x000C5800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3535 #define I40E_GLHMC_PEPBLCNT(_i) (0x000C5900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3539 #define I40E_GLHMC_PEPBLMAX 0x000C206c /* Reset: CORER */ 3542 #define I40E_GLHMC_PEPFFIRSTSD 0x000C20E4 /* Reset: CORER */ 3545 #define I40E_GLHMC_PEQ1BASE(_i) (0x000C5200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3549 #define I40E_GLHMC_PEQ1CNT(_i) (0x000C5300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3553 #define I40E_GLHMC_PEQ1FLBASE(_i) (0x000C5400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3557 #define I40E_GLHMC_PEQ1FLMAX 0x000C2058 /* Reset: CORER */ 3560 #define I40E_GLHMC_PEQ1MAX 0x000C2054 /* Reset: CORER */ 3563 #define I40E_GLHMC_PEQ1OBJSZ 0x000C2050 /* Reset: CORER */ 3566 #define I40E_GLHMC_PEQPBASE(_i) (0x000C4000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3570 #define I40E_GLHMC_PEQPCNT(_i) (0x000C4100 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3574 #define I40E_GLHMC_PEQPOBJSZ 0x000C201c /* Reset: CORER */ 3577 #define I40E_GLHMC_PESRQBASE(_i) (0x000C4400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3581 #define I40E_GLHMC_PESRQCNT(_i) (0x000C4500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3585 #define I40E_GLHMC_PESRQMAX 0x000C2028 /* Reset: CORER */ 3588 #define I40E_GLHMC_PESRQOBJSZ 0x000C2024 /* Reset: CORER */ 3591 #define I40E_GLHMC_PETIMERBASE(_i) (0x000C5A00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3595 #define I40E_GLHMC_PETIMERCNT(_i) (0x000C5B00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3599 #define I40E_GLHMC_PETIMERMAX 0x000C2084 /* Reset: CORER */ 3602 #define I40E_GLHMC_PETIMEROBJSZ 0x000C2080 /* Reset: CORER */ 3605 #define I40E_GLHMC_PEXFBASE(_i) (0x000C4e00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3609 #define I40E_GLHMC_PEXFCNT(_i) (0x000C4f00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3613 #define I40E_GLHMC_PEXFFLBASE(_i) (0x000C5000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3617 #define I40E_GLHMC_PEXFFLMAX 0x000C204c /* Reset: CORER */ 3620 #define I40E_GLHMC_PEXFMAX 0x000C2048 /* Reset: CORER */ 3623 #define I40E_GLHMC_PEXFOBJSZ 0x000C2044 /* Reset: CORER */ 3626 #define I40E_GLHMC_PFPESDPART(_i) (0x000C0880 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3632 #define I40E_GLHMC_VFAPBVTINUSEBASE(_i) (0x000Cca00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3636 #define I40E_GLHMC_VFCEQPART(_i) (0x00132240 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3642 #define I40E_GLHMC_VFDBCQPART(_i) (0x00132140 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3648 #define I40E_GLHMC_VFDBQPPART(_i) (0x00138E00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3654 #define I40E_GLHMC_VFFSIAVBASE(_i) (0x000Cd600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3658 #define I40E_GLHMC_VFFSIAVCNT(_i) (0x000Cd700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3662 #define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3670 #define I40E_GLHMC_VFPEARPBASE(_i) (0x000Cc800 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3674 #define I40E_GLHMC_VFPEARPCNT(_i) (0x000Cc900 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3678 #define I40E_GLHMC_VFPECQBASE(_i) (0x000Cc200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3682 #define I40E_GLHMC_VFPECQCNT(_i) (0x000Cc300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3686 #define I40E_GLHMC_VFPEHTCNT(_i) (0x000Cc700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3690 #define I40E_GLHMC_VFPEHTEBASE(_i) (0x000Cc600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3694 #define I40E_GLHMC_VFPEMRBASE(_i) (0x000Ccc00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3698 #define I40E_GLHMC_VFPEMRCNT(_i) (0x000Ccd00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3702 #define I40E_GLHMC_VFPEPBLBASE(_i) (0x000Cd800 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3706 #define I40E_GLHMC_VFPEPBLCNT(_i) (0x000Cd900 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3710 #define I40E_GLHMC_VFPEQ1BASE(_i) (0x000Cd200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3714 #define I40E_GLHMC_VFPEQ1CNT(_i) (0x000Cd300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3718 #define I40E_GLHMC_VFPEQ1FLBASE(_i) (0x000Cd400 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3722 #define I40E_GLHMC_VFPEQPBASE(_i) (0x000Cc000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3726 #define I40E_GLHMC_VFPEQPCNT(_i) (0x000Cc100 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3730 #define I40E_GLHMC_VFPESRQBASE(_i) (0x000Cc400 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3734 #define I40E_GLHMC_VFPESRQCNT(_i) (0x000Cc500 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3738 #define I40E_GLHMC_VFPETIMERBASE(_i) (0x000CDA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3742 #define I40E_GLHMC_VFPETIMERCNT(_i) (0x000CDB00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3746 #define I40E_GLHMC_VFPEXFBASE(_i) (0x000Cce00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3750 #define I40E_GLHMC_VFPEXFCNT(_i) (0x000Ccf00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3754 #define I40E_GLHMC_VFPEXFFLBASE(_i) (0x000Cd000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3758 #define I40E_GLHMC_VFSDPART(_i) (0x000C8800 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3764 #define I40E_GLPBLOC_CACHESIZE 0x000A80BC /* Reset: CORER */ 3771 #define I40E_GLPDOC_CACHESIZE 0x000D0088 /* Reset: CORER */ 3778 #define I40E_GLPEOC_CACHESIZE 0x000A60E8 /* Reset: CORER */ 3789 #define I40E_GL_PPRS_SPARE 0x000856E0 /* Reset: CORER */ 3792 #define I40E_GL_TLAN_SPARE 0x000E64E0 /* Reset: CORER */ 3795 #define I40E_GL_TUPM_SPARE 0x000a2230 /* Reset: CORER */ 3798 #define I40E_GLGEN_CAR_DEBUG 0x000B81C0 /* Reset: POR */ 3829 #define I40E_GLGEN_MISC_SPARE 0x000880E0 /* Reset: POR */ 3832 #define I40E_GL_UFUSE_SOC 0x000BE550 /* Reset: POR */ 3847 #define I40E_VPLAN_QBASE(_VF) (0x00074800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 3855 #define I40E_PRTMAC_LINK_DOWN_COUNTER 0x001E2440 /* Reset: GLOBR */ 3858 #define I40E_GLNVM_AL_REQ 0x000B6164 /* Reset: POR */ 3871 #define I40E_GLNVM_ALTIMERS 0x000B6140 /* Reset: POR */ 3876 #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 3880 #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 3897 #define I40E_GLNVM_ULT 0x000B6154 /* Reset: POR */ 3920 #define I40E_MEM_INIT_DONE_STAT 0x000B615C /* Reset: POR */ 3955 #define I40E_MNGSB_DADD 0x000B7030 /* Reset: POR */ 3958 #define I40E_MNGSB_DCNT 0x000B7034 /* Reset: POR */ 3961 #define I40E_MNGSB_MSGCTL 0x000B7020 /* Reset: POR */ 3974 #define I40E_MNGSB_RDATA 0x000B7300 /* Reset: POR */ 3977 #define I40E_MNGSB_RHDR0 0x000B72FC /* Reset: POR */ 3990 #define I40E_MNGSB_RSPCTL 0x000B7024 /* Reset: POR */ 3999 #define I40E_MNGSB_WDATA 0x000B7100 /* Reset: POR */ 4002 #define I40E_MNGSB_WHDR0 0x000B70F4 /* Reset: POR */ 4011 #define I40E_MNGSB_WHDR1 0x000B70F8 /* Reset: POR */ 4014 #define I40E_MNGSB_WHDR2 0x000B70FC /* Reset: POR */ 4021 #define I40E_GLPCI_CUR_CLNT_COMMON 0x0009CA18 /* Reset: PCIR */ 4026 #define I40E_GLPCI_CUR_CLNT_PIPEMON 0x0009CA20 /* Reset: PCIR */ 4029 #define I40E_GLPCI_CUR_MNG_ALWD 0x0009c514 /* Reset: PCIR */ 4034 #define I40E_GLPCI_CUR_MNG_RSVD 0x0009c594 /* Reset: PCIR */ 4039 #define I40E_GLPCI_CUR_PMAT_ALWD 0x0009c510 /* Reset: PCIR */ 4044 #define I40E_GLPCI_CUR_PMAT_RSVD 0x0009c590 /* Reset: PCIR */ 4049 #define I40E_GLPCI_CUR_RLAN_ALWD 0x0009c500 /* Reset: PCIR */ 4054 #define I40E_GLPCI_CUR_RLAN_RSVD 0x0009c580 /* Reset: PCIR */ 4059 #define I40E_GLPCI_CUR_RXPE_ALWD 0x0009c508 /* Reset: PCIR */ 4064 #define I40E_GLPCI_CUR_RXPE_RSVD 0x0009c588 /* Reset: PCIR */ 4069 #define I40E_GLPCI_CUR_TDPU_ALWD 0x0009c518 /* Reset: PCIR */ 4074 #define I40E_GLPCI_CUR_TDPU_RSVD 0x0009c598 /* Reset: PCIR */ 4079 #define I40E_GLPCI_CUR_TLAN_ALWD 0x0009c504 /* Reset: PCIR */ 4084 #define I40E_GLPCI_CUR_TLAN_RSVD 0x0009c584 /* Reset: PCIR */ 4089 #define I40E_GLPCI_CUR_TXPE_ALWD 0x0009c50C /* Reset: PCIR */ 4094 #define I40E_GLPCI_CUR_TXPE_RSVD 0x0009c58c /* Reset: PCIR */ 4099 #define I40E_GLPCI_CUR_WATMK_CLNT_COMMON 0x0009CA28 /* Reset: PCIR */ 4109 #define I40E_GLPCI_NPQ_CFG 0x0009CA00 /* Reset: PCIR */ 4120 #define I40E_GLPCI_WATMK_CLNT_PIPEMON 0x0009CA30 /* Reset: PCIR */ 4123 #define I40E_GLPCI_WATMK_MNG_ALWD 0x0009CB14 /* Reset: PCIR */ 4128 #define I40E_GLPCI_WATMK_PMAT_ALWD 0x0009CB10 /* Reset: PCIR */ 4133 #define I40E_GLPCI_WATMK_RLAN_ALWD 0x0009CB00 /* Reset: PCIR */ 4138 #define I40E_GLPCI_WATMK_RXPE_ALWD 0x0009CB08 /* Reset: PCIR */ 4143 #define I40E_GLPCI_WATMK_TLAN_ALWD 0x0009CB04 /* Reset: PCIR */ 4148 #define I40E_GLPCI_WATMK_TPDU_ALWD 0x0009CB18 /* Reset: PCIR */ 4153 #define I40E_GLPCI_WATMK_TXPE_ALWD 0x0009CB0c /* Reset: PCIR */ 4158 #define I40E_GLPE_CPUSTATUS0 0x0000D040 /* Reset: PE_CORER */ 4161 #define I40E_GLPE_CPUSTATUS1 0x0000D044 /* Reset: PE_CORER */ 4164 #define I40E_GLPE_CPUSTATUS2 0x0000D048 /* Reset: PE_CORER */ 4167 #define I40E_GLPE_CPUTRIG0 0x0000D060 /* Reset: PE_CORER */ 4174 #define I40E_GLPE_DUAL40_RUPM 0x0000DA04 /* Reset: PE_CORER */ 4177 #define I40E_GLPE_PFAEQEDROPCNT(_i) (0x00131440 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 4181 #define I40E_GLPE_PFCEQEDROPCNT(_i) (0x001313C0 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 4185 #define I40E_GLPE_PFCQEDROPCNT(_i) (0x00131340 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 4189 #define I40E_GLPE_RUPM_CQPPOOL 0x0000DACC /* Reset: PE_CORER */ 4192 #define I40E_GLPE_RUPM_FLRPOOL 0x0000DAC4 /* Reset: PE_CORER */ 4195 #define I40E_GLPE_RUPM_GCTL 0x0000DA00 /* Reset: PE_CORER */ 4210 #define I40E_GLPE_RUPM_PTXPOOL 0x0000DAC8 /* Reset: PE_CORER */ 4213 #define I40E_GLPE_RUPM_PUSHPOOL 0x0000DAC0 /* Reset: PE_CORER */ 4216 #define I40E_GLPE_RUPM_TXHOST_EN 0x0000DA08 /* Reset: PE_CORER */ 4219 #define I40E_GLPE_VFAEQEDROPCNT(_i) (0x00132540 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 4223 #define I40E_GLPE_VFCEQEDROPCNT(_i) (0x00132440 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 4227 #define I40E_GLPE_VFCQEDROPCNT(_i) (0x00132340 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 4231 #define I40E_GLPE_VFFLMOBJCTRL(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4237 #define I40E_GLPE_VFFLMQ1ALLOCERR(_i) (0x0000C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4241 #define I40E_GLPE_VFFLMXMITALLOCERR(_i) (0x0000C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4245 #define I40E_GLPE_VFUDACTRL(_i) (0x0000C000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4257 #define I40E_GLPE_VFUDAUCFBQPN(_i) (0x0000C100 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4263 #define I40E_PFPE_AEQALLOC 0x00131180 /* Reset: PFR */ 4266 #define I40E_PFPE_CCQPHIGH 0x00008200 /* Reset: PFR */ 4269 #define I40E_PFPE_CCQPLOW 0x00008180 /* Reset: PFR */ 4272 #define I40E_PFPE_CCQPSTATUS 0x00008100 /* Reset: PFR */ 4281 #define I40E_PFPE_CQACK 0x00131100 /* Reset: PFR */ 4284 #define I40E_PFPE_CQARM 0x00131080 /* Reset: PFR */ 4287 #define I40E_PFPE_CQPDB 0x00008000 /* Reset: PFR */ 4290 #define I40E_PFPE_CQPERRCODES 0x00008880 /* Reset: PFR */ 4295 #define I40E_PFPE_CQPTAIL 0x00008080 /* Reset: PFR */ 4300 #define I40E_PFPE_FLMQ1ALLOCERR 0x00008980 /* Reset: PFR */ 4303 #define I40E_PFPE_FLMXMITALLOCERR 0x00008900 /* Reset: PFR */ 4306 #define I40E_PFPE_IPCONFIG0 0x00008280 /* Reset: PFR */ 4311 #define I40E_PFPE_MRTEIDXMASK 0x00008600 /* Reset: PFR */ 4314 #define I40E_PFPE_RCVUNEXPECTEDERROR 0x00008680 /* Reset: PFR */ 4317 #define I40E_PFPE_TCPNOWTIMER 0x00008580 /* Reset: PFR */ 4320 #define I40E_PFPE_UDACTRL 0x00008700 /* Reset: PFR */ 4331 #define I40E_PFPE_UDAUCFBQPN 0x00008780 /* Reset: PFR */ 4336 #define I40E_PFPE_WQEALLOC 0x00138C00 /* Reset: PFR */ 4341 #define I40E_PRTDCB_RLPMC 0x0001F140 /* Reset: PE_CORER */ 4344 #define I40E_PRTDCB_TCMSTC_RLPM(_i) (0x0001F040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: PE_CORER */ 4348 #define I40E_PRTDCB_TCPMC_RLPM 0x0001F1A0 /* Reset: PE_CORER */ 4355 #define I40E_PRTE_RUPM_TCCNTR03 0x0000DAE0 /* Reset: PE_CORER */ 4364 #define I40E_PRTPE_RUPM_CNTR 0x0000DB20 /* Reset: PE_CORER */ 4367 #define I40E_PRTPE_RUPM_CTL 0x0000DA40 /* Reset: PE_CORER */ 4372 #define I40E_PRTPE_RUPM_PFCCTL 0x0000DA60 /* Reset: PE_CORER */ 4375 #define I40E_PRTPE_RUPM_PFCPC 0x0000DA80 /* Reset: PE_CORER */ 4378 #define I40E_PRTPE_RUPM_PFCTCC 0x0000DAA0 /* Reset: PE_CORER */ 4385 #define I40E_PRTPE_RUPM_PTCTCCNTR47 0x0000DB60 /* Reset: PE_CORER */ 4394 #define I40E_PRTPE_RUPM_PTXTCCNTR03 0x0000DB40 /* Reset: PE_CORER */ 4403 #define I40E_PRTPE_RUPM_TCCNTR47 0x0000DB00 /* Reset: PE_CORER */ 4412 #define I40E_PRTPE_RUPM_THRES 0x0000DA20 /* Reset: PE_CORER */ 4419 #define I40E_VFPE_AEQALLOC(_VF) (0x00130C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4423 #define I40E_VFPE_CCQPHIGH(_VF) (0x00001000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4427 #define I40E_VFPE_CCQPLOW(_VF) (0x00000C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4431 #define I40E_VFPE_CCQPSTATUS(_VF) (0x00000800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4441 #define I40E_VFPE_CQACK(_VF) (0x00130800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4445 #define I40E_VFPE_CQARM(_VF) (0x00130400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4449 #define I40E_VFPE_CQPDB(_VF) (0x00000000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4453 #define I40E_VFPE_CQPERRCODES(_VF) (0x00001800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4459 #define I40E_VFPE_CQPTAIL(_VF) (0x00000400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4465 #define I40E_VFPE_IPCONFIG0(_VF) (0x00001400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4471 #define I40E_VFPE_MRTEIDXMASK(_VF) (0x00003000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4475 #define I40E_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00003400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4479 #define I40E_VFPE_TCPNOWTIMER(_VF) (0x00002C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4483 #define I40E_VFPE_WQEALLOC(_VF) (0x00138000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4489 #define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4493 #define I40E_GLPES_PFIP4RXFRAGSHI(_i) (0x00010804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4497 #define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4501 #define I40E_GLPES_PFIP4RXMCOCTSHI(_i) (0x00010A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4505 #define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4509 #define I40E_GLPES_PFIP4RXMCPKTSHI(_i) (0x00010C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4513 #define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4517 #define I40E_GLPES_PFIP4RXOCTSHI(_i) (0x00010204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4521 #define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4525 #define I40E_GLPES_PFIP4RXPKTSHI(_i) (0x00010404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4529 #define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4533 #define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4537 #define I40E_GLPES_PFIP4TXFRAGSHI(_i) (0x00011E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4541 #define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4545 #define I40E_GLPES_PFIP4TXMCOCTSHI(_i) (0x00012004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4549 #define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4553 #define I40E_GLPES_PFIP4TXMCPKTSHI(_i) (0x00012204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4557 #define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4561 #define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4565 #define I40E_GLPES_PFIP4TXOCTSHI(_i) (0x00011A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4569 #define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4573 #define I40E_GLPES_PFIP4TXPKTSHI(_i) (0x00011C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4577 #define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4581 #define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4585 #define I40E_GLPES_PFIP6RXFRAGSHI(_i) (0x00011404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4589 #define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4593 #define I40E_GLPES_PFIP6RXMCOCTSHI(_i) (0x00011604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4597 #define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4601 #define I40E_GLPES_PFIP6RXMCPKTSHI(_i) (0x00011804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4605 #define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4609 #define I40E_GLPES_PFIP6RXOCTSHI(_i) (0x00010E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4613 #define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4617 #define I40E_GLPES_PFIP6RXPKTSHI(_i) (0x00011004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4621 #define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4625 #define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4629 #define I40E_GLPES_PFIP6TXFRAGSHI(_i) (0x00012804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4633 #define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4637 #define I40E_GLPES_PFIP6TXMCOCTSHI(_i) (0x00012A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4641 #define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4645 #define I40E_GLPES_PFIP6TXMCPKTSHI(_i) (0x00012C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4649 #define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4653 #define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4657 #define I40E_GLPES_PFIP6TXOCTSHI(_i) (0x00012404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4661 #define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4665 #define I40E_GLPES_PFIP6TXPKTSHI(_i) (0x00012604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4669 #define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4673 #define I40E_GLPES_PFRDMARXRDSHI(_i) (0x00013E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4677 #define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4681 #define I40E_GLPES_PFRDMARXSNDSHI(_i) (0x00014004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4685 #define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4689 #define I40E_GLPES_PFRDMARXWRSHI(_i) (0x00013C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4693 #define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4697 #define I40E_GLPES_PFRDMATXRDSHI(_i) (0x00014404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4701 #define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4705 #define I40E_GLPES_PFRDMATXSNDSHI(_i) (0x00014604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4709 #define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4713 #define I40E_GLPES_PFRDMATXWRSHI(_i) (0x00014204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4717 #define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4721 #define I40E_GLPES_PFRDMAVBNDHI(_i) (0x00014804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4725 #define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4729 #define I40E_GLPES_PFRDMAVINVHI(_i) (0x00014A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4733 #define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4737 #define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4741 #define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4745 #define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4749 #define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4753 #define I40E_GLPES_PFTCPRXSEGSHI(_i) (0x00013004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4757 #define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4761 #define I40E_GLPES_PFTCPTXSEGHI(_i) (0x00013404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4765 #define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4769 #define I40E_GLPES_PFUDPRXPKTSHI(_i) (0x00013804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4773 #define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4777 #define I40E_GLPES_PFUDPTXPKTSHI(_i) (0x00013A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4781 #define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4785 #define I40E_GLPES_RDMARXMULTFPDUSHI 0x0001E014 /* Reset: PE_CORER */ 4788 #define I40E_GLPES_RDMARXMULTFPDUSLO 0x0001E010 /* Reset: PE_CORER */ 4791 #define I40E_GLPES_RDMARXOOODDPHI 0x0001E01C /* Reset: PE_CORER */ 4794 #define I40E_GLPES_RDMARXOOODDPLO 0x0001E018 /* Reset: PE_CORER */ 4797 #define I40E_GLPES_RDMARXOOONOMARK 0x0001E004 /* Reset: PE_CORER */ 4800 #define I40E_GLPES_RDMARXUNALIGN 0x0001E000 /* Reset: PE_CORER */ 4803 #define I40E_GLPES_TCPRXFOURHOLEHI 0x0001E044 /* Reset: PE_CORER */ 4806 #define I40E_GLPES_TCPRXFOURHOLELO 0x0001E040 /* Reset: PE_CORER */ 4809 #define I40E_GLPES_TCPRXONEHOLEHI 0x0001E02C /* Reset: PE_CORER */ 4812 #define I40E_GLPES_TCPRXONEHOLELO 0x0001E028 /* Reset: PE_CORER */ 4815 #define I40E_GLPES_TCPRXPUREACKHI 0x0001E024 /* Reset: PE_CORER */ 4818 #define I40E_GLPES_TCPRXPUREACKSLO 0x0001E020 /* Reset: PE_CORER */ 4821 #define I40E_GLPES_TCPRXTHREEHOLEHI 0x0001E03C /* Reset: PE_CORER */ 4824 #define I40E_GLPES_TCPRXTHREEHOLELO 0x0001E038 /* Reset: PE_CORER */ 4827 #define I40E_GLPES_TCPRXTWOHOLEHI 0x0001E034 /* Reset: PE_CORER */ 4830 #define I40E_GLPES_TCPRXTWOHOLELO 0x0001E030 /* Reset: PE_CORER */ 4833 #define I40E_GLPES_TCPTXRETRANSFASTHI 0x0001E04C /* Reset: PE_CORER */ 4836 #define I40E_GLPES_TCPTXRETRANSFASTLO 0x0001E048 /* Reset: PE_CORER */ 4839 #define I40E_GLPES_TCPTXTOUTSFASTHI 0x0001E054 /* Reset: PE_CORER */ 4842 #define I40E_GLPES_TCPTXTOUTSFASTLO 0x0001E050 /* Reset: PE_CORER */ 4845 #define I40E_GLPES_TCPTXTOUTSHI 0x0001E05C /* Reset: PE_CORER */ 4848 #define I40E_GLPES_TCPTXTOUTSLO 0x0001E058 /* Reset: PE_CORER */ 4851 #define I40E_GLPES_VFIP4RXDISCARD(_i) (0x00018600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4855 #define I40E_GLPES_VFIP4RXFRAGSHI(_i) (0x00018804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4859 #define I40E_GLPES_VFIP4RXFRAGSLO(_i) (0x00018800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4863 #define I40E_GLPES_VFIP4RXMCOCTSHI(_i) (0x00018A04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4867 #define I40E_GLPES_VFIP4RXMCOCTSLO(_i) (0x00018A00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4871 #define I40E_GLPES_VFIP4RXMCPKTSHI(_i) (0x00018C04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4875 #define I40E_GLPES_VFIP4RXMCPKTSLO(_i) (0x00018C00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4879 #define I40E_GLPES_VFIP4RXOCTSHI(_i) (0x00018204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4883 #define I40E_GLPES_VFIP4RXOCTSLO(_i) (0x00018200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4887 #define I40E_GLPES_VFIP4RXPKTSHI(_i) (0x00018404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4891 #define I40E_GLPES_VFIP4RXPKTSLO(_i) (0x00018400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4895 #define I40E_GLPES_VFIP4RXTRUNC(_i) (0x00018700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4899 #define I40E_GLPES_VFIP4TXFRAGSHI(_i) (0x00019E04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4903 #define I40E_GLPES_VFIP4TXFRAGSLO(_i) (0x00019E00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4907 #define I40E_GLPES_VFIP4TXMCOCTSHI(_i) (0x0001A004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4911 #define I40E_GLPES_VFIP4TXMCOCTSLO(_i) (0x0001A000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4915 #define I40E_GLPES_VFIP4TXMCPKTSHI(_i) (0x0001A204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4919 #define I40E_GLPES_VFIP4TXMCPKTSLO(_i) (0x0001A200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4923 #define I40E_GLPES_VFIP4TXNOROUTE(_i) (0x0001AE00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4927 #define I40E_GLPES_VFIP4TXOCTSHI(_i) (0x00019A04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4931 #define I40E_GLPES_VFIP4TXOCTSLO(_i) (0x00019A00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4935 #define I40E_GLPES_VFIP4TXPKTSHI(_i) (0x00019C04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4939 #define I40E_GLPES_VFIP4TXPKTSLO(_i) (0x00019C00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4943 #define I40E_GLPES_VFIP6RXDISCARD(_i) (0x00019200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4947 #define I40E_GLPES_VFIP6RXFRAGSHI(_i) (0x00019404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4951 #define I40E_GLPES_VFIP6RXFRAGSLO(_i) (0x00019400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4955 #define I40E_GLPES_VFIP6RXMCOCTSHI(_i) (0x00019604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4959 #define I40E_GLPES_VFIP6RXMCOCTSLO(_i) (0x00019600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4963 #define I40E_GLPES_VFIP6RXMCPKTSHI(_i) (0x00019804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4967 #define I40E_GLPES_VFIP6RXMCPKTSLO(_i) (0x00019800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4971 #define I40E_GLPES_VFIP6RXOCTSHI(_i) (0x00018E04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4975 #define I40E_GLPES_VFIP6RXOCTSLO(_i) (0x00018E00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4979 #define I40E_GLPES_VFIP6RXPKTSHI(_i) (0x00019004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4983 #define I40E_GLPES_VFIP6RXPKTSLO(_i) (0x00019000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4987 #define I40E_GLPES_VFIP6RXTRUNC(_i) (0x00019300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4991 #define I40E_GLPES_VFIP6TXFRAGSHI(_i) (0x0001A804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4995 #define I40E_GLPES_VFIP6TXFRAGSLO(_i) (0x0001A800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4999 #define I40E_GLPES_VFIP6TXMCOCTSHI(_i) (0x0001AA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5003 #define I40E_GLPES_VFIP6TXMCOCTSLO(_i) (0x0001AA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5007 #define I40E_GLPES_VFIP6TXMCPKTSHI(_i) (0x0001AC04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5011 #define I40E_GLPES_VFIP6TXMCPKTSLO(_i) (0x0001AC00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5015 #define I40E_GLPES_VFIP6TXNOROUTE(_i) (0x0001AF00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 5019 #define I40E_GLPES_VFIP6TXOCTSHI(_i) (0x0001A404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5023 #define I40E_GLPES_VFIP6TXOCTSLO(_i) (0x0001A400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5027 #define I40E_GLPES_VFIP6TXPKTSHI(_i) (0x0001A604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5031 #define I40E_GLPES_VFIP6TXPKTSLO(_i) (0x0001A600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5035 #define I40E_GLPES_VFRDMARXRDSHI(_i) (0x0001BE04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5039 #define I40E_GLPES_VFRDMARXRDSLO(_i) (0x0001BE00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5043 #define I40E_GLPES_VFRDMARXSNDSHI(_i) (0x0001C004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5047 #define I40E_GLPES_VFRDMARXSNDSLO(_i) (0x0001C000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5051 #define I40E_GLPES_VFRDMARXWRSHI(_i) (0x0001BC04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5055 #define I40E_GLPES_VFRDMARXWRSLO(_i) (0x0001BC00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5059 #define I40E_GLPES_VFRDMATXRDSHI(_i) (0x0001C404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5063 #define I40E_GLPES_VFRDMATXRDSLO(_i) (0x0001C400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5067 #define I40E_GLPES_VFRDMATXSNDSHI(_i) (0x0001C604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5071 #define I40E_GLPES_VFRDMATXSNDSLO(_i) (0x0001C600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5075 #define I40E_GLPES_VFRDMATXWRSHI(_i) (0x0001C204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5079 #define I40E_GLPES_VFRDMATXWRSLO(_i) (0x0001C200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5083 #define I40E_GLPES_VFRDMAVBNDHI(_i) (0x0001C804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5087 #define I40E_GLPES_VFRDMAVBNDLO(_i) (0x0001C800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5091 #define I40E_GLPES_VFRDMAVINVHI(_i) (0x0001CA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5095 #define I40E_GLPES_VFRDMAVINVLO(_i) (0x0001CA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5099 #define I40E_GLPES_VFRXVLANERR(_i) (0x00018000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 5103 #define I40E_GLPES_VFTCPRTXSEG(_i) (0x0001B600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 5107 #define I40E_GLPES_VFTCPRXOPTERR(_i) (0x0001B200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 5111 #define I40E_GLPES_VFTCPRXPROTOERR(_i) (0x0001B300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 5115 #define I40E_GLPES_VFTCPRXSEGSHI(_i) (0x0001B004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5119 #define I40E_GLPES_VFTCPRXSEGSLO(_i) (0x0001B000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5123 #define I40E_GLPES_VFTCPTXSEGHI(_i) (0x0001B404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5127 #define I40E_GLPES_VFTCPTXSEGLO(_i) (0x0001B400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5131 #define I40E_GLPES_VFUDPRXPKTSHI(_i) (0x0001B804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5135 #define I40E_GLPES_VFUDPRXPKTSLO(_i) (0x0001B800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5139 #define I40E_GLPES_VFUDPTXPKTSHI(_i) (0x0001BA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5143 #define I40E_GLPES_VFUDPTXPKTSLO(_i) (0x0001BA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5147 #define I40E_GLGEN_PME_TO 0x000B81BC /* Reset: POR */ 5150 #define I40E_GLQF_APBVT(_i) (0x00260000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset: CORER */ 5154 #define I40E_GLQF_FD_PCTYPES(_i) (0x00268000 + ((_i) * 4)) /* _i=0...63 */ /* Reset: POR */ 5158 #define I40E_GLQF_FDEVICTENA(_i) (0x00270384 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 5162 #define I40E_GLQF_FDEVICTFLAG 0x00270280 /* Reset: CORER */ 5167 #define I40E_PFQF_CTL_2 0x00270300 /* Reset: CORER */ 5173 #define I40E_X722_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */ 5183 #define I40E_PFQF_HREGION(_i) (0x00245400 + ((_i) * 128)) /* _i=0...7 */ /* Reset: CORER */ 5219 #define I40E_VSIQF_HKEY(_i, _VSI) (0x002A0000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...12, _VSI=0...383 */ /* Reset: CORER */ 5229 #define I40E_VSIQF_HLUT(_i, _VSI) (0x00220000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...15, _VSI=0...383 */ /* Reset: CORER */ 5239 #define I40E_GLGEN_STAT_CLEAR 0x00390004 /* Reset: CORER */ 5242 #define I40E_GLGEN_STAT_HALT 0x00390000 /* Reset: CORER */ 5249 #define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */ 5252 #define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */ 5255 #define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */ 5258 #define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */ 5267 #define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */ 5270 #define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */ 5273 #define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */ 5276 #define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */ 5281 #define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */ 5286 #define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */ 5291 #define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */ 5294 #define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */ 5297 #define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */ 5300 #define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */
/linux-4.4.14/drivers/net/ethernet/ibm/emac/
H A D	emac.h	35 u32 mr1; /* Reset */ 38 u32 rmr; /* Reset */ 40 u32 iser; /* Reset */ 41 u32 iahr; /* Reset, R, T */ 42 u32 ialr; /* Reset, R, T */ 43 u32 vtpid; /* Reset, R, T */ 44 u32 vtci; /* Reset, R, T */ 45 u32 ptr; /* Reset, T */ 49 u32 iaht1; /* Reset, R */ 50 u32 iaht2; /* Reset, R */ 51 u32 iaht3; /* Reset, R */ 52 u32 iaht4; /* Reset, R */ 53 u32 gaht1; /* Reset, R */ 54 u32 gaht2; /* Reset, R */ 55 u32 gaht3; /* Reset, R */ 56 u32 gaht4; /* Reset, R */ 60 u32 mahr; /* Reset, R, T */ 61 u32 malr; /* Reset, R, T */ 62 u32 mmahr; /* Reset, R, T */ 63 u32 mmalr; /* Reset, R, T */ 70 u32 ipgvr; /* Reset, T */ 73 u32 rwmr; /* Reset */ 86 u32 iaht1; /* Reset, R */ 87 u32 iaht2; /* Reset, R */ 88 u32 iaht3; /* Reset, R */ 89 u32 iaht4; /* Reset, R */ 90 u32 iaht5; /* Reset, R */ 91 u32 iaht6; /* Reset, R */ 92 u32 iaht7; /* Reset, R */ 93 u32 iaht8; /* Reset, R */ 94 u32 gaht1; /* Reset, R */ 95 u32 gaht2; /* Reset, R */ 96 u32 gaht3; /* Reset, R */ 97 u32 gaht4; /* Reset, R */ 98 u32 gaht5; /* Reset, R */ 99 u32 gaht6; /* Reset, R */ 100 u32 gaht7; /* Reset, R */ 101 u32 gaht8; /* Reset, R */ 102 u32 tpc; /* Reset, T */
H A D	tah.c	32 /* Reset has been done at probe() time... nothing else to do for now */ tah_attach() 54 /* Reset TAH */ tah_reset()
/linux-4.4.14/drivers/net/ethernet/intel/i40evf/
H A D	i40e_register.h	30 #define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */ 34 #define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 40 #define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 44 #define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 48 #define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 52 #define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */ 55 #define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */ 58 #define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */ 61 #define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */ 72 #define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ 75 #define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ 78 #define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ 81 #define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */ 84 #define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */ 95 #define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ 98 #define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ 101 #define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ 118 #define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */ 136 #define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */ 143 #define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */ 160 #define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ 164 #define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */ 168 #define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */ 171 #define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */ 175 #define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */ 179 #define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */ 182 #define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 188 #define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 192 #define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 196 #define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 200 #define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */ 207 #define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */ 218 #define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 222 #define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ 232 #define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 242 #define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */ 280 #define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */ 283 #define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */ 286 #define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */ 289 #define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */ 298 #define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */ 301 #define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */ 304 #define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */ 307 #define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */ 312 #define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */ 317 #define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */ 322 #define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */ 325 #define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */ 328 #define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */ 331 #define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */
/linux-4.4.14/arch/arm/mach-pxa/include/mach/
H A D	reset.h	4 #define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */ 5 #define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */ 7 #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */
H A D	mainstone.h	76 #define MST_MSCWR3_GPIO_RESET_EN (1 << 2) /* Enable GPIO Reset */ 77 #define MST_MSCWR3_GPIO_RESET (1 << 1) /* Initiate a GPIO Reset */ 78 #define MST_MSCWR3_COMMS_SW_RESET (1 << 0) /* Communications Processor Reset Control */
H A D	pxa2xx-regs.h	35 #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ 110 #define RCSR_GPR (1 << 3) /* GPIO Reset */ 112 #define RCSR_WDR (1 << 1) /* Watchdog Reset */ 113 #define RCSR_HWR (1 << 0) /* Hardware Reset */
H A D	regs-ac97.h	34 #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ 35 #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
H A D	gumstix.h	11 /* BTRESET - Reset line to Bluetooth module, active low signal. */
/linux-4.4.14/include/linux/input/
H A D	cy8ctmg110_pdata.h	6 int reset_pin; /* Reset pin is wired to this GPIO (optional) */
H A D	adp5589.h	159 unsigned char reset_cfg; /* Reset config */ 160 unsigned short reset1_key_1; /* Reset Key 1 */ 161 unsigned short reset1_key_2; /* Reset Key 2 */ 162 unsigned short reset1_key_3; /* Reset Key 3 */ 163 unsigned short reset2_key_1; /* Reset Key 1 */ 164 unsigned short reset2_key_2; /* Reset Key 2 */
/linux-4.4.14/arch/sh/include/mach-common/mach/
H A D	r2d.h	22 #define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */ 24 #define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */ 25 #define PA_R2D1_CFRST 0xa4000024 /* CF Reset control */ 26 #define PA_R2D1_ADMRTS 0xa4000026 /* SD Reset control */ 27 #define PA_R2D1_EXTRST 0xa4000028 /* Extension Reset control */ 30 #define PA_R2DPLUS_CFRST 0xa4000022 /* CF Reset control */ 31 #define PA_R2DPLUS_ADMRTS 0xa4000024 /* SD Reset control */ 32 #define PA_R2DPLUS_EXTRST 0xa4000026 /* Extension Reset control */
H A D	secureedge5410.h	26 * D1 Reset Switch heatbeat
H A D	sdk7780.h	58 #define FPGA_RSE (PA_FPGA + 0x100) /* Reset source */
/linux-4.4.14/drivers/power/reset/
H A D	at91-reset.c	24 #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */ 25 #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */ 26 #define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */ 27 #define AT91_RSTC_EXTRST BIT(3) /* External Reset */ 30 #define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */ 31 #define AT91_RSTC_URSTS BIT(0) /* User Reset Status */ 32 #define AT91_RSTC_RSTTYP GENMASK(10, 8) /* Reset Type */ 34 #define AT91_RSTC_SRCMP BIT(17) /* Software Reset Command in Progress */ 36 #define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */ 37 #define AT91_RSTC_URSTEN BIT(0) /* User Reset Enable */ 38 #define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */ 39 #define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */ 70 /* Reset CPU */ at91sam9260_restart() 112 /* Reset CPU */ at91sam9g45_restart() 256 MODULE_DESCRIPTION("Reset driver for Atmel SoCs");
H A D	rmobile-reset.c	2 * Renesas R-Mobile Reset Driver 20 #define RESCNT2 0x20 /* Reset Control Register 2 */ 22 /* Reset Control Register 2 */ 89 MODULE_DESCRIPTION("Renesas R-Mobile Reset Driver");
H A D	axxia-reset.c	2 * Reset driver for Axxia devices
/linux-4.4.14/drivers/edac/
H A D	octeon_edac-pci.c	31 cfg01.s.dpe = 1; /* Reset */ octeon_pci_poll() 36 cfg01.s.sse = 1; /* Reset */ octeon_pci_poll() 41 cfg01.s.rma = 1; /* Reset */ octeon_pci_poll() 46 cfg01.s.rta = 1; /* Reset */ octeon_pci_poll() 51 cfg01.s.sta = 1; /* Reset */ octeon_pci_poll() 56 cfg01.s.mdpe = 1; /* Reset */ octeon_pci_poll()
/linux-4.4.14/arch/powerpc/include/asm/
H A D	mpc5121.h	11 /* MPC512x Reset module registers */ 13 u32 rcwlr; /* Reset Configuration Word Low Register */ 14 u32 rcwhr; /* Reset Configuration Word High Register */ 17 u32 rsr; /* Reset Status Register */ 18 u32 rmr; /* Reset Mode Register */ 19 u32 rpr; /* Reset Protection Register */ 20 u32 rcr; /* Reset Control Register */ 21 u32 rcer; /* Reset Control Enable Register */
H A D	mmu-8xx.h	51 /* Reset value is undefined */ 65 /* Reset value is undefined */ 124 /* Reset value is undefined */ 133 /* Reset value is undefined */ 151 /* Reset value is undefined */
H A D	dcr-regs.h	168 /* 440SP/440SPe Software Reset DCR */ 170 #define DCRN_SDR0_SRST_I2ODMA (0x80000000 >> 15) /* Reset I2O/DMA */
H A D	hydra.h	66 #define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */
/linux-4.4.14/include/linux/platform_data/
H A D	bd6107.h	15 int reset; /* Reset GPIO */
/linux-4.4.14/arch/mips/dec/
H A D	reset.c	2 * Reset a DECstation machine.
/linux-4.4.14/arch/arm64/kvm/
H A D	reset.c	35 * ARMv8 Reset Values 117 /* Reset core registers */ kvm_reset_vcpu() 120 /* Reset system registers */ kvm_reset_vcpu() 123 /* Reset timer */ kvm_reset_vcpu()
/linux-4.4.14/arch/arm/mach-mmp/include/mach/
H A D	regs-apbc.h	19 #define APBC_RST (1 << 2) /* Reset Generation */
/linux-4.4.14/arch/arm/kvm/
H A D	reset.c	33 * Cortex-A15 and Cortex-A7 Reset Values 73 /* Reset core registers */ kvm_reset_vcpu() 76 /* Reset CP15 registers */ kvm_reset_vcpu() 79 /* Reset arch_timer context */ kvm_reset_vcpu()
/linux-4.4.14/arch/arm/mach-socfpga/
H A D	core.h	32 #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ 33 #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ 35 #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
/linux-4.4.14/drivers/scsi/
H A D	aha1542.h	21 #define SCRD BIT(3) /* SCSI Reset Detected */ 29 #define HRST BIT(7) /* Hard Reset */ 30 #define SRST BIT(6) /* Soft Reset */ 31 #define IRST BIT(5) /* Interrupt Reset */ 32 #define SCRST BIT(4) /* SCSI Bus Reset */
H A D	a100u2w.c	114 0x0A, /* 0x13: SCSI Reset Recovering time */ 125 0x0A, /* 0x29: SCSI Reset Recovering time */ 418 outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Reset program count 0 */ orc_load_firmware() 419 bios_addr -= 0x1000; /* Reset the BIOS address */ orc_load_firmware() 427 outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ orc_load_firmware() 436 outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ orc_load_firmware() 511 outb(DEVRST, host->base + ORC_HCTRL); /* Reset Host Adapter */ init_orchid() 524 outb(DEVRST, host->base + ORC_HCTRL); /* Reset Host Adapter */ init_orchid() 529 outb(HDO, host->base + ORC_HCTRL); /* Do Hardware Reset & */ init_orchid() 591 * Reset registers, reset a hanging bus and kill active and disconnected 623 printk(KERN_ERR "Unable to Reset - No SCB Found\n"); orc_device_reset() 635 /* Reset device is handled by the firmware, we fill in an SCB and orc_device_reset() 953 Description : Reset registers, reset a hanging bus and 968 Description : Reset the device 1018 will generate a SCSI Reset Condition, notifying the host with inia100_scb_handler()
/linux-4.4.14/include/media/
H A D	tc358743.h	94 /* Reset PHY automatically when TMDS clock goes from DC to AC. 100 /* Reset PHY automatically when TMDS clock passes 21 MHz. 106 /* Reset PHY automatically when TMDS clock is detected. 112 /* Reset HDMI PHY automatically when hsync period is out of range. 118 /* Reset HDMI PHY automatically when vsync period is out of range.
/linux-4.4.14/drivers/scsi/snic/
H A D	snic_stats.h	48 atomic64_t dev_resets; /* Device Reset Counter */ 49 atomic64_t dev_reset_fail; /* Device Reset Failures */ 50 atomic64_t dev_reset_aborts; /* Device Reset Aborts */ 51 atomic64_t dev_reset_tmo; /* Device Reset Timeout */ 52 atomic64_t dev_reset_terms; /* Device Reset terminate */ 79 atomic64_t devrst_wq_alloc_fail;/* Device Reset - WQ desc alloc fail */
H A D	snic_scsi.c	702 "itmf_cmpl: Terminate Pending Dev Reset Cmpl Recvd.id %x, status %s flags 0x%llx\n", snic_proc_dr_cmpl_locked() 717 "itmf_cmpl:Dev Reset Completion Received after timeout. id %d cmpl status %s flags 0x%llx\n", snic_proc_dr_cmpl_locked() 729 "itmf_cmpl:Dev Reset Cmpl Recvd id %d cmpl status %s flags 0x%llx\n", snic_proc_dr_cmpl_locked() 971 SNIC_SCSI_DBG(snic->shost, "HBA Reset scsi cleanup.\n"); snic_hba_reset_scsi_cleanup() 1005 "reset_cmpl:HBA Reset Completion received.\n"); snic_hba_reset_cmpl_handler() 1718 /* Ignore Cmd that don't belong to Lun Reset device */ snic_dr_clean_single_req() 1919 "dr_fini: Tag %x Dev Reset Timedout. flags 0x%llx\n", snic_dr_finish() 1929 "dr_fini: Tag %x Dev Reset cmpl\n", snic_dr_finish() 1936 "dr_fini:Device Reset completed& failed.Tag = %x lr_status %s flags 0x%llx\n", snic_dr_finish() 1946 * If any of these fail, then LUN Reset fails. snic_dr_finish() 1948 * the lun reset command. If all cmds get cleaned, the LUN Reset snic_dr_finish() 1956 "dr_fini: Device Reset Failed since could not abort all IOs. Tag = %x.\n", snic_dr_finish() 1962 /* Cleanup LUN Reset Command */ snic_dr_finish() 2035 * This logic still makes LUN Reset is inevitable. snic_send_dr_and_wait() 2112 * SCSI Eh thread issues a LUN Reset when one or more commands on a LUN 2133 SNIC_HOST_INFO(shost, "LUN Reset Op not supported.\n"); snic_device_reset() 2149 "Devrst: LUN Reset Recvd thru IOCTL.\n"); snic_device_reset() 2184 "Devrst: Returning from Device Reset : %s\n", snic_device_reset() 2194 * Host Reset is the highest level of error recovery. If this fails, then 2198 * snic_issue_hba_reset : Queues FW Reset Request. 2244 "issu_hr:Queuing HBA Reset Failed. w err %d\n", snic_issue_hba_reset() 2254 SNIC_HOST_INFO(snic->shost, "Queued HBA Reset Successfully.\n"); snic_issue_hba_reset() 2260 SNIC_HOST_ERR(snic->shost, "reset_cmpl: Reset Timedout.\n"); snic_issue_hba_reset() 2291 "reset:HBA Reset Failed w/ err = %d.\n", snic_issue_hba_reset() 2330 "reset:Host Reset Failed w/ err %d.\n", snic_reset() 2351 * Host Reset is the highest level of error recovery. If this fails, then
/linux-4.4.14/drivers/net/ethernet/sfc/
H A D	enum.h	137 * Reset methods are numbered in order of increasing scope. 139 * @RESET_TYPE_INVISIBLE: Reset datapath and MAC (Falcon only) 142 * @RESET_TYPE_ALL: Reset datapath, MAC and PHY 143 * @RESET_TYPE_WORLD: Reset as much as possible 146 * @RESET_TYPE_DATAPATH: Reset datapath only. 148 * @RESET_TYPE_DISABLE: Reset datapath, MAC and PHY; leave NIC disabled
/linux-4.4.14/drivers/tty/serial/
H A D	sunzilog.h	49 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ 51 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ 52 #define RES_Tx_P 0x28 /* Reset TxINT Pending */ 53 #define ERR_RES 0x30 /* Error Reset */ 54 #define RES_H_IUS 0x38 /* Reset highest IUS */ 56 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ 57 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ 58 #define RES_EOM_L 0xC0 /* Reset EOM latch */ 133 #define AUTO_EOM_RST 2 /* Automatic EOM Reset */ 150 #define CHRB 0x40 /* Reset channel B */ 151 #define CHRA 0x80 /* Reset channel A */ 193 #define RMC 0x40 /* Reset missing clock */
H A D	ip22zilog.h	57 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ 59 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ 60 #define RES_Tx_P 0x28 /* Reset TxINT Pending */ 61 #define ERR_RES 0x30 /* Error Reset */ 62 #define RES_H_IUS 0x38 /* Reset highest IUS */ 64 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ 65 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ 66 #define RES_EOM_L 0xC0 /* Reset EOM latch */ 148 #define CHRB 0x40 /* Reset channel B */ 149 #define CHRA 0x80 /* Reset channel A */ 191 #define RMC 0x40 /* Reset missing clock */
H A D	zs.h	78 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ 80 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ 81 #define RES_Tx_P 0x28 /* Reset TxINT Pending */ 82 #define ERR_RES 0x30 /* Error Reset */ 83 #define RES_H_IUS 0x38 /* Reset highest IUS */ 85 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ 86 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ 87 #define RES_EOM_L 0xC0 /* Reset EOM latch */ 167 #define CHRB 0x40 /* Reset channel B */ 168 #define CHRA 0x80 /* Reset channel A */ 210 #define RMC 0x40 /* Reset missing clock */
H A D	pmac_zilog.h	146 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ 148 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ 149 #define RES_Tx_P 0x28 /* Reset TxINT Pending */ 150 #define ERR_RES 0x30 /* Error Reset */ 151 #define RES_H_IUS 0x38 /* Reset highest IUS */ 153 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ 154 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ 155 #define RES_EOM_L 0xC0 /* Reset EOM latch */ 241 #define CHRB 0x40 /* Reset channel B */ 242 #define CHRA 0x80 /* Reset channel A */ 284 #define RMC 0x40 /* Reset missing clock */
H A D	sh-sci.h	86 #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */ 87 #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
/linux-4.4.14/drivers/net/hamradio/
H A D	z8530.h	25 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ 27 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ 28 #define RES_Tx_P 0x28 /* Reset TxINT Pending */ 29 #define ERR_RES 0x30 /* Error Reset */ 30 #define RES_H_IUS 0x38 /* Reset highest IUS */ 32 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ 33 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ 34 #define RES_EOM_L 0xC0 /* Reset EOM latch */ 112 #define CHRB 0x40 /* Reset channel B */ 113 #define CHRA 0x80 /* Reset channel A */ 155 #define RMC 0x40 /* Reset missing clock */ 226 #define AUTOEOM 0x02 /* Auto EOM Latch Reset */
/linux-4.4.14/drivers/net/wireless/b43/
H A D	phy_ac.h	7 #define B43_PHY_AC_BBCFG_RSTCCA 0x4000 /* Reset CCA */
H A D	phy_ht.h	8 #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */ 9 #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */ 80 #define B43_PHY_HT_RF_SEQ_TRIG_RST2RX 0x0020 /* Reset to RX */ 110 #define B43_PHY_B_BBCFG_RSTCCA 0x4000 /* Reset CCA */ 111 #define B43_PHY_B_BBCFG_RSTRX 0x8000 /* Reset RX */
/linux-4.4.14/include/sound/
H A D	cs42l52.h	28 /* Reset GPIO */
H A D	cs42l56.h	16 /* GPIO for Reset */
H A D	cs4271.h	21 int gpio_nreset; /* GPIO driving Reset pin, if any */
/linux-4.4.14/arch/mips/sni/
H A D	reset.c	4 * Reset a SNI machine.
/linux-4.4.14/arch/arm/mach-omap2/
H A D	prm-regbits-24xx.h	5 * OMAP24XX Power/Reset Management register bits
H A D	prminst44xx.h	2 * OMAP4 Power/Reset Management (PRM) function prototypes
H A D	prm-regbits-34xx.h	2 * OMAP3430 Power/Reset Management register bits
/linux-4.4.14/include/linux/mtd/
H A D	ndfc.h	33 #define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */ 34 #define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */
/linux-4.4.14/arch/sh/include/cpu-sh2/cpu/
H A D	watchdog.h	38 * sh_wdt_read_rstcsr - Read from Reset Control/Status Register 51 * sh_wdt_write_csr - Write to Reset Control/Status Register
/linux-4.4.14/arch/microblaze/kernel/
H A D	reset.c	42 pr_debug("Reset: Gpio output state: 0x%x\n", reset_val); of_platform_reset_gpio_probe() 66 pr_notice("Reset GPIO unavailable - halting!\n"); gpio_system_reset()
/linux-4.4.14/arch/mips/txx9/rbtx4927/
H A D	setup.c	73 /* Reset PCI Bus */ tx4927_pci_setup() 75 /* Reset PCIC */ tx4927_pci_setup() 91 /* Reset PCI Bus */ tx4927_pci_setup() 93 /* Reset PCIC */ tx4927_pci_setup() 120 /* Reset PCI Bus */ tx4937_pci_setup() 122 /* Reset PCIC */ tx4937_pci_setup() 138 /* Reset PCI Bus */ tx4937_pci_setup() 140 /* Reset PCIC */ tx4937_pci_setup()
/linux-4.4.14/drivers/usb/dwc3/
H A D	debug.h	113 return "Hot Reset"; dwc3_gadget_link_string() 119 return "Reset"; dwc3_gadget_link_string() 137 return "Reset"; dwc3_gadget_event_string() 193 return "Reset"; dwc3_gadget_event_type_string()
/linux-4.4.14/drivers/scsi/qla4xxx/
H A D	ql4_83xx.c	489 /* NIC, iSCSI and FCOE are the Reset owners based on order, NIC gets qla4_83xx_can_perform_reset() 521 /* Non-reset owners ACK Reset and wait for device INIT state qla4_83xx_need_reset_handler() 522 * as part of Reset Recovery by Reset Owner */ qla4_83xx_need_reset_handler() 527 ql4_printk(KERN_INFO, ha, "%s: Non Reset owner dev init timeout\n", qla4_83xx_need_reset_handler() 575 /* Start Reset Recovery */ qla4_83xx_need_reset_handler() 600 /*-------------------------Reset Sequence Functions-----------------------*/ 615 "Reset Template: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n", qla4_83xx_dump_reset_seq_hdr() 761 ql4_printk(KERN_ERR, ha, "%s: Reset seq checksum failed\n", qla4_83xx_reset_seq_checksum_test() 770 * qla4_83xx_read_reset_template - Read Reset Template from Flash 838 ql4_printk(KERN_ERR, ha, "%s: Reset Seq checksum failed!\n", qla4_83xx_read_reset_template() 843 "%s: Reset Seq checksum passed, Get stop, start and init seq offsets\n", qla4_83xx_read_reset_template() 1095 "%s: Reset sequence completed SUCCESSFULLY.\n", qla4_83xx_template_end() 1098 ql4_printk(KERN_ERR, ha, "%s: Reset sequence completed with some timeout errors.\n", qla4_83xx_template_end() 1108 * Reset Entry header, entry opcode/command, with size of the entry, number 1361 ql4_printk(KERN_ERR, ha, "%s: Reset recovery disabled\n", qla4_83xx_isp_reset() 1374 * Reset,irrespective of ql4xdontresethba. This is to allow a qla4_83xx_isp_reset() 1376 * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset qla4_83xx_isp_reset() 1377 * and then forces a Reset by setting device_state to qla4_83xx_isp_reset() 1384 /* For ISP8324 and ISP8042, Reset owner is NIC, iSCSI or FCOE based on qla4_83xx_isp_reset() 1386 * setting NEED_RESET, may not be the Reset owner. */ qla4_83xx_isp_reset() 1463 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ qla4_83xx_dump_pause_control_regs() 1481 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ qla4_83xx_dump_pause_control_regs() 1560 /* Write any value to Reset Control register */ qla4_83xx_eport_init()
H A D	ql4_attr.c	77 /* Reset HBA and collect FW dump */ qla4_8xxx_sysfs_write_fw_dump() 90 ql4_printk(KERN_INFO, ha, "%s: Reset owner is 0x%x\n", qla4_8xxx_sysfs_write_fw_dump() 95 "%s: Reset not performed as device state is 0x%x\n", qla4_8xxx_sysfs_write_fw_dump()
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/reset/
H A D	stih407-resets.h	25 /* Reset defines */
/linux-4.4.14/include/dt-bindings/reset/
H A D	stih407-resets.h	25 /* Reset defines */
/linux-4.4.14/include/linux/can/platform/
H A D	cc770.h	11 #define CPUIF_RST 0x80 /* Hardware Reset Status */
/linux-4.4.14/include/linux/dma/
H A D	xilinx_dma.h	28 * @reset: Reset Channel
/linux-4.4.14/arch/mips/jazz/
H A D	reset.c	2 * Reset a Jazz machine.
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/reset/
H A D	stih407-resets.h	25 /* Reset defines */
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/reset/
H A D	stih407-resets.h	25 /* Reset defines */
/linux-4.4.14/arch/mips/cobalt/
H A D	reset.c	2 * Cobalt Reset operations
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/reset/
H A D	stih407-resets.h	25 /* Reset defines */
/linux-4.4.14/arch/hexagon/kernel/
H A D	vm_vectors.S	41 jump 1b; /* Reset */
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/reset/
H A D	stih407-resets.h	25 /* Reset defines */
/linux-4.4.14/arch/blackfin/include/mach-common/
H A D	irq.h	17 * Reset RST 1
/linux-4.4.14/arch/arm/mach-omap1/
H A D	reset.c	30 * "Global Software Reset Affects Traffic Controller Frequency". omap1_restart()
H A D	fpga.h	37 #define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
/linux-4.4.14/arch/arm/mach-s3c24xx/
H A D	anubis.h	18 /* CTRL2 - NAND WP control, IDE Reset assert/check */
H A D	h1940-bluetooth.c	37 /* Reset the chip */ h1940bt_enable()
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/reset/
H A D	stih407-resets.h	25 /* Reset defines */
/linux-4.4.14/drivers/watchdog/
H A D	at91sam9_wdt.h	27 #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
H A D	iop_wdt.c	234 /* Configure Watchdog Timeout to cause an Internal Bus (IB) Reset iop_wdt_init() 235 * NOTE: An IB Reset will Reset both cores in the IOP342 iop_wdt_init()
H A D	smsc37b787_wdt.c	178 * Bit 0 Joystick enable: 0* = No Reset, 1 = Reset WDT upon wdt_timer_conf() 180 * Bit 1 Keyboard enable: 0* = No Reset, 1 = Reset WDT upon KBD Intr. wdt_timer_conf() 181 * Bit 2 Mouse enable: 0* = No Reset, 1 = Reset WDT upon Mouse Intr wdt_timer_conf() 182 * Bit 3 Reset the timer wdt_timer_conf()
H A D	da9052_wdt.c	146 /* Reset the watchdog timer */ da9052_wdt_ping() 153 * FIXME: Reset the watchdog core, in general PMIC da9052_wdt_ping()
H A D	it8712f_wdt.c	79 #define WDT_RESET_GAME 0x10 /* Reset timer on read or write to game port */ 80 #define WDT_RESET_KBD 0x20 /* Reset timer on keyboard interrupt */ 81 #define WDT_RESET_MOUSE 0x40 /* Reset timer on mouse interrupt */ 82 #define WDT_RESET_CIR 0x80 /* Reset timer on consumer IR interrupt */
H A D	sch311x_wdt.c	388 * Bit 1 Keyboard enable: 0* = No Reset, 1 = Reset WDT upon KBD Intr. sch311x_wdt_probe() 389 * Bit 2 Mouse enable: 0* = No Reset, 1 = Reset WDT upon Mouse Intr sch311x_wdt_probe()
/linux-4.4.14/drivers/net/wan/
H A D	z85230.h	46 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ 48 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ 49 #define RES_Tx_P 0x28 /* Reset TxINT Pending */ 50 #define ERR_RES 0x30 /* Error Reset */ 51 #define RES_H_IUS 0x38 /* Reset highest IUS */ 53 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ 54 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ 55 #define RES_EOM_L 0xC0 /* Reset EOM latch */ 133 #define CHRB 0x40 /* Reset channel B */ 134 #define CHRA 0x80 /* Reset channel A */ 176 #define RMC 0x40 /* Reset missing clock */
/linux-4.4.14/drivers/char/mwave/
H A D	3780i.h	165 unsigned short ResetCore:1; /* RW: Reset MSP core interface */ 175 unsigned short Memory:1; /* RW: Reset memory interface */ 176 unsigned short SerialPort1:1; /* RW: Reset serial port 1 interface */ 177 unsigned short SerialPort2:1; /* RW: Reset serial port 2 interface */ 178 unsigned short SerialPort3:1; /* RW: Reset serial port 3 interface */ 179 unsigned short Gpio:1; /* RW: Reset GPIO interface */ 180 unsigned short Dma:1; /* RW: Reset DMA interface */ 181 unsigned short SoundBlaster:1; /* RW: Reset soundblaster interface */ 182 unsigned short Uart:1; /* RW: Reset UART interface */ 183 unsigned short Midi:1; /* RW: Reset MIDI interface */ 184 unsigned short IsaMaster:1; /* RW: Reset ISA master interface */
/linux-4.4.14/drivers/pcmcia/
H A D	pxa2xx_vpac270.c	27 { GPIO11_VPAC270_PCMCIA_RESET, GPIOF_INIT_LOW, "PCMCIA Reset" }, 31 { GPIO16_VPAC270_CF_RESET, GPIOF_INIT_LOW, "CF Reset" },
H A D	pxa2xx_palmtc.c	28 { GPIO_NR_PALMTC_PCMCIA_RESET, GPIOF_INIT_HIGH,"PCMCIA Reset" }, 92 /* Reset the card */ palmtc_wifi_powerup()
H A D	pxa2xx_palmld.c	25 { GPIO_NR_PALMLD_PCMCIA_RESET, GPIOF_INIT_HIGH,"PCMCIA Reset" },
H A D	pxa2xx_palmtx.c	25 { GPIO_NR_PALMTX_PCMCIA_RESET, GPIOF_INIT_HIGH,"PCMCIA Reset" },
H A D	pxa2xx_stargate2.c	37 { SG2_S0_GPIO_RESET, GPIOF_OUT_INIT_HIGH, "PCMCIA Reset" },
/linux-4.4.14/arch/mips/include/asm/mach-ath25/
H A D	ath25_platform.h	26 #define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */ 40 u16 reset_config_gpio; /* Reset factory GPIO pin */
/linux-4.4.14/arch/arm/mach-ks8695/include/mach/
H A D	regs-uart.h	42 #define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */ 43 #define URFC_URRFR (1 << 1) /* Receive FIFO Reset */
H A D	regs-lan.h	37 #define LMDTXC_LMTRST (1 << 31) /* Soft Reset */
H A D	regs-wan.h	37 #define WMDTXC_WMTRST (1 << 31) /* Soft Reset */
/linux-4.4.14/arch/m68k/include/asm/
H A D	mcfuart.h	52 #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ 118 #define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */ 119 #define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */ 120 #define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */ 121 #define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */ 122 #define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
H A D	dvma.h	151 #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */ 152 #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */ 222 /* Reset the friggin' thing... */ 227 /* Reset the logic */ \
H A D	contregs.h	40 #define AC_M_RESET 0x0700 /* hv Reset Reg */
/linux-4.4.14/sound/soc/davinci/
H A D	davinci-mcasp.h	247 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */ 250 #define RXSMRST BIT(3) /* Receiver State Machine Reset */ 251 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */ 252 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */ 255 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */ 256 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
/linux-4.4.14/drivers/net/ppp/
H A D	ppp_mppe.c	346 * We received a CCP Reset-Request (actually, we are sending a Reset-Ack), 348 * every CCP Reset-Request; we only rekey on the next xmit packet. 349 * We might get multiple CCP Reset-Requests if our CCP Reset-Ack is lost. 350 * So, rekeying for every CCP Reset-Request is broken as the peer will not 352 * CCP Reset-Request, we must rekey again.) 409 (state->bits & MPPE_BIT_FLUSHED)) { /* CCP Reset-Request */ mppe_compress() 462 * We received a CCP Reset-Ack. Just ignore it. 557 * Signal the peer to rekey (by sending a CCP Reset-Request). mppe_decompress() 565 /* ccp.c will be silent (no additional CCP Reset-Requests). */ mppe_decompress() 582 * peer need not send a Reset-Ack packet. But RFC 1962 mppe_decompress() 583 * requires it. Hopefully, M$ does send a Reset-Ack; even mppe_decompress()
/linux-4.4.14/net/dccp/
H A D	input.c	220 * If P.type == CloseReq or P.type == Close or P.type == Reset, dccp_check_seqno() 252 * If P.type == Reset, dccp_check_seqno() 306 * Step 9: Process Reset __dccp_rcv_established() 307 * If P.type == Reset, __dccp_rcv_established() 396 * If (P.type == Response or P.type == Reset) dccp_rcv_request_sent_state_process() 401 * / * Response processing continues in Step 10; Reset dccp_rcv_request_sent_state_process() 421 * dccp_v4_do_rcv() sends a Reset. The Reset code depends on dccp_rcv_request_sent_state_process() 601 * Generate Reset(No Connection) unless P.type == Reset dccp_rcv_state_process() 614 /* Caller (dccp_v4_do_rcv) will send Reset */ dccp_rcv_state_process() 648 * Step 9: Process Reset dccp_rcv_state_process() 649 * If P.type == Reset, dccp_rcv_state_process()
/linux-4.4.14/drivers/isdn/hisax/
H A D	nj_s.c	103 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ reset_netjet_s() 109 cs->hw.njet.ctrl_reg = 0x40; /* Reset Off and status read clear */ reset_netjet_s() 111 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ reset_netjet_s() 195 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ njs_cs_init() 199 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ njs_cs_init()
H A D	bkm_ax.h	72 #define g_A4T_JADE_RES 0x01000000 /* JADE Reset (High) */ 73 #define g_A4T_ISAR_RES 0x02000000 /* ISAR Reset (High) */ 74 #define g_A4T_ISAC_RES 0x04000000 /* ISAC Reset (High) */
H A D	nj_u.c	86 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ reset_netjet_u() 89 cs->hw.njet.ctrl_reg = 0x40; /* Reset Off and status read clear */ reset_netjet_u() 156 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ nju_cs_init() 160 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ nju_cs_init()
/linux-4.4.14/drivers/input/misc/
H A D	cma3000_d0x.c	162 /* Reset sequence */ cma3000_reset() 163 CMA3000_SET(data, CMA3000_RSTR, 0x02, "Reset"); cma3000_reset() 164 CMA3000_SET(data, CMA3000_RSTR, 0x0A, "Reset"); cma3000_reset() 165 CMA3000_SET(data, CMA3000_RSTR, 0x04, "Reset"); cma3000_reset() 172 dev_err(data->dev, "Reset failed\n"); cma3000_reset()
/linux-4.4.14/include/linux/
H A D	atmel_serial.h	20 #define ATMEL_US_RSTRX BIT(2) /* Reset Receiver */ 21 #define ATMEL_US_RSTTX BIT(3) /* Reset Transmitter */ 26 #define ATMEL_US_RSTSTA BIT(8) /* Reset Status Bits */ 31 #define ATMEL_US_RSTIT BIT(13) /* Reset Iterations */ 32 #define ATMEL_US_RSTNACK BIT(14) /* Reset Non Acknowledge */
H A D	ppp-comp.h	49 /* Reset a compressor */ 70 /* Reset a decompressor */
H A D	pcieport_if.h	54 /* Link Reset Capability - AER service driver specific */
/linux-4.4.14/arch/mips/txx9/rbtx4938/
H A D	setup.c	52 /* Reset PCI Bus */ rbtx4938_pci_setup() 54 /* Reset PCIC */ rbtx4938_pci_setup() 70 /* Reset PCI Bus */ rbtx4938_pci_setup() 72 /* Reset PCIC */ rbtx4938_pci_setup() 87 /* Reset PCIC1 */ rbtx4938_pci_setup()
/linux-4.4.14/drivers/isdn/act2000/
H A D	act2000_isa.h	44 #define ISA_COR_RESET 0x80 /* Soft Reset for Transputer */ 56 #define ISA_ISR_SERIAL 0x08 /* Read out Serial ID after Reset */ 62 /* Signature delivered after Reset at ISA_ISR_SERIAL (LSB first) */
/linux-4.4.14/drivers/staging/rtl8192u/ieee80211/
H A D	dot11d.c	21 /* Reset to the state as we are just entering a regulatory domain. */ Dot11d_Reset() 128 /* Reset country IE if previous one is gone. */ DOT11D_ScanComplete()
/linux-4.4.14/drivers/reset/
H A D	reset-socfpga.c	5 * Allwinner SoCs Reset Controller driver 166 MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
H A D	reset-zynq.c	4 * Xilinx Zynq Reset controller driver 155 MODULE_DESCRIPTION("Zynq Reset Controller Driver");
H A D	reset-sunxi.c	2 * Allwinner SoCs Reset Controller driver 192 MODULE_DESCRIPTION("Allwinner SoCs Reset Controller Driver");
H A D	reset-lpc18xx.c	2 * Reset driver for NXP LPC18xx/43xx Reset Generation Unit (RGU). 257 MODULE_DESCRIPTION("Reset driver for LPC18xx/43xx RGU");
/linux-4.4.14/drivers/net/phy/
H A D	bcm-cygnus.c	68 /* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */ bcm_cygnus_afe_config() 73 /* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */ bcm_cygnus_afe_config()
H A D	bcm7xxx.c	50 /* Reset R_CAL/RC_CAL Engine */ r_rc_cal_reset() 53 /* Disable Reset R_AL/RC_CAL Engine */ r_rc_cal_reset() 132 /* Reset R_CAL/RC_CAL engine */ bcm7xxx_28nm_d0_afe_config_init() 160 /* Reset R_CAL/RC_CAL engine */ bcm7xxx_28nm_e0_plus_afe_config_init()
H A D	ste10Xp.c	39 /* Software Reset PHY */ ste10Xp_config_init()
/linux-4.4.14/arch/x86/boot/
H A D	pm.c	47 * Reset IGNNE# if asserted in the FPU. 115 /* Reset coprocessor (IGNNE#) */ go_to_protected_mode()
/linux-4.4.14/drivers/clk/mmp/
H A D	clk-apbc.c	23 #define APBC_RST (1 << 2) /* Reset Generation */ 24 #define APBC_POWER (1 << 7) /* Reset Generation */
/linux-4.4.14/arch/powerpc/platforms/85xx/
H A D	ksi8560.c	41 #define KSI8560_CPLD_RCR1 0x30 /* Reset Command Register 1 */ 43 #define KSI8560_CPLD_RCR1_CPUHR 0x80 /* CPU Hard Reset */
/linux-4.4.14/arch/m68k/coldfire/
H A D	sltimers.c	45 /* Reset Slice Timer 1 */ mcfslt_profile_tick() 88 /* Reset Slice Timer 0 */ mcfslt_tick()
H A D	timers.c	75 /* Reset the ColdFire timer */ mcftmr_tick() 163 /* Reset ColdFire timer2 */ coldfire_profile_tick()
H A D	pit.c	102 /* Reset the ColdFire timer */ pit_tick()
/linux-4.4.14/arch/arm/kernel/
H A D	entry-v7m.S	130 .long 0 @ 0 - Reset stack pointer 131 .long __invalid_entry @ 1 - Reset
/linux-4.4.14/drivers/staging/sm750fb/
H A D	ddk750_chip.h	65 * 1 = Reset the memory controller
/linux-4.4.14/drivers/usb/chipidea/
H A D	otg_fsm.h	58 /* A-SE0 to B-Reset */
/linux-4.4.14/drivers/clocksource/
H A D	numachip.c	84 /* Reset timer */ numachip_timer_init()
H A D	timer-u300.c	35 /* Reset OS Timer 32bit (-/W) */ 71 /* Reset DD Timer 32bit (-/W) */ 107 /* Reset GP1 Timer 32bit (-/W) */ 143 /* Reset GP2 Timer 32bit (-/W) */ 286 /* Reset the General Purpose timer 1. */ u300_set_next_event() 408 /* Reset the General Purpose timer 1. */ u300_timer_init_of() 415 /* Reset the General Purpose timer 2 */ u300_timer_init_of()
/linux-4.4.14/drivers/dma/bestcomm/
H A D	fec.c	120 /* Reset the microcode */ bcom_fec_rx_reset() 139 /* Reset the BDs */ bcom_fec_rx_reset() 221 /* Reset the microcode */ bcom_fec_tx_reset() 240 /* Reset the BDs */ bcom_fec_tx_reset()
H A D	gen_bd.c	127 /* Reset the microcode */ bcom_gen_bd_rx_reset() 145 /* Reset the BDs */ bcom_gen_bd_rx_reset() 211 /* Reset the microcode */ bcom_gen_bd_tx_reset() 229 /* Reset the BDs */ bcom_gen_bd_tx_reset()
/linux-4.4.14/arch/c6x/include/asm/
H A D	irq.h	25 * The C64X+ core has 16 IRQ vectors. One each is used by Reset and NMI. Two
/linux-4.4.14/include/uapi/linux/
H A D	watchdog.h	38 #define WDIOF_OVERHEAT 0x0001 /* Reset due to CPU overheat */
/linux-4.4.14/include/net/
H A D	llc_if.h	45 /* Reset reasons, remote entity or local LLC */
/linux-4.4.14/include/linux/fsl/
H A D	guts.h	58 __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */ 62 __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */ 68 __be32 rstcr; /* 0x.00b0 - Reset Control Register */ 73 __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
/linux-4.4.14/arch/mips/lantiq/falcon/
H A D	reset.c	18 /* CPU0 Reset Source Register */
/linux-4.4.14/arch/sh/boards/
H A D	board-secureedge5410.c	45 printk("SnapGear: failed to register IRQ%d for Reset witch\n", eraseconfig_init()
/linux-4.4.14/arch/sh/kernel/cpu/sh5/
H A D	clock-sh5.c	19 /* Clock, Power and Reset Controller */
/linux-4.4.14/arch/sparc/include/asm/
H A D	contregs.h	18 #define AC_M_RESET 0x0700 /* hv Reset Reg */
H A D	fhc.h	29 #define FHC_PREGS_RCS 0x10UL /* FHC Reset Control/Status Register */ 40 #define FHC_CONTROL_FRST 0x00080000 /* Fatal Error Reset Enable */
H A D	sunbpp.h	38 #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
/linux-4.4.14/arch/m68k/sun3/prom/
H A D	misc.c	17 /* Reset and reboot the machine with the command 'bcommand'. */
/linux-4.4.14/arch/mips/lasat/
H A D	reset.c	18 * Reset the LASAT board.
/linux-4.4.14/arch/mips/ralink/
H A D	reset.c	21 /* Reset Control */
/linux-4.4.14/arch/mips/sgi-ip27/
H A D	ip27-reset.c	6 * Reset an IP27.
/linux-4.4.14/arch/mn10300/include/asm/
H A D	reset-regs.h	1 /* MN10300 Reset controller and watchdog timer definitions
/linux-4.4.14/arch/powerpc/boot/
H A D	mpc8xx.c	20 #define MPC8XX_PLPRCR (0x284/4) /* PLL and Reset Control Register */
/linux-4.4.14/arch/blackfin/mach-bf518/include/mach/
H A D	anomaly.h	51 /* Software System Reset Corrupts PLL_LOCKCNT Register */ 57 /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ 87 /* PLL Latches Incorrect Settings During Reset */
/linux-4.4.14/arch/arm/mach-shmobile/
H A D	headsmp.S	20 * Reset vector for secondary CPUs.
/linux-4.4.14/arch/arm/mach-cns3xxx/
H A D	devices.c	69 /* De-Asscer SATA Reset */ cns3xxx_ahci_init()
/linux-4.4.14/arch/arm/mach-ep93xx/include/mach/
H A D	uncompress.h	69 /* Reset the ethernet MAC. */ ethernet_reset()
/linux-4.4.14/arch/arm/mach-gemini/
H A D	board-rut1xx.c	30 .desc = "Reset to defaults",
/linux-4.4.14/include/linux/mfd/syscon/
H A D	atmel-st.h	27 #define AT91_ST_RSTEN BIT(16) /* Reset Enable */
/linux-4.4.14/tools/testing/selftests/powerpc/pmu/ebb/
H A D	back_to_back_ebbs_test.c	45 /* Reset but leave counters frozen */ ebb_callee()
/linux-4.4.14/arch/blackfin/mach-bf527/include/mach/
H A D	anomaly.h	70 /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ 74 /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ 102 /* Reset Vector Must Not Be in SDRAM Memory Space */ 164 /* Software System Reset Corrupts PLL_LOCKCNT Register */ 172 /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ 206 /* PLL Latches Incorrect Settings During Reset */
/linux-4.4.14/drivers/scsi/fnic/
H A D	fnic_trace.c	284 "Number of Device Reset Failures: %lld\n" fnic_get_stats_data() 285 "Number of Device Reset Aborts: %lld\n" fnic_get_stats_data() 286 "Number of Device Reset Timeouts: %lld\n" fnic_get_stats_data() 287 "Number of Device Reset Terminates: %lld\n" fnic_get_stats_data() 289 "Number of FW Reset Completions: %lld\n" fnic_get_stats_data() 290 "Number of FW Reset Failures: %lld\n" fnic_get_stats_data() 291 "Number of Fnic Reset: %lld\n" fnic_get_stats_data() 292 "Number of Fnic Reset Completions: %lld\n" fnic_get_stats_data() 293 "Number of Fnic Reset Failures: %lld\n", fnic_get_stats_data() 357 "Number of Copy WQ Alloc Failures for Device Reset: %lld\n" fnic_get_stats_data()
/linux-4.4.14/drivers/net/ethernet/marvell/
H A D	sky2.h	33 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */ 117 P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */ 121 P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */ 126 P_REL_PCIE_RESET_ASS = 1<<21, /* PCIe Reset Asserted */ 134 P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */ 139 P_GAT_PCIE_RESET_ASS = 1<<5, /* PCIe Reset Asserted */ 166 P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */ 234 PSM_CONFIG_REG1_DIS_PERST = 1<<6, /* Disable Internal PCIe Reset after PSM Goes back to IDLE */ 237 PSM_CONFIG_REG1_EN_PSM_HOT_RST = 1<<3, /* Enable PCIe Hot Reset for PSM */ 238 PSM_CONFIG_REG1_EN_PSM_PERST = 1<<2, /* Enable PCIe Reset Event for PSM */ 250 PSM_CONFIG_REG4_RST_PHY_LINK_DETECT = 1<<0, /* Reset GPHY Link Detect */ 523 GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */ 662 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */ 663 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */ 885 BMU_FIFO_RST = 1<<4, /* Reset FIFO */ 888 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */ 889 BMU_RST_SET = 1<<0, /* Set BMU Reset */ 948 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */ 949 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */ 974 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */ 975 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */ 1036 HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */ 1904 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */ 1905 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */ 1981 HCU_CCSR_WDOG = 1<<24, /* Watchdog Reset */ 1986 HCU_CCSR_AHB_RST = 1<<9, /* Reset AHB bridge */ 1987 HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */ 2014 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */ 2015 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */ 2035 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */ 2036 GMC_RST_SET = 1<<0, /* Set GMAC Reset */ 2063 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */ 2064 GPC_RST_SET = 1<<0, /* Set GPHY Reset */ 2082 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */ 2083 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
H A D	skge.h	371 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */ 372 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */ 380 MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */ 381 MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */ 406 PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */ 407 PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */ 598 MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */ 599 MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */ 634 MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */ 635 MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */ 713 CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */ 714 CSR_DESC_SET = 1<<20, /* Set Reset for Descr */ 715 CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */ 716 CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */ 718 CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */ 720 CSR_SV_RST = 1<<14, /* Reset Supervisor SM */ 722 CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */ 724 CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */ 726 CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */ 777 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */ 778 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */ 1178 PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */ 1870 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */ 1871 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */ 1903 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */ 1904 GMC_RST_SET = 1<<0, /* Set GMAC Reset */ 1931 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */ 1932 GPC_RST_SET = 1<<0, /* Set GPHY Reset */ 1972 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */ 1973 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */ 2173 XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */ 2174 XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */
/linux-4.4.14/drivers/bluetooth/
H A D	btbcm.c	176 BT_ERR("%s: BCM: Reset failed (%d)", hdev->name, err); btbcm_reset() 285 /* Reset */ btbcm_initialize() 340 /* Reset */ btbcm_finalize() 394 /* Reset */ btbcm_setup_patchram() 477 /* Reset */ btbcm_setup_patchram() 517 /* Reset */ btbcm_setup_apple()
/linux-4.4.14/arch/alpha/kernel/
H A D	core_lca.c	136 /* Reset status register to avoid losing errors. */ conf_read() 153 /* Reset error status. */ conf_read() 157 /* Reset machine check. */ conf_read() 173 /* Reset status register to avoid losing errors. */ conf_write() 190 /* Reset error status. */ conf_write() 194 /* Reset machine check. */ conf_write()
H A D	core_apecs.c	136 /* Reset status register to avoid losing errors. */ conf_read() 189 /* Reset error status. */ conf_read() 216 /* Reset status register to avoid losing errors. */ conf_write() 258 /* Reset error status. */ conf_write()
/linux-4.4.14/init/
H A D	initramfs.c	196 Reset enumerator in enum:state 329 next_state = Reset; do_name() 397 next_state = Reset; do_symlink() 409 [Reset] = do_reset, 438 state = Reset; flush_buffer() 498 if (state != Reset) unpack_to_rootfs()
/linux-4.4.14/drivers/usb/gadget/udc/
H A D	at91_udc.h	46 #define AT91_UDP_ENDBUSRES (1 << 12) /* End of Bus Reset Interrupt Status */ 50 #define AT91_UDP_RST_EP 0x28 /* Reset Endpoint Register */
/linux-4.4.14/drivers/iio/humidity/
H A D	si7020.c	41 /* Software Reset */ 126 /* Reset device, loads default settings. */ si7020_probe()
/linux-4.4.14/drivers/infiniband/hw/mthca/
H A D	mthca_catas.c	76 printk(KERN_ERR "mthca %s: Reset failed (%d)\n", catas_reset() 80 mthca_dbg(d, "Reset succeeded\n"); catas_reset()
/linux-4.4.14/drivers/media/dvb-frontends/
H A D	drxd_firm.c	514 /* Reset packet sync bytes in EC_VD ram */ 527 /* Reset packet sync bytes in EC_RS ram */ 595 /* Reset packet sync bytes in EC_VD ram */ 608 /* Reset packet sync bytes in EC_RS ram */ 650 /* Reset packet sync bytes in EC_VD ram */ 663 /* Reset packet sync bytes in EC_RS ram */ 724 /* Reset packet sync bytes in EC_VD ram */ 737 /* Reset packet sync bytes in EC_RS ram */
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb/
H A D	my3126.c	6 /* Port Reset */ my3126_reset() 185 /* Chip Reset */ my3126_phy_reset()
/linux-4.4.14/drivers/net/ethernet/altera/
H A D	altera_msgdma.c	41 /* Reset Rx mSGDMA */ msgdma_reset() 62 /* Reset Tx mSGDMA */ msgdma_reset()
/linux-4.4.14/drivers/platform/x86/
H A D	toshiba_haps.c	120 /* Reset the protection interface */ reset_protection_store() 242 /* Reset the protection on resume */ toshiba_haps_resume()
/linux-4.4.14/drivers/char/hw_random/
H A D	iproc-rng200.c	70 /* Reset RNG and RBG */ iproc_rng200_restart() 140 /* Reset the IDLE timeout */ iproc_rng200_read()
/linux-4.4.14/arch/s390/include/asm/
H A D	tlbflush.h	74 /* Reset TLB flush mask */ __tlb_flush_full() 101 /* Reset TLB flush mask */ __tlb_flush_asce()
/linux-4.4.14/arch/sh/boards/mach-r2d/
H A D	setup.c	287 * RstX = 1 - External Memory Reset: Normal. rts7751r2d_setup() 292 * Rst = 1 - Internal Memory Reset: Normal. rts7751r2d_setup()
/linux-4.4.14/arch/sparc/include/uapi/asm/
H A D	pstate.h	21 #define PSTATE_RED _AC(0x0000000000000020,UL) /* Reset Error Debug. */ 58 #define TSTATE_RED _AC(0x0000000000002000,UL) /* Reset Error Debug.*/
/linux-4.4.14/arch/m32r/include/asm/mappi3/
H A D	mappi3_pld.h	68 * 2: Reset switch side 139 /* Reset Control */
/linux-4.4.14/arch/arm/mach-orion5x/
H A D	wrt350n-v2-setup.c	76 .desc = "Reset Button", 107 MPP3_GPIO, /* Reset Button (0=on) */
/linux-4.4.14/arch/arm/mach-zynq/
H A D	slcr.c	27 #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ 28 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
/linux-4.4.14/sound/oss/
H A D	pas2_midi.c	49 * Reset input and output FIFO pointers pas_midi_open() 97 * Reset FIFO pointers, disable intrs pas_midi_close()
/linux-4.4.14/drivers/usb/usbip/
H A D	usbip_event.c	44 /* Reset the device. */ event_handler()
/linux-4.4.14/drivers/reset/sti/
H A D	reset-stih415.c	52 #define SYSCFG_376 0x130 /* Reset generator 0 control 0 */
H A D	reset-syscfg.h	18 * Reset channel description for a system configuration register based
/linux-4.4.14/drivers/vfio/platform/reset/
H A D	vfio_platform_calxedaxgmac.c	31 #define DRIVER_DESC "Reset support for Calxeda xgmac vfio platform device"
/linux-4.4.14/drivers/isdn/hardware/eicon/
H A D	xdi_msg.h	45 Reset of the board + activation of primary
/linux-4.4.14/drivers/iio/accel/
H A D	mma9551_core.h	28 /* Reset/Suspend/Clear application app masks */
/linux-4.4.14/drivers/input/serio/
H A D	xilinx_ps2.c	33 #define XPS2_SRST_OFFSET 0x00000000 /* Software Reset register */ 41 /* Reset Register Bit Definitions */ 42 #define XPS2_SRST_RESET 0x0000000A /* Software Reset */ 296 /* Reset the PS2 device and abort any current transaction, to make sure xps2_of_probe()
/linux-4.4.14/drivers/net/ethernet/qlogic/qed/
H A D	qed_cxt.h	98 * @brief qed_cxt_mngr_setup - Reset the acquired CIDs
H A D	qed_sp.h	167 * @brief qed_spq_setup - Reset the SPQ to its start state. 216 * @brief qed_eq_setup - Reset the SPQ to its start state. 287 * @brief qed_consq_setup - Reset the ConsQ to its start
/linux-4.4.14/drivers/devfreq/exynos/
H A D	exynos_ppmu.c	65 /* Reset the performance and cycle counters */ busfreq_mon_reset()
/linux-4.4.14/drivers/ata/
H A D	pata_palmld.c	38 { GPIO_NR_PALMLD_IDE_RESET, GPIOF_INIT_LOW, "HDD Reset" },
/linux-4.4.14/drivers/gpu/drm/msm/edp/
H A D	edp_phy.c	48 /* Reset */ msm_edp_phy_ctrl()
/linux-4.4.14/arch/sparc/prom/
H A D	misc_32.c	21 /* Reset and reboot the machine with the command 'bcommand'. */
/linux-4.4.14/arch/x86/platform/geode/
H A D	geos.c	37 .desc = "Reset button",
H A D	net5501.c	40 .desc = "Reset button",
/linux-4.4.14/arch/alpha/oprofile/
H A D	op_model_ev6.c	75 in between one of the widths selectable in hardware. Reset the count
/linux-4.4.14/arch/cris/arch-v32/mach-a3/
H A D	dram_init.S	42 ; Reset phy and start calibration
/linux-4.4.14/arch/powerpc/platforms/83xx/
H A D	mpc832x_mds.c	89 /* Reset the Ethernet PHYs */ mpc832x_sys_setup_arch()
/linux-4.4.14/arch/m68k/68000/
H A D	timers.c	62 /* Reset Timer1 */ hw_tick()
/linux-4.4.14/arch/blackfin/include/asm/
H A D	bfin-global.h	91 extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
/linux-4.4.14/arch/arm/mach-berlin/
H A D	platsmp.c	52 * Reset the CPU, making it to execute the instruction in the reset berlin_boot_secondary()
/linux-4.4.14/drivers/net/wireless/orinoco/
H A D	spectrum_cs.c	73 * Reset the card using configuration registers COR and CCSR. 92 /* Soft-Reset card */ spectrum_reset() 235 /* Reset card */ spectrum_cs_config()
/linux-4.4.14/drivers/phy/
H A D	phy-exynos5250-usb2.c	221 /* Reset */ exynos5250_power_on() 253 /* Reset */ exynos5250_power_on() 273 /* Reset */ exynos5250_power_on()

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