/linux-4.4.14/drivers/gpu/drm/nouveau/ |
H A D | nvc0_fbcon.c | 43 OUT_RING (chan, 1); nvc0_fbcon_fillrect() 48 OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]); nvc0_fbcon_fillrect() 50 OUT_RING (chan, rect->color); nvc0_fbcon_fillrect() 52 OUT_RING (chan, rect->dx); nvc0_fbcon_fillrect() 53 OUT_RING (chan, rect->dy); nvc0_fbcon_fillrect() 54 OUT_RING (chan, rect->dx + rect->width); nvc0_fbcon_fillrect() 55 OUT_RING (chan, rect->dy + rect->height); nvc0_fbcon_fillrect() 58 OUT_RING (chan, 3); nvc0_fbcon_fillrect() 77 OUT_RING (chan, 0); nvc0_fbcon_copyarea() 79 OUT_RING (chan, region->dx); nvc0_fbcon_copyarea() 80 OUT_RING (chan, region->dy); nvc0_fbcon_copyarea() 81 OUT_RING (chan, region->width); nvc0_fbcon_copyarea() 82 OUT_RING (chan, region->height); nvc0_fbcon_copyarea() 84 OUT_RING (chan, 0); nvc0_fbcon_copyarea() 85 OUT_RING (chan, region->sx); nvc0_fbcon_copyarea() 86 OUT_RING (chan, 0); nvc0_fbcon_copyarea() 87 OUT_RING (chan, region->sy); nvc0_fbcon_copyarea() 116 OUT_RING (chan, palette[image->bg_color] | mask); nvc0_fbcon_imageblit() 117 OUT_RING (chan, palette[image->fg_color] | mask); nvc0_fbcon_imageblit() 119 OUT_RING (chan, image->bg_color); nvc0_fbcon_imageblit() 120 OUT_RING (chan, image->fg_color); nvc0_fbcon_imageblit() 123 OUT_RING (chan, image->width); nvc0_fbcon_imageblit() 124 OUT_RING (chan, image->height); nvc0_fbcon_imageblit() 126 OUT_RING (chan, 0); nvc0_fbcon_imageblit() 127 OUT_RING (chan, image->dx); nvc0_fbcon_imageblit() 128 OUT_RING (chan, 0); nvc0_fbcon_imageblit() 129 OUT_RING (chan, image->dy); nvc0_fbcon_imageblit() 199 OUT_RING (chan, nfbdev->twod.handle); nvc0_fbcon_accel_init() 201 OUT_RING (chan, 0); nvc0_fbcon_accel_init() 203 OUT_RING (chan, 1); nvc0_fbcon_accel_init() 205 OUT_RING (chan, 3); nvc0_fbcon_accel_init() 207 OUT_RING (chan, 0x55); nvc0_fbcon_accel_init() 209 OUT_RING (chan, 0); nvc0_fbcon_accel_init() 210 OUT_RING (chan, 1); nvc0_fbcon_accel_init() 211 OUT_RING (chan, 0); nvc0_fbcon_accel_init() 212 OUT_RING (chan, 1); nvc0_fbcon_accel_init() 214 OUT_RING (chan, 4); nvc0_fbcon_accel_init() 215 OUT_RING (chan, format); nvc0_fbcon_accel_init() 217 OUT_RING (chan, 2); nvc0_fbcon_accel_init() 218 OUT_RING (chan, 1); nvc0_fbcon_accel_init() 221 OUT_RING (chan, format); nvc0_fbcon_accel_init() 223 OUT_RING (chan, 1); nvc0_fbcon_accel_init() 225 OUT_RING (chan, 0); nvc0_fbcon_accel_init() 226 OUT_RING (chan, 0); nvc0_fbcon_accel_init() 227 OUT_RING (chan, 1); nvc0_fbcon_accel_init() 229 OUT_RING (chan, 1); nvc0_fbcon_accel_init() 231 OUT_RING (chan, 0); nvc0_fbcon_accel_init() 232 OUT_RING (chan, 1); nvc0_fbcon_accel_init() 233 OUT_RING (chan, 0); nvc0_fbcon_accel_init() 234 OUT_RING (chan, 1); nvc0_fbcon_accel_init() 236 OUT_RING (chan, format); nvc0_fbcon_accel_init() 237 OUT_RING (chan, 1); nvc0_fbcon_accel_init() 238 OUT_RING (chan, 0); nvc0_fbcon_accel_init() 239 OUT_RING (chan, 1); nvc0_fbcon_accel_init() 240 OUT_RING (chan, 0); nvc0_fbcon_accel_init() 241 OUT_RING (chan, info->fix.line_length); nvc0_fbcon_accel_init() 242 OUT_RING (chan, info->var.xres_virtual); nvc0_fbcon_accel_init() 243 OUT_RING (chan, info->var.yres_virtual); nvc0_fbcon_accel_init() 244 OUT_RING (chan, upper_32_bits(fb->vma.offset)); nvc0_fbcon_accel_init() 245 OUT_RING (chan, lower_32_bits(fb->vma.offset)); nvc0_fbcon_accel_init() 247 OUT_RING (chan, format); nvc0_fbcon_accel_init() 248 OUT_RING (chan, 1); nvc0_fbcon_accel_init() 249 OUT_RING (chan, 0); nvc0_fbcon_accel_init() 250 OUT_RING (chan, 1); nvc0_fbcon_accel_init() 251 OUT_RING (chan, 0); nvc0_fbcon_accel_init() 252 OUT_RING (chan, info->fix.line_length); nvc0_fbcon_accel_init() 253 OUT_RING (chan, info->var.xres_virtual); nvc0_fbcon_accel_init() 254 OUT_RING (chan, info->var.yres_virtual); nvc0_fbcon_accel_init() 255 OUT_RING (chan, upper_32_bits(fb->vma.offset)); nvc0_fbcon_accel_init() 256 OUT_RING (chan, lower_32_bits(fb->vma.offset)); nvc0_fbcon_accel_init()
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H A D | nv50_fbcon.c | 43 OUT_RING(chan, 1); nv50_fbcon_fillrect() 48 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); nv50_fbcon_fillrect() 50 OUT_RING(chan, rect->color); nv50_fbcon_fillrect() 52 OUT_RING(chan, rect->dx); nv50_fbcon_fillrect() 53 OUT_RING(chan, rect->dy); nv50_fbcon_fillrect() 54 OUT_RING(chan, rect->dx + rect->width); nv50_fbcon_fillrect() 55 OUT_RING(chan, rect->dy + rect->height); nv50_fbcon_fillrect() 58 OUT_RING(chan, 3); nv50_fbcon_fillrect() 77 OUT_RING(chan, 0); nv50_fbcon_copyarea() 79 OUT_RING(chan, region->dx); nv50_fbcon_copyarea() 80 OUT_RING(chan, region->dy); nv50_fbcon_copyarea() 81 OUT_RING(chan, region->width); nv50_fbcon_copyarea() 82 OUT_RING(chan, region->height); nv50_fbcon_copyarea() 84 OUT_RING(chan, 0); nv50_fbcon_copyarea() 85 OUT_RING(chan, region->sx); nv50_fbcon_copyarea() 86 OUT_RING(chan, 0); nv50_fbcon_copyarea() 87 OUT_RING(chan, region->sy); nv50_fbcon_copyarea() 116 OUT_RING(chan, palette[image->bg_color] | mask); nv50_fbcon_imageblit() 117 OUT_RING(chan, palette[image->fg_color] | mask); nv50_fbcon_imageblit() 119 OUT_RING(chan, image->bg_color); nv50_fbcon_imageblit() 120 OUT_RING(chan, image->fg_color); nv50_fbcon_imageblit() 123 OUT_RING(chan, image->width); nv50_fbcon_imageblit() 124 OUT_RING(chan, image->height); nv50_fbcon_imageblit() 126 OUT_RING(chan, 0); nv50_fbcon_imageblit() 127 OUT_RING(chan, image->dx); nv50_fbcon_imageblit() 128 OUT_RING(chan, 0); nv50_fbcon_imageblit() 129 OUT_RING(chan, image->dy); nv50_fbcon_imageblit() 198 OUT_RING(chan, nfbdev->twod.handle); nv50_fbcon_accel_init() 200 OUT_RING(chan, chan->vram.handle); nv50_fbcon_accel_init() 201 OUT_RING(chan, chan->vram.handle); nv50_fbcon_accel_init() 202 OUT_RING(chan, chan->vram.handle); nv50_fbcon_accel_init() 204 OUT_RING(chan, 0); nv50_fbcon_accel_init() 206 OUT_RING(chan, 1); nv50_fbcon_accel_init() 208 OUT_RING(chan, 3); nv50_fbcon_accel_init() 210 OUT_RING(chan, 0x55); nv50_fbcon_accel_init() 212 OUT_RING(chan, 0); nv50_fbcon_accel_init() 213 OUT_RING(chan, 1); nv50_fbcon_accel_init() 214 OUT_RING(chan, 0); nv50_fbcon_accel_init() 215 OUT_RING(chan, 1); nv50_fbcon_accel_init() 217 OUT_RING(chan, 4); nv50_fbcon_accel_init() 218 OUT_RING(chan, format); nv50_fbcon_accel_init() 220 OUT_RING(chan, 2); nv50_fbcon_accel_init() 221 OUT_RING(chan, 1); nv50_fbcon_accel_init() 223 OUT_RING(chan, format); nv50_fbcon_accel_init() 225 OUT_RING(chan, 1); nv50_fbcon_accel_init() 227 OUT_RING(chan, 0); nv50_fbcon_accel_init() 228 OUT_RING(chan, 0); nv50_fbcon_accel_init() 229 OUT_RING(chan, 1); nv50_fbcon_accel_init() 231 OUT_RING(chan, 1); nv50_fbcon_accel_init() 233 OUT_RING(chan, 0); nv50_fbcon_accel_init() 234 OUT_RING(chan, 1); nv50_fbcon_accel_init() 235 OUT_RING(chan, 0); nv50_fbcon_accel_init() 236 OUT_RING(chan, 1); nv50_fbcon_accel_init() 238 OUT_RING(chan, format); nv50_fbcon_accel_init() 239 OUT_RING(chan, 1); nv50_fbcon_accel_init() 241 OUT_RING(chan, info->fix.line_length); nv50_fbcon_accel_init() 242 OUT_RING(chan, info->var.xres_virtual); nv50_fbcon_accel_init() 243 OUT_RING(chan, info->var.yres_virtual); nv50_fbcon_accel_init() 244 OUT_RING(chan, upper_32_bits(fb->vma.offset)); nv50_fbcon_accel_init() 245 OUT_RING(chan, lower_32_bits(fb->vma.offset)); nv50_fbcon_accel_init() 247 OUT_RING(chan, format); nv50_fbcon_accel_init() 248 OUT_RING(chan, 1); nv50_fbcon_accel_init() 250 OUT_RING(chan, info->fix.line_length); nv50_fbcon_accel_init() 251 OUT_RING(chan, info->var.xres_virtual); nv50_fbcon_accel_init() 252 OUT_RING(chan, info->var.yres_virtual); nv50_fbcon_accel_init() 253 OUT_RING(chan, upper_32_bits(fb->vma.offset)); nv50_fbcon_accel_init() 254 OUT_RING(chan, lower_32_bits(fb->vma.offset)); nv50_fbcon_accel_init()
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H A D | nv04_fbcon.c | 42 OUT_RING(chan, (region->sy << 16) | region->sx); nv04_fbcon_copyarea() 43 OUT_RING(chan, (region->dy << 16) | region->dx); nv04_fbcon_copyarea() 44 OUT_RING(chan, (region->height << 16) | region->width); nv04_fbcon_copyarea() 62 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3); nv04_fbcon_fillrect() 66 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); nv04_fbcon_fillrect() 68 OUT_RING(chan, rect->color); nv04_fbcon_fillrect() 70 OUT_RING(chan, (rect->dx << 16) | rect->dy); nv04_fbcon_fillrect() 71 OUT_RING(chan, (rect->width << 16) | rect->height); nv04_fbcon_fillrect() 109 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); nv04_fbcon_imageblit() 110 OUT_RING(chan, ((image->dy + image->height) << 16) | nv04_fbcon_imageblit() 112 OUT_RING(chan, bg); nv04_fbcon_imageblit() 113 OUT_RING(chan, fg); nv04_fbcon_imageblit() 114 OUT_RING(chan, (image->height << 16) | width); nv04_fbcon_imageblit() 115 OUT_RING(chan, (image->height << 16) | image->width); nv04_fbcon_imageblit() 116 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); nv04_fbcon_imageblit() 212 OUT_RING(chan, nfbdev->surf2d.handle); nv04_fbcon_accel_init() 214 OUT_RING(chan, chan->vram.handle); nv04_fbcon_accel_init() 215 OUT_RING(chan, chan->vram.handle); nv04_fbcon_accel_init() 217 OUT_RING(chan, surface_fmt); nv04_fbcon_accel_init() 218 OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); nv04_fbcon_accel_init() 219 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); nv04_fbcon_accel_init() 220 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); nv04_fbcon_accel_init() 223 OUT_RING(chan, nfbdev->rop.handle); nv04_fbcon_accel_init() 225 OUT_RING(chan, 0x55); nv04_fbcon_accel_init() 228 OUT_RING(chan, nfbdev->patt.handle); nv04_fbcon_accel_init() 230 OUT_RING(chan, pattern_fmt); nv04_fbcon_accel_init() 232 OUT_RING(chan, 2); nv04_fbcon_accel_init() 234 OUT_RING(chan, 1); nv04_fbcon_accel_init() 236 OUT_RING(chan, 0); nv04_fbcon_accel_init() 237 OUT_RING(chan, 1); nv04_fbcon_accel_init() 238 OUT_RING(chan, ~0); nv04_fbcon_accel_init() 239 OUT_RING(chan, ~0); nv04_fbcon_accel_init() 240 OUT_RING(chan, ~0); nv04_fbcon_accel_init() 241 OUT_RING(chan, ~0); nv04_fbcon_accel_init() 244 OUT_RING(chan, nfbdev->clip.handle); nv04_fbcon_accel_init() 246 OUT_RING(chan, 0); nv04_fbcon_accel_init() 247 OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual); nv04_fbcon_accel_init() 250 OUT_RING(chan, nfbdev->blit.handle); nv04_fbcon_accel_init() 252 OUT_RING(chan, nfbdev->surf2d.handle); nv04_fbcon_accel_init() 254 OUT_RING(chan, 3); nv04_fbcon_accel_init() 257 OUT_RING(chan, 0); nv04_fbcon_accel_init() 258 OUT_RING(chan, 1); nv04_fbcon_accel_init() 259 OUT_RING(chan, 2); nv04_fbcon_accel_init() 263 OUT_RING(chan, nfbdev->gdi.handle); nv04_fbcon_accel_init() 265 OUT_RING(chan, nfbdev->surf2d.handle); nv04_fbcon_accel_init() 267 OUT_RING(chan, nfbdev->patt.handle); nv04_fbcon_accel_init() 268 OUT_RING(chan, nfbdev->rop.handle); nv04_fbcon_accel_init() 270 OUT_RING(chan, 1); nv04_fbcon_accel_init() 272 OUT_RING(chan, rect_fmt); nv04_fbcon_accel_init() 274 OUT_RING(chan, 3); nv04_fbcon_accel_init()
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H A D | nvc0_fence.c | 37 OUT_RING (chan, upper_32_bits(virtual)); nvc0_fence_emit32() 38 OUT_RING (chan, lower_32_bits(virtual)); nvc0_fence_emit32() 39 OUT_RING (chan, sequence); nvc0_fence_emit32() 40 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); nvc0_fence_emit32() 41 OUT_RING (chan, 0x00000000); nvc0_fence_emit32() 53 OUT_RING (chan, upper_32_bits(virtual)); nvc0_fence_sync32() 54 OUT_RING (chan, lower_32_bits(virtual)); nvc0_fence_sync32() 55 OUT_RING (chan, sequence); nvc0_fence_sync32() 56 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL | nvc0_fence_sync32()
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H A D | nouveau_bo.c | 682 OUT_RING (chan, handle & 0x0000ffff); nve0_bo_move_init() 696 OUT_RING (chan, upper_32_bits(node->vma[0].offset)); nve0_bo_move_copy() 697 OUT_RING (chan, lower_32_bits(node->vma[0].offset)); nve0_bo_move_copy() 698 OUT_RING (chan, upper_32_bits(node->vma[1].offset)); nve0_bo_move_copy() 699 OUT_RING (chan, lower_32_bits(node->vma[1].offset)); nve0_bo_move_copy() 700 OUT_RING (chan, PAGE_SIZE); nve0_bo_move_copy() 701 OUT_RING (chan, PAGE_SIZE); nve0_bo_move_copy() 702 OUT_RING (chan, PAGE_SIZE); nve0_bo_move_copy() 703 OUT_RING (chan, new_mem->num_pages); nve0_bo_move_copy() 715 OUT_RING (chan, handle); nvc0_bo_move_init() 739 OUT_RING (chan, upper_32_bits(src_offset)); nvc0_bo_move_copy() 740 OUT_RING (chan, lower_32_bits(src_offset)); nvc0_bo_move_copy() 741 OUT_RING (chan, upper_32_bits(dst_offset)); nvc0_bo_move_copy() 742 OUT_RING (chan, lower_32_bits(dst_offset)); nvc0_bo_move_copy() 743 OUT_RING (chan, PAGE_SIZE); nvc0_bo_move_copy() 744 OUT_RING (chan, PAGE_SIZE); nvc0_bo_move_copy() 745 OUT_RING (chan, PAGE_SIZE); nvc0_bo_move_copy() 746 OUT_RING (chan, line_count); nvc0_bo_move_copy() 748 OUT_RING (chan, 0x00000110); nvc0_bo_move_copy() 777 OUT_RING (chan, upper_32_bits(dst_offset)); nvc0_bo_move_m2mf() 778 OUT_RING (chan, lower_32_bits(dst_offset)); nvc0_bo_move_m2mf() 780 OUT_RING (chan, upper_32_bits(src_offset)); nvc0_bo_move_m2mf() 781 OUT_RING (chan, lower_32_bits(src_offset)); nvc0_bo_move_m2mf() 782 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ nvc0_bo_move_m2mf() 783 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ nvc0_bo_move_m2mf() 784 OUT_RING (chan, PAGE_SIZE); /* line_length */ nvc0_bo_move_m2mf() 785 OUT_RING (chan, line_count); nvc0_bo_move_m2mf() 787 OUT_RING (chan, 0x00100110); nvc0_bo_move_m2mf() 816 OUT_RING (chan, upper_32_bits(src_offset)); nva3_bo_move_copy() 817 OUT_RING (chan, lower_32_bits(src_offset)); nva3_bo_move_copy() 818 OUT_RING (chan, upper_32_bits(dst_offset)); nva3_bo_move_copy() 819 OUT_RING (chan, lower_32_bits(dst_offset)); nva3_bo_move_copy() 820 OUT_RING (chan, PAGE_SIZE); nva3_bo_move_copy() 821 OUT_RING (chan, PAGE_SIZE); nva3_bo_move_copy() 822 OUT_RING (chan, PAGE_SIZE); nva3_bo_move_copy() 823 OUT_RING (chan, line_count); nva3_bo_move_copy() 825 OUT_RING (chan, 0x00000110); nva3_bo_move_copy() 843 OUT_RING (chan, upper_32_bits(node->vma[0].offset)); nv98_bo_move_exec() 844 OUT_RING (chan, lower_32_bits(node->vma[0].offset)); nv98_bo_move_exec() 845 OUT_RING (chan, upper_32_bits(node->vma[1].offset)); nv98_bo_move_exec() 846 OUT_RING (chan, lower_32_bits(node->vma[1].offset)); nv98_bo_move_exec() 847 OUT_RING (chan, 0x00000000 /* COPY */); nv98_bo_move_exec() 848 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT); nv98_bo_move_exec() 861 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT); nv84_bo_move_exec() 862 OUT_RING (chan, upper_32_bits(node->vma[0].offset)); nv84_bo_move_exec() 863 OUT_RING (chan, lower_32_bits(node->vma[0].offset)); nv84_bo_move_exec() 864 OUT_RING (chan, upper_32_bits(node->vma[1].offset)); nv84_bo_move_exec() 865 OUT_RING (chan, lower_32_bits(node->vma[1].offset)); nv84_bo_move_exec() 866 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); nv84_bo_move_exec() 877 OUT_RING (chan, handle); nv50_bo_move_init() 879 OUT_RING (chan, chan->drm->ntfy.handle); nv50_bo_move_init() 880 OUT_RING (chan, chan->vram.handle); nv50_bo_move_init() 881 OUT_RING (chan, chan->vram.handle); nv50_bo_move_init() 912 OUT_RING (chan, 0); nv50_bo_move_m2mf() 913 OUT_RING (chan, 0); nv50_bo_move_m2mf() 914 OUT_RING (chan, stride); nv50_bo_move_m2mf() 915 OUT_RING (chan, height); nv50_bo_move_m2mf() 916 OUT_RING (chan, 1); nv50_bo_move_m2mf() 917 OUT_RING (chan, 0); nv50_bo_move_m2mf() 918 OUT_RING (chan, 0); nv50_bo_move_m2mf() 921 OUT_RING (chan, 1); nv50_bo_move_m2mf() 925 OUT_RING (chan, 0); nv50_bo_move_m2mf() 926 OUT_RING (chan, 0); nv50_bo_move_m2mf() 927 OUT_RING (chan, stride); nv50_bo_move_m2mf() 928 OUT_RING (chan, height); nv50_bo_move_m2mf() 929 OUT_RING (chan, 1); nv50_bo_move_m2mf() 930 OUT_RING (chan, 0); nv50_bo_move_m2mf() 931 OUT_RING (chan, 0); nv50_bo_move_m2mf() 934 OUT_RING (chan, 1); nv50_bo_move_m2mf() 938 OUT_RING (chan, upper_32_bits(src_offset)); nv50_bo_move_m2mf() 939 OUT_RING (chan, upper_32_bits(dst_offset)); nv50_bo_move_m2mf() 941 OUT_RING (chan, lower_32_bits(src_offset)); nv50_bo_move_m2mf() 942 OUT_RING (chan, lower_32_bits(dst_offset)); nv50_bo_move_m2mf() 943 OUT_RING (chan, stride); nv50_bo_move_m2mf() 944 OUT_RING (chan, stride); nv50_bo_move_m2mf() 945 OUT_RING (chan, stride); nv50_bo_move_m2mf() 946 OUT_RING (chan, height); nv50_bo_move_m2mf() 947 OUT_RING (chan, 0x00000101); nv50_bo_move_m2mf() 948 OUT_RING (chan, 0x00000000); nv50_bo_move_m2mf() 950 OUT_RING (chan, 0); nv50_bo_move_m2mf() 966 OUT_RING (chan, handle); nv04_bo_move_init() 968 OUT_RING (chan, chan->drm->ntfy.handle); nv04_bo_move_init() 997 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem)); nv04_bo_move_m2mf() 998 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem)); nv04_bo_move_m2mf() 1010 OUT_RING (chan, src_offset); nv04_bo_move_m2mf() 1011 OUT_RING (chan, dst_offset); nv04_bo_move_m2mf() 1012 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ nv04_bo_move_m2mf() 1013 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ nv04_bo_move_m2mf() 1014 OUT_RING (chan, PAGE_SIZE); /* line_length */ nv04_bo_move_m2mf() 1015 OUT_RING (chan, line_count); nv04_bo_move_m2mf() 1016 OUT_RING (chan, 0x00000101); nv04_bo_move_m2mf() 1017 OUT_RING (chan, 0x00000000); nv04_bo_move_m2mf() 1019 OUT_RING (chan, 0); nv04_bo_move_m2mf()
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H A D | nv17_fence.c | 53 OUT_RING (prev, fctx->sema.handle); nv17_fence_sync() 54 OUT_RING (prev, 0); nv17_fence_sync() 55 OUT_RING (prev, value + 0); nv17_fence_sync() 56 OUT_RING (prev, value + 1); nv17_fence_sync() 62 OUT_RING (chan, fctx->sema.handle); nv17_fence_sync() 63 OUT_RING (chan, 0); nv17_fence_sync() 64 OUT_RING (chan, value + 1); nv17_fence_sync() 65 OUT_RING (chan, value + 2); nv17_fence_sync()
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H A D | nv84_fence.c | 44 OUT_RING (chan, chan->vram.handle); nv84_fence_emit32() 46 OUT_RING (chan, upper_32_bits(virtual)); nv84_fence_emit32() 47 OUT_RING (chan, lower_32_bits(virtual)); nv84_fence_emit32() 48 OUT_RING (chan, sequence); nv84_fence_emit32() 49 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); nv84_fence_emit32() 50 OUT_RING (chan, 0x00000000); nv84_fence_emit32() 62 OUT_RING (chan, chan->vram.handle); nv84_fence_sync32() 64 OUT_RING (chan, upper_32_bits(virtual)); nv84_fence_sync32() 65 OUT_RING (chan, lower_32_bits(virtual)); nv84_fence_sync32() 66 OUT_RING (chan, sequence); nv84_fence_sync32() 67 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL); nv84_fence_sync32()
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H A D | nouveau_dma.h | 102 OUT_RING(struct nouveau_channel *chan, int data) OUT_RING() function 113 OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); BEGIN_NV04() 119 OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd); BEGIN_NI04() 125 OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); BEGIN_NVC0() 131 OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2)); BEGIN_NIC0() 137 OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); BEGIN_IMC0()
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H A D | nv50_display.c | 591 OUT_RING (chan, NvEvoSema0 + nv_crtc->index); nv50_display_flip_next() 592 OUT_RING (chan, sync->addr ^ 0x10); nv50_display_flip_next() 594 OUT_RING (chan, sync->data + 1); nv50_display_flip_next() 596 OUT_RING (chan, sync->addr); nv50_display_flip_next() 597 OUT_RING (chan, sync->data); nv50_display_flip_next() 606 OUT_RING (chan, chan->vram.handle); nv50_display_flip_next() 608 OUT_RING (chan, upper_32_bits(addr ^ 0x10)); nv50_display_flip_next() 609 OUT_RING (chan, lower_32_bits(addr ^ 0x10)); nv50_display_flip_next() 610 OUT_RING (chan, sync->data + 1); nv50_display_flip_next() 611 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); nv50_display_flip_next() 613 OUT_RING (chan, upper_32_bits(addr)); nv50_display_flip_next() 614 OUT_RING (chan, lower_32_bits(addr)); nv50_display_flip_next() 615 OUT_RING (chan, sync->data); nv50_display_flip_next() 616 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL); nv50_display_flip_next() 625 OUT_RING (chan, upper_32_bits(addr ^ 0x10)); nv50_display_flip_next() 626 OUT_RING (chan, lower_32_bits(addr ^ 0x10)); nv50_display_flip_next() 627 OUT_RING (chan, sync->data + 1); nv50_display_flip_next() 628 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG | nv50_display_flip_next() 631 OUT_RING (chan, upper_32_bits(addr)); nv50_display_flip_next() 632 OUT_RING (chan, lower_32_bits(addr)); nv50_display_flip_next() 633 OUT_RING (chan, sync->data); nv50_display_flip_next() 634 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL | nv50_display_flip_next()
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H A D | nv04_fence.c | 44 OUT_RING (chan, fence->base.seqno); nv04_fence_emit()
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H A D | nv10_fence.c | 36 OUT_RING (chan, fence->base.seqno); nv10_fence_emit()
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H A D | nouveau_display.c | 695 OUT_RING (chan, 0x00000000); nouveau_page_flip_emit() 784 OUT_RING (chan, 0); nouveau_crtc_page_flip() 786 OUT_RING (chan, head); nouveau_crtc_page_flip() 788 OUT_RING (chan, 0); nouveau_crtc_page_flip() 790 OUT_RING (chan, 0); nouveau_crtc_page_flip()
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H A D | nouveau_gem.c | 782 OUT_RING(chan, (nvbo->bo.offset + push[i].offset) | 2); nouveau_gem_ioctl_pushbuf() 783 OUT_RING(chan, 0); nouveau_gem_ioctl_pushbuf() 816 OUT_RING(chan, 0x20000000 | nouveau_gem_ioctl_pushbuf() 818 OUT_RING(chan, 0); nouveau_gem_ioctl_pushbuf() 820 OUT_RING(chan, 0); nouveau_gem_ioctl_pushbuf()
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H A D | nouveau_chan.c | 376 OUT_RING(chan, 0x00000000); nouveau_channel_init() 391 OUT_RING (chan, chan->nvsw.handle); nouveau_channel_init()
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H A D | nouveau_dma.c | 227 OUT_RING(chan, chan->push.vma.offset | 0x20000000); nouveau_dma_wait()
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H A D | nouveau_drm.c | 250 OUT_RING (drm->channel, NVDRM_NVSW); nouveau_accel_init() 254 OUT_RING (drm->channel, 0x001f0000); nouveau_accel_init()
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/linux-4.4.14/drivers/gpu/drm/radeon/ |
H A D | r600_blit.c | 95 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_render_target() 96 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_render_target() 97 OUT_RING(gpu_addr >> 8); set_render_target() 98 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); set_render_target() 99 OUT_RING(2 << 0); set_render_target() 102 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_render_target() 103 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_render_target() 104 OUT_RING(gpu_addr >> 8); set_render_target() 107 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_render_target() 108 OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_render_target() 109 OUT_RING((pitch << 0) | (slice << 10)); set_render_target() 111 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_render_target() 112 OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_render_target() 113 OUT_RING(0); set_render_target() 115 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_render_target() 116 OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_render_target() 117 OUT_RING(cb_color_info); set_render_target() 119 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_render_target() 120 OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_render_target() 121 OUT_RING(0); set_render_target() 123 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_render_target() 124 OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_render_target() 125 OUT_RING(0); set_render_target() 127 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_render_target() 128 OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_render_target() 129 OUT_RING(0); set_render_target() 148 OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3)); cp_set_surface_sync() 149 OUT_RING(sync_type); cp_set_surface_sync() 150 OUT_RING(cp_coher_size); cp_set_surface_sync() 151 OUT_RING((mc_addr >> 8)); cp_set_surface_sync() 152 OUT_RING(10); /* poll interval */ cp_set_surface_sync() 185 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_shaders() 186 OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_shaders() 187 OUT_RING(gpu_addr >> 8); set_shaders() 189 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_shaders() 190 OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_shaders() 191 OUT_RING(sq_pgm_resources); set_shaders() 193 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_shaders() 194 OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_shaders() 195 OUT_RING(0); set_shaders() 198 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_shaders() 199 OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_shaders() 200 OUT_RING((gpu_addr + 256) >> 8); set_shaders() 202 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_shaders() 203 OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_shaders() 204 OUT_RING(sq_pgm_resources | (1 << 28)); set_shaders() 206 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_shaders() 207 OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_shaders() 208 OUT_RING(2); set_shaders() 210 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); set_shaders() 211 OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_shaders() 212 OUT_RING(0); set_shaders() 232 OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); set_vtx_resource() 233 OUT_RING(0x460); set_vtx_resource() 234 OUT_RING(gpu_addr & 0xffffffff); set_vtx_resource() 235 OUT_RING(48 - 1); set_vtx_resource() 236 OUT_RING(sq_vtx_constant_word2); set_vtx_resource() 237 OUT_RING(1 << 0); set_vtx_resource() 238 OUT_RING(0); set_vtx_resource() 239 OUT_RING(0); set_vtx_resource() 240 OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30); set_vtx_resource() 280 OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); set_tex_resource() 281 OUT_RING(0); set_tex_resource() 282 OUT_RING(sq_tex_resource_word0); set_tex_resource() 283 OUT_RING(sq_tex_resource_word1); set_tex_resource() 284 OUT_RING(gpu_addr >> 8); set_tex_resource() 285 OUT_RING(gpu_addr >> 8); set_tex_resource() 286 OUT_RING(sq_tex_resource_word4); set_tex_resource() 287 OUT_RING(0); set_tex_resource() 288 OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30); set_tex_resource() 300 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); set_scissors() 301 OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_scissors() 302 OUT_RING((x1 << 0) | (y1 << 16)); set_scissors() 303 OUT_RING((x2 << 0) | (y2 << 16)); set_scissors() 305 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); set_scissors() 306 OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_scissors() 307 OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); set_scissors() 308 OUT_RING((x2 << 0) | (y2 << 16)); set_scissors() 310 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); set_scissors() 311 OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); set_scissors() 312 OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); set_scissors() 313 OUT_RING((x2 << 0) | (y2 << 16)); set_scissors() 324 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); draw_auto() 325 OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2); draw_auto() 326 OUT_RING(DI_PT_RECTLIST); draw_auto() 328 OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); draw_auto() 330 OUT_RING((2 << 2) | DI_INDEX_SIZE_16_BIT); draw_auto() 332 OUT_RING(DI_INDEX_SIZE_16_BIT); draw_auto() 335 OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); draw_auto() 336 OUT_RING(1); draw_auto() 338 OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1)); draw_auto() 339 OUT_RING(3); draw_auto() 340 OUT_RING(DI_SRC_SEL_AUTO_INDEX); draw_auto() 504 OUT_RING(r7xx_default_state[i]); set_default_state() 508 OUT_RING(r6xx_default_state[i]); set_default_state() 510 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); set_default_state() 511 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); set_default_state() 513 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6)); set_default_state() 514 OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2); set_default_state() 515 OUT_RING(sq_config); set_default_state() 516 OUT_RING(sq_gpr_resource_mgmt_1); set_default_state() 517 OUT_RING(sq_gpr_resource_mgmt_2); set_default_state() 518 OUT_RING(sq_thread_resource_mgmt); set_default_state() 519 OUT_RING(sq_stack_resource_mgmt_1); set_default_state() 520 OUT_RING(sq_stack_resource_mgmt_2); set_default_state() 578 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); r600_done_blit_copy() 579 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); r600_done_blit_copy() 581 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); r600_done_blit_copy() 582 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); r600_done_blit_copy() 583 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); r600_done_blit_copy()
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H A D | radeon_state.c | 458 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); radeon_emit_clip_rect() 459 OUT_RING((box->y1 << 16) | box->x1); radeon_emit_clip_rect() 460 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); radeon_emit_clip_rect() 461 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); radeon_emit_clip_rect() 490 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); radeon_emit_state() 491 OUT_RING(ctx->pp_misc); radeon_emit_state() 492 OUT_RING(ctx->pp_fog_color); radeon_emit_state() 493 OUT_RING(ctx->re_solid_color); radeon_emit_state() 494 OUT_RING(ctx->rb3d_blendcntl); radeon_emit_state() 495 OUT_RING(ctx->rb3d_depthoffset); radeon_emit_state() 496 OUT_RING(ctx->rb3d_depthpitch); radeon_emit_state() 497 OUT_RING(ctx->rb3d_zstencilcntl); radeon_emit_state() 498 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2)); radeon_emit_state() 499 OUT_RING(ctx->pp_cntl); radeon_emit_state() 500 OUT_RING(ctx->rb3d_cntl); radeon_emit_state() 501 OUT_RING(ctx->rb3d_coloroffset); radeon_emit_state() 502 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); radeon_emit_state() 503 OUT_RING(ctx->rb3d_colorpitch); radeon_emit_state() 509 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0)); radeon_emit_state() 510 OUT_RING(ctx->se_coord_fmt); radeon_emit_state() 516 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1)); radeon_emit_state() 517 OUT_RING(ctx->re_line_pattern); radeon_emit_state() 518 OUT_RING(ctx->re_line_state); radeon_emit_state() 519 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0)); radeon_emit_state() 520 OUT_RING(ctx->se_line_width); radeon_emit_state() 526 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0)); radeon_emit_state() 527 OUT_RING(ctx->pp_lum_matrix); radeon_emit_state() 528 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1)); radeon_emit_state() 529 OUT_RING(ctx->pp_rot_matrix_0); radeon_emit_state() 530 OUT_RING(ctx->pp_rot_matrix_1); radeon_emit_state() 536 OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2)); radeon_emit_state() 537 OUT_RING(ctx->rb3d_stencilrefmask); radeon_emit_state() 538 OUT_RING(ctx->rb3d_ropcntl); radeon_emit_state() 539 OUT_RING(ctx->rb3d_planemask); radeon_emit_state() 545 OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5)); radeon_emit_state() 546 OUT_RING(ctx->se_vport_xscale); radeon_emit_state() 547 OUT_RING(ctx->se_vport_xoffset); radeon_emit_state() 548 OUT_RING(ctx->se_vport_yscale); radeon_emit_state() 549 OUT_RING(ctx->se_vport_yoffset); radeon_emit_state() 550 OUT_RING(ctx->se_vport_zscale); radeon_emit_state() 551 OUT_RING(ctx->se_vport_zoffset); radeon_emit_state() 557 OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0)); radeon_emit_state() 558 OUT_RING(ctx->se_cntl); radeon_emit_state() 559 OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0)); radeon_emit_state() 560 OUT_RING(ctx->se_cntl_status); radeon_emit_state() 566 OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0)); radeon_emit_state() 567 OUT_RING(ctx->re_misc); radeon_emit_state() 579 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5)); radeon_emit_state() 580 OUT_RING(tex[0].pp_txfilter); radeon_emit_state() 581 OUT_RING(tex[0].pp_txformat); radeon_emit_state() 582 OUT_RING(tex[0].pp_txoffset); radeon_emit_state() 583 OUT_RING(tex[0].pp_txcblend); radeon_emit_state() 584 OUT_RING(tex[0].pp_txablend); radeon_emit_state() 585 OUT_RING(tex[0].pp_tfactor); radeon_emit_state() 586 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0)); radeon_emit_state() 587 OUT_RING(tex[0].pp_border_color); radeon_emit_state() 599 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5)); radeon_emit_state() 600 OUT_RING(tex[1].pp_txfilter); radeon_emit_state() 601 OUT_RING(tex[1].pp_txformat); radeon_emit_state() 602 OUT_RING(tex[1].pp_txoffset); radeon_emit_state() 603 OUT_RING(tex[1].pp_txcblend); radeon_emit_state() 604 OUT_RING(tex[1].pp_txablend); radeon_emit_state() 605 OUT_RING(tex[1].pp_tfactor); radeon_emit_state() 606 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0)); radeon_emit_state() 607 OUT_RING(tex[1].pp_border_color); radeon_emit_state() 619 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5)); radeon_emit_state() 620 OUT_RING(tex[2].pp_txfilter); radeon_emit_state() 621 OUT_RING(tex[2].pp_txformat); radeon_emit_state() 622 OUT_RING(tex[2].pp_txoffset); radeon_emit_state() 623 OUT_RING(tex[2].pp_txcblend); radeon_emit_state() 624 OUT_RING(tex[2].pp_txablend); radeon_emit_state() 625 OUT_RING(tex[2].pp_tfactor); radeon_emit_state() 626 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0)); radeon_emit_state() 627 OUT_RING(tex[2].pp_border_color); radeon_emit_state() 644 OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1)); radeon_emit_state2() 645 OUT_RING(state->context2.se_zbias_factor); radeon_emit_state2() 646 OUT_RING(state->context2.se_zbias_constant); radeon_emit_state2() 790 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); radeon_clear_box() 791 OUT_RING(0xffffffff); radeon_clear_box() 796 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); radeon_clear_box() 797 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | radeon_clear_box() 804 OUT_RING(dev_priv->front_pitch_offset); radeon_clear_box() 806 OUT_RING(dev_priv->back_pitch_offset); radeon_clear_box() 809 OUT_RING(color); radeon_clear_box() 811 OUT_RING((x << 16) | y); radeon_clear_box() 812 OUT_RING((w << 16) | h); radeon_clear_box() 918 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); radeon_cp_dispatch_clear() 919 OUT_RING(clear->color_mask); radeon_cp_dispatch_clear() 939 OUT_RING(CP_PACKET3 radeon_cp_dispatch_clear() 941 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | radeon_cp_dispatch_clear() 949 OUT_RING(dev_priv->front_pitch_offset); radeon_cp_dispatch_clear() 950 OUT_RING(clear->clear_color); radeon_cp_dispatch_clear() 952 OUT_RING((x << 16) | y); radeon_cp_dispatch_clear() 953 OUT_RING((w << 16) | h); radeon_cp_dispatch_clear() 961 OUT_RING(CP_PACKET3 radeon_cp_dispatch_clear() 963 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | radeon_cp_dispatch_clear() 971 OUT_RING(dev_priv->back_pitch_offset); radeon_cp_dispatch_clear() 972 OUT_RING(clear->clear_color); radeon_cp_dispatch_clear() 974 OUT_RING((x << 16) | y); radeon_cp_dispatch_clear() 975 OUT_RING((w << 16) | h); radeon_cp_dispatch_clear() 1068 OUT_RING(CP_PACKET3 radeon_cp_dispatch_clear() 1071 OUT_RING(tileoffset * 8); radeon_cp_dispatch_clear() 1073 OUT_RING(nrtilesx + 4); radeon_cp_dispatch_clear() 1075 OUT_RING(clearmask); radeon_cp_dispatch_clear() 1091 OUT_RING(CP_PACKET3 radeon_cp_dispatch_clear() 1098 OUT_RING(tileoffset * 16); radeon_cp_dispatch_clear() 1100 OUT_RING(nrtilesx + 1); radeon_cp_dispatch_clear() 1102 OUT_RING(clearmask); radeon_cp_dispatch_clear() 1119 OUT_RING(CP_PACKET3 radeon_cp_dispatch_clear() 1121 OUT_RING(tileoffset * 128); radeon_cp_dispatch_clear() 1123 OUT_RING(nrtilesx + 4); radeon_cp_dispatch_clear() 1125 OUT_RING(clearmask); radeon_cp_dispatch_clear() 1142 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2)); radeon_cp_dispatch_clear() 1143 OUT_RING(0x0); /* First tile */ radeon_cp_dispatch_clear() 1144 OUT_RING(0x3cc0); radeon_cp_dispatch_clear() 1145 OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f); radeon_cp_dispatch_clear() 1259 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12)); radeon_cp_dispatch_clear() 1260 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | radeon_cp_dispatch_clear() 1263 OUT_RING(depth_boxes[i].ui[CLEAR_X1]); radeon_cp_dispatch_clear() 1264 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); radeon_cp_dispatch_clear() 1265 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); radeon_cp_dispatch_clear() 1266 OUT_RING(0x3f800000); radeon_cp_dispatch_clear() 1267 OUT_RING(depth_boxes[i].ui[CLEAR_X1]); radeon_cp_dispatch_clear() 1268 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); radeon_cp_dispatch_clear() 1269 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); radeon_cp_dispatch_clear() 1270 OUT_RING(0x3f800000); radeon_cp_dispatch_clear() 1271 OUT_RING(depth_boxes[i].ui[CLEAR_X2]); radeon_cp_dispatch_clear() 1272 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); radeon_cp_dispatch_clear() 1273 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); radeon_cp_dispatch_clear() 1274 OUT_RING(0x3f800000); radeon_cp_dispatch_clear() 1308 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1)); radeon_cp_dispatch_clear() 1309 OUT_RING(0x00000000); radeon_cp_dispatch_clear() 1310 OUT_RING(rb3d_cntl); radeon_cp_dispatch_clear() 1331 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13)); radeon_cp_dispatch_clear() 1332 OUT_RING(RADEON_VTX_Z_PRESENT | radeon_cp_dispatch_clear() 1334 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | radeon_cp_dispatch_clear() 1340 OUT_RING(depth_boxes[i].ui[CLEAR_X1]); radeon_cp_dispatch_clear() 1341 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); radeon_cp_dispatch_clear() 1342 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); radeon_cp_dispatch_clear() 1343 OUT_RING(0x0); radeon_cp_dispatch_clear() 1345 OUT_RING(depth_boxes[i].ui[CLEAR_X1]); radeon_cp_dispatch_clear() 1346 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); radeon_cp_dispatch_clear() 1347 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); radeon_cp_dispatch_clear() 1348 OUT_RING(0x0); radeon_cp_dispatch_clear() 1350 OUT_RING(depth_boxes[i].ui[CLEAR_X2]); radeon_cp_dispatch_clear() 1351 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); radeon_cp_dispatch_clear() 1352 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); radeon_cp_dispatch_clear() 1353 OUT_RING(0x0); radeon_cp_dispatch_clear() 1408 OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0)); radeon_cp_dispatch_swap() 1409 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | radeon_cp_dispatch_swap() 1420 OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1)); radeon_cp_dispatch_swap() 1422 OUT_RING(dev_priv->back_pitch_offset); radeon_cp_dispatch_swap() 1423 OUT_RING(dev_priv->front_pitch_offset); radeon_cp_dispatch_swap() 1425 OUT_RING(dev_priv->front_pitch_offset); radeon_cp_dispatch_swap() 1426 OUT_RING(dev_priv->back_pitch_offset); radeon_cp_dispatch_swap() 1429 OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2)); radeon_cp_dispatch_swap() 1430 OUT_RING((x << 16) | y); radeon_cp_dispatch_swap() 1431 OUT_RING((x << 16) | y); radeon_cp_dispatch_swap() 1432 OUT_RING((w << 16) | h); radeon_cp_dispatch_swap() 1563 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3)); radeon_cp_dispatch_vertex() 1564 OUT_RING(offset); radeon_cp_dispatch_vertex() 1565 OUT_RING(numverts); radeon_cp_dispatch_vertex() 1566 OUT_RING(prim->vc_format); radeon_cp_dispatch_vertex() 1567 OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST | radeon_cp_dispatch_vertex() 1628 OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1)); radeon_cp_dispatch_indirect() 1629 OUT_RING(offset); radeon_cp_dispatch_indirect() 1630 OUT_RING(dwords); radeon_cp_dispatch_indirect() 1900 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5)); radeon_cp_dispatch_texture() 1901 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | radeon_cp_dispatch_texture() 1909 OUT_RING((spitch << 22) | (offset >> 10)); radeon_cp_dispatch_texture() 1910 OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10))); radeon_cp_dispatch_texture() 1911 OUT_RING(0); radeon_cp_dispatch_texture() 1912 OUT_RING((image->x << 16) | (image->y % 2048)); radeon_cp_dispatch_texture() 1913 OUT_RING((image->width << 16) | height); radeon_cp_dispatch_texture() 1948 OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0)); radeon_cp_dispatch_stipple() 1949 OUT_RING(0x00000000); radeon_cp_dispatch_stipple() 1951 OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31)); radeon_cp_dispatch_stipple() 1953 OUT_RING(stipple[i]); radeon_cp_dispatch_stipple() 2193 OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0)); radeon_do_init_pageflip() 2194 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) | radeon_do_init_pageflip() 2196 OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0)); radeon_do_init_pageflip() 2197 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) | radeon_do_init_pageflip() 2663 OUT_RING(CP_PACKET0(reg, (sz - 1))); radeon_emit_packets() 2680 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); radeon_emit_scalars() 2681 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); radeon_emit_scalars() 2682 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); radeon_emit_scalars() 2700 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); radeon_emit_scalars2() 2701 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); radeon_emit_scalars2() 2702 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); radeon_emit_scalars2() 2719 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); radeon_emit_vectors() 2720 OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); radeon_emit_vectors() 2721 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); radeon_emit_vectors() 2743 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); radeon_emit_veclinear() 2744 OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); radeon_emit_veclinear() 2745 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); radeon_emit_veclinear()
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H A D | r300_cmdbuf.c | 75 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); r300_emit_cliprects() 107 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | r300_emit_cliprects() 109 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | r300_emit_cliprects() 121 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); r300_emit_cliprects() 122 OUT_RING(0); r300_emit_cliprects() 123 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK); r300_emit_cliprects() 148 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); r300_emit_cliprects() 149 OUT_RING(R300_RB3D_DC_FLUSH); r300_emit_cliprects() 152 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); r300_emit_cliprects() 153 OUT_RING(RADEON_WAIT_3D_IDLECLEAN); r300_emit_cliprects() 336 OUT_RING(CP_PACKET0(reg, sz - 1)); r300_emit_carefully_checked_packet0() 380 OUT_RING(CP_PACKET0(reg, sz - 1)); r300_emit_packet0() 411 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); r300_emit_vpu() 412 OUT_RING(R300_RB3D_DC_FLUSH); r300_emit_vpu() 413 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); r300_emit_vpu() 414 OUT_RING(RADEON_WAIT_3D_IDLECLEAN); r300_emit_vpu() 415 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); r300_emit_vpu() 416 OUT_RING(0); r300_emit_vpu() 423 OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1)); r300_emit_vpu() 428 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); r300_emit_vpu() 429 OUT_RING(0); r300_emit_vpu() 448 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); r300_emit_clear() 449 OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | r300_emit_clear() 455 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); r300_emit_clear() 456 OUT_RING(R300_RB3D_DC_FLUSH); r300_emit_clear() 457 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); r300_emit_clear() 458 OUT_RING(RADEON_WAIT_3D_IDLECLEAN); r300_emit_clear() 526 OUT_RING(header); r300_emit_3d_load_vbpntr() 812 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); r300_pacify() 813 OUT_RING(cache_z); r300_pacify() 817 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); r300_pacify() 818 OUT_RING(cache_3d); r300_pacify() 822 OUT_RING(CP_PACKET0(R300_TX_INVALTAGS, 0)); r300_pacify() 823 OUT_RING(0); r300_pacify() 827 OUT_RING(CP_PACKET0(R300_RB3D_AARESOLVE_CTL, 0)); r300_pacify() 828 OUT_RING(0); r300_pacify() 831 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); r300_pacify() 832 OUT_RING(RADEON_WAIT_3D_IDLECLEAN); r300_pacify() 836 OUT_RING(CP_PACKET0(R300_DSTCACHE_CTLSTAT, 0)); r300_pacify() 837 OUT_RING(cache_2d); r300_pacify() 838 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); r300_pacify() 839 OUT_RING(RADEON_WAIT_2D_IDLECLEAN | r300_pacify() 897 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); r300_cmd_wait() 898 OUT_RING(wait_until); r300_cmd_wait() 955 OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) ); r300_scratch() 956 OUT_RING( dev_priv->scratch_ages[header.scratch.reg] ); r300_scratch() 998 OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1)); r300_emit_r500fp() 1099 OUT_RING(RADEON_CP_PACKET2); r300_do_cp_cmdbuf()
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H A D | radeon_drv.h | 1930 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1931 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1936 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1937 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1942 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1943 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1949 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1950 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1955 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1956 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1958 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1959 OUT_RING(R300_RB3D_DC_FLUSH); \ 1965 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1966 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1968 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1969 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \ 1975 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1976 OUT_RING(RADEON_RB3D_ZC_FLUSH); \ 1978 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1979 OUT_RING(R300_ZC_FLUSH); \ 1985 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1986 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 1988 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1989 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 2025 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 2026 OUT_RING( age ); \ 2030 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 2031 OUT_RING( age ); \ 2035 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 2036 OUT_RING( age ); \ 2040 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2041 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2042 OUT_RING(age); \ 2046 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2047 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2048 OUT_RING(age); \ 2052 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2053 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2054 OUT_RING(age); \ 2103 #define OUT_RING( x ) do { \ macro 2105 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 2113 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 2114 OUT_RING( val ); \
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H A D | r600_cp.c | 2313 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); r600_do_cp_idle() 2314 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); r600_do_cp_idle() 2316 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); r600_do_cp_idle() 2317 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); r600_do_cp_idle() 2318 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); r600_do_cp_idle() 2335 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); r600_do_cp_start() 2336 OUT_RING(0x00000001); r600_do_cp_start() 2338 OUT_RING(0x00000003); r600_do_cp_start() 2340 OUT_RING(0x00000000); r600_do_cp_start() 2341 OUT_RING((dev_priv->r600_max_hw_contexts - 1)); r600_do_cp_start() 2342 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1)); r600_do_cp_start() 2343 OUT_RING(0x00000000); r600_do_cp_start() 2344 OUT_RING(0x00000000); r600_do_cp_start() 2407 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); r600_cp_dispatch_indirect() 2408 OUT_RING((offset & 0xfffffffc)); r600_cp_dispatch_indirect() 2409 OUT_RING((upper_32_bits(offset) & 0xff)); r600_cp_dispatch_indirect() 2410 OUT_RING(dwords); r600_cp_dispatch_indirect()
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H A D | radeon_cp.c | 619 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1)); radeon_do_cp_start() 620 OUT_RING(5); /* scratch reg 5 */ radeon_do_cp_start() 621 OUT_RING(0xdeadbeef); radeon_do_cp_start() 628 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); radeon_do_cp_start() 629 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | radeon_do_cp_start() 669 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); radeon_do_cp_stop() 670 OUT_RING(R300_RB3D_DC_FINISH); radeon_do_cp_stop()
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/linux-4.4.14/drivers/gpu/drm/r128/ |
H A D | r128_state.c | 49 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3)); r128_emit_clip_rects() 50 OUT_RING(boxes[0].x1); r128_emit_clip_rects() 51 OUT_RING(boxes[0].x2 - 1); r128_emit_clip_rects() 52 OUT_RING(boxes[0].y1); r128_emit_clip_rects() 53 OUT_RING(boxes[0].y2 - 1); r128_emit_clip_rects() 58 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3)); r128_emit_clip_rects() 59 OUT_RING(boxes[1].x1); r128_emit_clip_rects() 60 OUT_RING(boxes[1].x2 - 1); r128_emit_clip_rects() 61 OUT_RING(boxes[1].y1); r128_emit_clip_rects() 62 OUT_RING(boxes[1].y2 - 1); r128_emit_clip_rects() 67 OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3)); r128_emit_clip_rects() 68 OUT_RING(boxes[2].x1); r128_emit_clip_rects() 69 OUT_RING(boxes[2].x2 - 1); r128_emit_clip_rects() 70 OUT_RING(boxes[2].y1); r128_emit_clip_rects() 71 OUT_RING(boxes[2].y2 - 1); r128_emit_clip_rects() 76 OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0)); r128_emit_clip_rects() 77 OUT_RING(aux_sc_cntl); r128_emit_clip_rects() 91 OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0)); r128_emit_core() 92 OUT_RING(ctx->scale_3d_cntl); r128_emit_core() 106 OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11)); r128_emit_context() 107 OUT_RING(ctx->dst_pitch_offset_c); r128_emit_context() 108 OUT_RING(ctx->dp_gui_master_cntl_c); r128_emit_context() 109 OUT_RING(ctx->sc_top_left_c); r128_emit_context() 110 OUT_RING(ctx->sc_bottom_right_c); r128_emit_context() 111 OUT_RING(ctx->z_offset_c); r128_emit_context() 112 OUT_RING(ctx->z_pitch_c); r128_emit_context() 113 OUT_RING(ctx->z_sten_cntl_c); r128_emit_context() 114 OUT_RING(ctx->tex_cntl_c); r128_emit_context() 115 OUT_RING(ctx->misc_3d_state_cntl_reg); r128_emit_context() 116 OUT_RING(ctx->texture_clr_cmp_clr_c); r128_emit_context() 117 OUT_RING(ctx->texture_clr_cmp_msk_c); r128_emit_context() 118 OUT_RING(ctx->fog_color_c); r128_emit_context() 132 OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP)); r128_emit_setup() 133 OUT_RING(ctx->setup_cntl); r128_emit_setup() 134 OUT_RING(ctx->pm4_vc_fpu_setup); r128_emit_setup() 148 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0)); r128_emit_masks() 149 OUT_RING(ctx->dp_write_mask); r128_emit_masks() 151 OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1)); r128_emit_masks() 152 OUT_RING(ctx->sten_ref_mask_c); r128_emit_masks() 153 OUT_RING(ctx->plane_3d_mask_c); r128_emit_masks() 167 OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0)); r128_emit_window() 168 OUT_RING(ctx->window_xy_offset); r128_emit_window() 184 OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C, r128_emit_tex0() 186 OUT_RING(tex->tex_cntl); r128_emit_tex0() 187 OUT_RING(tex->tex_combine_cntl); r128_emit_tex0() 188 OUT_RING(ctx->tex_size_pitch_c); r128_emit_tex0() 190 OUT_RING(tex->tex_offset[i]); r128_emit_tex0() 192 OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1)); r128_emit_tex0() 193 OUT_RING(ctx->constant_color_c); r128_emit_tex0() 194 OUT_RING(tex->tex_border_color); r128_emit_tex0() 209 OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS)); r128_emit_tex1() 210 OUT_RING(tex->tex_cntl); r128_emit_tex1() 211 OUT_RING(tex->tex_combine_cntl); r128_emit_tex1() 213 OUT_RING(tex->tex_offset[i]); r128_emit_tex1() 215 OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0)); r128_emit_tex1() 216 OUT_RING(tex->tex_border_color); r128_emit_tex1() 304 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); r128_clear_box() 305 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | r128_clear_box() 312 OUT_RING((pitch << 21) | (offset >> 5)); r128_clear_box() 313 OUT_RING(color); r128_clear_box() 315 OUT_RING((x << 16) | y); r128_clear_box() 316 OUT_RING((w << 16) | h); r128_clear_box() 386 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0)); r128_cce_dispatch_clear() 387 OUT_RING(clear->color_mask); r128_cce_dispatch_clear() 395 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); r128_cce_dispatch_clear() 396 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | r128_cce_dispatch_clear() 404 OUT_RING(dev_priv->front_pitch_offset_c); r128_cce_dispatch_clear() 405 OUT_RING(clear->clear_color); r128_cce_dispatch_clear() 407 OUT_RING((x << 16) | y); r128_cce_dispatch_clear() 408 OUT_RING((w << 16) | h); r128_cce_dispatch_clear() 416 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); r128_cce_dispatch_clear() 417 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | r128_cce_dispatch_clear() 425 OUT_RING(dev_priv->back_pitch_offset_c); r128_cce_dispatch_clear() 426 OUT_RING(clear->clear_color); r128_cce_dispatch_clear() 428 OUT_RING((x << 16) | y); r128_cce_dispatch_clear() 429 OUT_RING((w << 16) | h); r128_cce_dispatch_clear() 437 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); r128_cce_dispatch_clear() 438 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | r128_cce_dispatch_clear() 446 OUT_RING(dev_priv->depth_pitch_offset_c); r128_cce_dispatch_clear() 447 OUT_RING(clear->clear_depth); r128_cce_dispatch_clear() 449 OUT_RING((x << 16) | y); r128_cce_dispatch_clear() 450 OUT_RING((w << 16) | h); r128_cce_dispatch_clear() 481 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); r128_cce_dispatch_swap() 482 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | r128_cce_dispatch_swap() 495 OUT_RING(dev_priv->back_pitch_offset_c); r128_cce_dispatch_swap() 496 OUT_RING(dev_priv->front_pitch_offset_c); r128_cce_dispatch_swap() 498 OUT_RING(dev_priv->front_pitch_offset_c); r128_cce_dispatch_swap() 499 OUT_RING(dev_priv->back_pitch_offset_c); r128_cce_dispatch_swap() 502 OUT_RING((x << 16) | y); r128_cce_dispatch_swap() 503 OUT_RING((x << 16) | y); r128_cce_dispatch_swap() 504 OUT_RING((w << 16) | h); r128_cce_dispatch_swap() 517 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); r128_cce_dispatch_swap() 518 OUT_RING(dev_priv->sarea_priv->last_frame); r128_cce_dispatch_swap() 539 OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0)); r128_cce_dispatch_flip() 542 OUT_RING(dev_priv->back_offset); r128_cce_dispatch_flip() 544 OUT_RING(dev_priv->front_offset); r128_cce_dispatch_flip() 558 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); r128_cce_dispatch_flip() 559 OUT_RING(dev_priv->sarea_priv->last_frame); r128_cce_dispatch_flip() 597 OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3)); r128_cce_dispatch_vertex() 598 OUT_RING(offset); r128_cce_dispatch_vertex() 599 OUT_RING(size); r128_cce_dispatch_vertex() 600 OUT_RING(format); r128_cce_dispatch_vertex() 601 OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | r128_cce_dispatch_vertex() 616 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); r128_cce_dispatch_vertex() 617 OUT_RING(buf_priv->age); r128_cce_dispatch_vertex() 661 OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1)); r128_cce_dispatch_indirect() 662 OUT_RING(offset); r128_cce_dispatch_indirect() 663 OUT_RING(dwords); r128_cce_dispatch_indirect() 674 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); r128_cce_dispatch_indirect() 675 OUT_RING(buf_priv->age); r128_cce_dispatch_indirect() 755 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); r128_cce_dispatch_indices() 756 OUT_RING(buf_priv->age); r128_cce_dispatch_indices() 815 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); r128_cce_dispatch_blit() 816 OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI); r128_cce_dispatch_blit() 868 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); r128_cce_dispatch_blit() 869 OUT_RING(R128_PC_FLUSH_GUI); r128_cce_dispatch_blit() 920 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); r128_cce_dispatch_write_span() 921 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | r128_cce_dispatch_write_span() 929 OUT_RING(dev_priv->depth_pitch_offset_c); r128_cce_dispatch_write_span() 930 OUT_RING(buffer[i]); r128_cce_dispatch_write_span() 932 OUT_RING((x << 16) | y); r128_cce_dispatch_write_span() 933 OUT_RING((1 << 16) | 1); r128_cce_dispatch_write_span() 944 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); r128_cce_dispatch_write_span() 945 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | r128_cce_dispatch_write_span() 953 OUT_RING(dev_priv->depth_pitch_offset_c); r128_cce_dispatch_write_span() 954 OUT_RING(buffer[i]); r128_cce_dispatch_write_span() 956 OUT_RING((x << 16) | y); r128_cce_dispatch_write_span() 957 OUT_RING((1 << 16) | 1); r128_cce_dispatch_write_span() 1026 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); r128_cce_dispatch_write_pixels() 1027 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | r128_cce_dispatch_write_pixels() 1035 OUT_RING(dev_priv->depth_pitch_offset_c); r128_cce_dispatch_write_pixels() 1036 OUT_RING(buffer[i]); r128_cce_dispatch_write_pixels() 1038 OUT_RING((x[i] << 16) | y[i]); r128_cce_dispatch_write_pixels() 1039 OUT_RING((1 << 16) | 1); r128_cce_dispatch_write_pixels() 1050 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); r128_cce_dispatch_write_pixels() 1051 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | r128_cce_dispatch_write_pixels() 1059 OUT_RING(dev_priv->depth_pitch_offset_c); r128_cce_dispatch_write_pixels() 1060 OUT_RING(buffer[i]); r128_cce_dispatch_write_pixels() 1062 OUT_RING((x[i] << 16) | y[i]); r128_cce_dispatch_write_pixels() 1063 OUT_RING((1 << 16) | 1); r128_cce_dispatch_write_pixels() 1095 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); r128_cce_dispatch_read_span() 1096 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | r128_cce_dispatch_read_span() 1105 OUT_RING(dev_priv->depth_pitch_offset_c); r128_cce_dispatch_read_span() 1106 OUT_RING(dev_priv->span_pitch_offset_c); r128_cce_dispatch_read_span() 1108 OUT_RING((x << 16) | y); r128_cce_dispatch_read_span() 1109 OUT_RING((0 << 16) | 0); r128_cce_dispatch_read_span() 1110 OUT_RING((count << 16) | 1); r128_cce_dispatch_read_span() 1157 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); r128_cce_dispatch_read_pixels() 1158 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | r128_cce_dispatch_read_pixels() 1167 OUT_RING(dev_priv->depth_pitch_offset_c); r128_cce_dispatch_read_pixels() 1168 OUT_RING(dev_priv->span_pitch_offset_c); r128_cce_dispatch_read_pixels() 1170 OUT_RING((x[i] << 16) | y[i]); r128_cce_dispatch_read_pixels() 1171 OUT_RING((i << 16) | 0); r128_cce_dispatch_read_pixels() 1172 OUT_RING((1 << 16) | 1); r128_cce_dispatch_read_pixels() 1196 OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31)); r128_cce_dispatch_stipple() 1198 OUT_RING(stipple[i]); r128_cce_dispatch_stipple()
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H A D | r128_drv.h | 466 OUT_RING(CCE_PACKET0(R128_WAIT_UNTIL, 0)); \ 467 OUT_RING(R128_EVENT_CRTC_OFFSET); \ 525 #define OUT_RING(x) do { \ macro 527 DRM_INFO(" OUT_RING( 0x%08x ) at 0x%x\n", \
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/linux-4.4.14/drivers/gpu/drm/i810/ |
H A D | i810_dma.c | 465 OUT_RING(GFX_OP_COLOR_FACTOR); i810EmitContextVerified() 466 OUT_RING(code[I810_CTXREG_CF1]); i810EmitContextVerified() 468 OUT_RING(GFX_OP_STIPPLE); i810EmitContextVerified() 469 OUT_RING(code[I810_CTXREG_ST1]); i810EmitContextVerified() 476 OUT_RING(tmp); i810EmitContextVerified() 483 OUT_RING(0); i810EmitContextVerified() 497 OUT_RING(GFX_OP_MAP_INFO); i810EmitTexVerified() 498 OUT_RING(code[I810_TEXREG_MI1]); i810EmitTexVerified() 499 OUT_RING(code[I810_TEXREG_MI2]); i810EmitTexVerified() 500 OUT_RING(code[I810_TEXREG_MI3]); i810EmitTexVerified() 507 OUT_RING(tmp); i810EmitTexVerified() 514 OUT_RING(0); i810EmitTexVerified() 532 OUT_RING(CMD_OP_DESTBUFFER_INFO); i810EmitDestVerified() 533 OUT_RING(tmp); i810EmitDestVerified() 540 OUT_RING(CMD_OP_Z_BUFFER_INFO); i810EmitDestVerified() 541 OUT_RING(dev_priv->zi1); i810EmitDestVerified() 543 OUT_RING(GFX_OP_DESTBUFFER_VARS); i810EmitDestVerified() 544 OUT_RING(code[I810_DESTREG_DV1]); i810EmitDestVerified() 546 OUT_RING(GFX_OP_DRAWRECT_INFO); i810EmitDestVerified() 547 OUT_RING(code[I810_DESTREG_DR1]); i810EmitDestVerified() 548 OUT_RING(code[I810_DESTREG_DR2]); i810EmitDestVerified() 549 OUT_RING(code[I810_DESTREG_DR3]); i810EmitDestVerified() 550 OUT_RING(code[I810_DESTREG_DR4]); i810EmitDestVerified() 551 OUT_RING(0); i810EmitDestVerified() 629 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); i810_dma_dispatch_clear() 630 OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); i810_dma_dispatch_clear() 631 OUT_RING((height << 16) | width); i810_dma_dispatch_clear() 632 OUT_RING(start); i810_dma_dispatch_clear() 633 OUT_RING(clear_color); i810_dma_dispatch_clear() 634 OUT_RING(0); i810_dma_dispatch_clear() 640 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); i810_dma_dispatch_clear() 641 OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); i810_dma_dispatch_clear() 642 OUT_RING((height << 16) | width); i810_dma_dispatch_clear() 643 OUT_RING(dev_priv->back_offset + start); i810_dma_dispatch_clear() 644 OUT_RING(clear_color); i810_dma_dispatch_clear() 645 OUT_RING(0); i810_dma_dispatch_clear() 651 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); i810_dma_dispatch_clear() 652 OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); i810_dma_dispatch_clear() 653 OUT_RING((height << 16) | width); i810_dma_dispatch_clear() 654 OUT_RING(dev_priv->depth_offset + start); i810_dma_dispatch_clear() 655 OUT_RING(clear_zval); i810_dma_dispatch_clear() 656 OUT_RING(0); i810_dma_dispatch_clear() 692 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4); i810_dma_dispatch_swap() 693 OUT_RING(pitch | (0xCC << 16)); i810_dma_dispatch_swap() 694 OUT_RING((h << 16) | (w * cpp)); i810_dma_dispatch_swap() 696 OUT_RING(dev_priv->front_offset + start); i810_dma_dispatch_swap() 698 OUT_RING(dev_priv->back_offset + start); i810_dma_dispatch_swap() 699 OUT_RING(pitch); i810_dma_dispatch_swap() 701 OUT_RING(dev_priv->back_offset + start); i810_dma_dispatch_swap() 703 OUT_RING(dev_priv->front_offset + start); i810_dma_dispatch_swap() 750 OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR | i810_dma_dispatch_vertex() 752 OUT_RING(GFX_OP_SCISSOR_INFO); i810_dma_dispatch_vertex() 753 OUT_RING(box[i].x1 | (box[i].y1 << 16)); i810_dma_dispatch_vertex() 754 OUT_RING((box[i].x2 - i810_dma_dispatch_vertex() 760 OUT_RING(CMD_OP_BATCH_BUFFER); i810_dma_dispatch_vertex() 761 OUT_RING(start | BB1_PROTECTED); i810_dma_dispatch_vertex() 762 OUT_RING(start + used - 4); i810_dma_dispatch_vertex() 763 OUT_RING(0); i810_dma_dispatch_vertex() 776 OUT_RING(CMD_STORE_DWORD_IDX); i810_dma_dispatch_vertex() 777 OUT_RING(20); i810_dma_dispatch_vertex() 778 OUT_RING(dev_priv->counter); i810_dma_dispatch_vertex() 779 OUT_RING(CMD_STORE_DWORD_IDX); i810_dma_dispatch_vertex() 780 OUT_RING(buf_priv->my_use_idx); i810_dma_dispatch_vertex() 781 OUT_RING(I810_BUF_FREE); i810_dma_dispatch_vertex() 782 OUT_RING(CMD_REPORT_HEAD); i810_dma_dispatch_vertex() 783 OUT_RING(0); i810_dma_dispatch_vertex() 801 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); i810_dma_dispatch_flip() 802 OUT_RING(0); i810_dma_dispatch_flip() 810 OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ ); i810_dma_dispatch_flip() 812 OUT_RING(dev_priv->back_offset); i810_dma_dispatch_flip() 815 OUT_RING(dev_priv->front_offset); i810_dma_dispatch_flip() 818 OUT_RING(0); i810_dma_dispatch_flip() 822 OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP); i810_dma_dispatch_flip() 823 OUT_RING(0); i810_dma_dispatch_flip() 842 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); i810_dma_quiescent() 843 OUT_RING(CMD_REPORT_HEAD); i810_dma_quiescent() 844 OUT_RING(0); i810_dma_quiescent() 845 OUT_RING(0); i810_dma_quiescent() 861 OUT_RING(CMD_REPORT_HEAD); i810_flush_queue() 862 OUT_RING(0); i810_flush_queue() 1068 OUT_RING(CMD_OP_BATCH_BUFFER); i810_dma_dispatch_mc() 1069 OUT_RING(start | BB1_PROTECTED); i810_dma_dispatch_mc() 1070 OUT_RING(start + used - 4); i810_dma_dispatch_mc() 1071 OUT_RING(0); i810_dma_dispatch_mc() 1075 OUT_RING(CMD_STORE_DWORD_IDX); i810_dma_dispatch_mc() 1076 OUT_RING(buf_priv->my_use_idx); i810_dma_dispatch_mc() 1077 OUT_RING(I810_BUF_FREE); i810_dma_dispatch_mc() 1078 OUT_RING(0); i810_dma_dispatch_mc() 1080 OUT_RING(CMD_STORE_DWORD_IDX); i810_dma_dispatch_mc() 1081 OUT_RING(16); i810_dma_dispatch_mc() 1082 OUT_RING(last_render); i810_dma_dispatch_mc() 1083 OUT_RING(0); i810_dma_dispatch_mc()
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H A D | i810_drv.h | 165 #define OUT_RING(n) do { \ macro 167 DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
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/linux-4.4.14/drivers/gpu/drm/msm/adreno/ |
H A D | adreno_gpu.c | 141 OUT_RING(ring, submit->cmd[i].iova); adreno_submit() 142 OUT_RING(ring, submit->cmd[i].size); adreno_submit() 156 OUT_RING(ring, submit->fence); adreno_submit() 164 OUT_RING(ring, HLSQ_FLUSH); adreno_submit() 167 OUT_RING(ring, 0x00000000); adreno_submit() 171 OUT_RING(ring, CACHE_FLUSH_TS); adreno_submit() 172 OUT_RING(ring, rbmemptr(adreno_gpu, fence)); adreno_submit() 173 OUT_RING(ring, submit->fence); adreno_submit() 177 OUT_RING(ring, 0x80000000); adreno_submit() 185 OUT_RING(ring, 0x00000000); adreno_submit() 187 OUT_RING(ring, 0x80000000); adreno_submit() 194 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG)); adreno_submit() 195 OUT_RING(ring, 0x00000000); adreno_submit()
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H A D | a4xx_gpu.c | 115 OUT_RING(ring, 0x000003f7); a4xx_me_init() 116 OUT_RING(ring, 0x00000000); a4xx_me_init() 117 OUT_RING(ring, 0x00000000); a4xx_me_init() 118 OUT_RING(ring, 0x00000000); a4xx_me_init() 119 OUT_RING(ring, 0x00000080); a4xx_me_init() 120 OUT_RING(ring, 0x00000100); a4xx_me_init() 121 OUT_RING(ring, 0x00000180); a4xx_me_init() 122 OUT_RING(ring, 0x00006600); a4xx_me_init() 123 OUT_RING(ring, 0x00000150); a4xx_me_init() 124 OUT_RING(ring, 0x0000014e); a4xx_me_init() 125 OUT_RING(ring, 0x00000154); a4xx_me_init() 126 OUT_RING(ring, 0x00000001); a4xx_me_init() 127 OUT_RING(ring, 0x00000000); a4xx_me_init() 128 OUT_RING(ring, 0x00000000); a4xx_me_init() 129 OUT_RING(ring, 0x00000000); a4xx_me_init() 130 OUT_RING(ring, 0x00000000); a4xx_me_init() 131 OUT_RING(ring, 0x00000000); a4xx_me_init()
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H A D | a3xx_gpu.c | 49 OUT_RING(ring, 0x000003f7); a3xx_me_init() 50 OUT_RING(ring, 0x00000000); a3xx_me_init() 51 OUT_RING(ring, 0x00000000); a3xx_me_init() 52 OUT_RING(ring, 0x00000000); a3xx_me_init() 53 OUT_RING(ring, 0x00000080); a3xx_me_init() 54 OUT_RING(ring, 0x00000100); a3xx_me_init() 55 OUT_RING(ring, 0x00000180); a3xx_me_init() 56 OUT_RING(ring, 0x00006600); a3xx_me_init() 57 OUT_RING(ring, 0x00000150); a3xx_me_init() 58 OUT_RING(ring, 0x0000014e); a3xx_me_init() 59 OUT_RING(ring, 0x00000154); a3xx_me_init() 60 OUT_RING(ring, 0x00000001); a3xx_me_init() 61 OUT_RING(ring, 0x00000000); a3xx_me_init() 62 OUT_RING(ring, 0x00000000); a3xx_me_init() 63 OUT_RING(ring, 0x00000000); a3xx_me_init() 64 OUT_RING(ring, 0x00000000); a3xx_me_init() 65 OUT_RING(ring, 0x00000000); a3xx_me_init()
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H A D | adreno_gpu.h | 257 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); OUT_PKT0() 265 OUT_RING(ring, CP_TYPE2_PKT); OUT_PKT2() 272 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); OUT_PKT3()
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/linux-4.4.14/drivers/video/fbdev/intelfb/ |
H A D | intelfbhw.c | 1552 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE); do_flush() 1553 OUT_RING(MI_NOOP); do_flush() 1690 OUT_RING(br00); intelfbhw_do_fillrect() 1691 OUT_RING(br13); intelfbhw_do_fillrect() 1692 OUT_RING(br14); intelfbhw_do_fillrect() 1693 OUT_RING(br09); intelfbhw_do_fillrect() 1694 OUT_RING(br16); intelfbhw_do_fillrect() 1695 OUT_RING(MI_NOOP); intelfbhw_do_fillrect() 1739 OUT_RING(br00); intelfbhw_do_bitblt() 1740 OUT_RING(br13); intelfbhw_do_bitblt() 1741 OUT_RING(br22); intelfbhw_do_bitblt() 1742 OUT_RING(br23); intelfbhw_do_bitblt() 1743 OUT_RING(br09); intelfbhw_do_bitblt() 1744 OUT_RING(br26); intelfbhw_do_bitblt() 1745 OUT_RING(br11); intelfbhw_do_bitblt() 1746 OUT_RING(br12); intelfbhw_do_bitblt() 1808 OUT_RING(br00); intelfbhw_do_drawglyph() 1809 OUT_RING(br13); intelfbhw_do_drawglyph() 1810 OUT_RING(br22); intelfbhw_do_drawglyph() 1811 OUT_RING(br23); intelfbhw_do_drawglyph() 1812 OUT_RING(br09); intelfbhw_do_drawglyph() 1813 OUT_RING(br18); intelfbhw_do_drawglyph() 1814 OUT_RING(br19); intelfbhw_do_drawglyph() 1829 OUT_RING(dat); intelfbhw_do_drawglyph() 1832 OUT_RING(MI_NOOP); intelfbhw_do_drawglyph()
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H A D | intelfbhw.h | 534 #define OUT_RING(n) do { \ macro
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/linux-4.4.14/drivers/gpu/drm/msm/ |
H A D | msm_ringbuffer.h | 36 OUT_RING(struct msm_ringbuffer *ring, uint32_t data) OUT_RING() function
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