95 		OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_render_target()
96 		OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_render_target()
97 		OUT_RING(gpu_addr >> 8);  in set_render_target()
98 		OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));  in set_render_target()
99 		OUT_RING(2 << 0);  in set_render_target()
102 		OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_render_target()
103 		OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_render_target()
104 		OUT_RING(gpu_addr >> 8);  in set_render_target()
107 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_render_target()
108 	OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_render_target()
109 	OUT_RING((pitch << 0) | (slice << 10));  in set_render_target()
111 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_render_target()
112 	OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_render_target()
113 	OUT_RING(0);  in set_render_target()
115 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_render_target()
116 	OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_render_target()
117 	OUT_RING(cb_color_info);  in set_render_target()
119 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_render_target()
120 	OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_render_target()
121 	OUT_RING(0);  in set_render_target()
123 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_render_target()
124 	OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_render_target()
125 	OUT_RING(0);  in set_render_target()
127 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_render_target()
128 	OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_render_target()
129 	OUT_RING(0);  in set_render_target()
148 	OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));  in cp_set_surface_sync()
149 	OUT_RING(sync_type);  in cp_set_surface_sync()
150 	OUT_RING(cp_coher_size);  in cp_set_surface_sync()
151 	OUT_RING((mc_addr >> 8));  in cp_set_surface_sync()
152 	OUT_RING(10); /* poll interval */  in cp_set_surface_sync()
185 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_shaders()
186 	OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_shaders()
187 	OUT_RING(gpu_addr >> 8);  in set_shaders()
189 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_shaders()
190 	OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_shaders()
191 	OUT_RING(sq_pgm_resources);  in set_shaders()
193 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_shaders()
194 	OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_shaders()
195 	OUT_RING(0);  in set_shaders()
198 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_shaders()
199 	OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_shaders()
200 	OUT_RING((gpu_addr + 256) >> 8);  in set_shaders()
202 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_shaders()
203 	OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_shaders()
204 	OUT_RING(sq_pgm_resources | (1 << 28));  in set_shaders()
206 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_shaders()
207 	OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_shaders()
208 	OUT_RING(2);  in set_shaders()
210 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));  in set_shaders()
211 	OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_shaders()
212 	OUT_RING(0);  in set_shaders()
232 	OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));  in set_vtx_resource()
233 	OUT_RING(0x460);  in set_vtx_resource()
234 	OUT_RING(gpu_addr & 0xffffffff);  in set_vtx_resource()
235 	OUT_RING(48 - 1);  in set_vtx_resource()
236 	OUT_RING(sq_vtx_constant_word2);  in set_vtx_resource()
237 	OUT_RING(1 << 0);  in set_vtx_resource()
238 	OUT_RING(0);  in set_vtx_resource()
239 	OUT_RING(0);  in set_vtx_resource()
240 	OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30);  in set_vtx_resource()
280 	OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));  in set_tex_resource()
281 	OUT_RING(0);  in set_tex_resource()
282 	OUT_RING(sq_tex_resource_word0);  in set_tex_resource()
283 	OUT_RING(sq_tex_resource_word1);  in set_tex_resource()
284 	OUT_RING(gpu_addr >> 8);  in set_tex_resource()
285 	OUT_RING(gpu_addr >> 8);  in set_tex_resource()
286 	OUT_RING(sq_tex_resource_word4);  in set_tex_resource()
287 	OUT_RING(0);  in set_tex_resource()
288 	OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30);  in set_tex_resource()
300 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));  in set_scissors()
301 	OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_scissors()
302 	OUT_RING((x1 << 0) | (y1 << 16));  in set_scissors()
303 	OUT_RING((x2 << 0) | (y2 << 16));  in set_scissors()
305 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));  in set_scissors()
306 	OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_scissors()
307 	OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));  in set_scissors()
308 	OUT_RING((x2 << 0) | (y2 << 16));  in set_scissors()
310 	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));  in set_scissors()
311 	OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);  in set_scissors()
312 	OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));  in set_scissors()
313 	OUT_RING((x2 << 0) | (y2 << 16));  in set_scissors()
324 	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));  in draw_auto()
325 	OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2);  in draw_auto()
326 	OUT_RING(DI_PT_RECTLIST);  in draw_auto()
328 	OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));  in draw_auto()
330 	OUT_RING((2 << 2) | DI_INDEX_SIZE_16_BIT);  in draw_auto()
332 	OUT_RING(DI_INDEX_SIZE_16_BIT);  in draw_auto()
335 	OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));  in draw_auto()
336 	OUT_RING(1);  in draw_auto()
338 	OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));  in draw_auto()
339 	OUT_RING(3);  in draw_auto()
340 	OUT_RING(DI_SRC_SEL_AUTO_INDEX);  in draw_auto()
504 			OUT_RING(r7xx_default_state[i]);  in set_default_state()
508 			OUT_RING(r6xx_default_state[i]);  in set_default_state()
510 	OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));  in set_default_state()
511 	OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);  in set_default_state()
513 	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6));  in set_default_state()
514 	OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2);  in set_default_state()
515 	OUT_RING(sq_config);  in set_default_state()
516 	OUT_RING(sq_gpr_resource_mgmt_1);  in set_default_state()
517 	OUT_RING(sq_gpr_resource_mgmt_2);  in set_default_state()
518 	OUT_RING(sq_thread_resource_mgmt);  in set_default_state()
519 	OUT_RING(sq_stack_resource_mgmt_1);  in set_default_state()
520 	OUT_RING(sq_stack_resource_mgmt_2);  in set_default_state()
578 	OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));  in r600_done_blit_copy()
579 	OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);  in r600_done_blit_copy()
581 	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));  in r600_done_blit_copy()
582 	OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);  in r600_done_blit_copy()
583 	OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);  in r600_done_blit_copy()