Lines Matching refs:OUT_RING
458 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); in radeon_emit_clip_rect()
459 OUT_RING((box->y1 << 16) | box->x1); in radeon_emit_clip_rect()
460 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); in radeon_emit_clip_rect()
461 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); in radeon_emit_clip_rect()
490 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); in radeon_emit_state()
491 OUT_RING(ctx->pp_misc); in radeon_emit_state()
492 OUT_RING(ctx->pp_fog_color); in radeon_emit_state()
493 OUT_RING(ctx->re_solid_color); in radeon_emit_state()
494 OUT_RING(ctx->rb3d_blendcntl); in radeon_emit_state()
495 OUT_RING(ctx->rb3d_depthoffset); in radeon_emit_state()
496 OUT_RING(ctx->rb3d_depthpitch); in radeon_emit_state()
497 OUT_RING(ctx->rb3d_zstencilcntl); in radeon_emit_state()
498 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2)); in radeon_emit_state()
499 OUT_RING(ctx->pp_cntl); in radeon_emit_state()
500 OUT_RING(ctx->rb3d_cntl); in radeon_emit_state()
501 OUT_RING(ctx->rb3d_coloroffset); in radeon_emit_state()
502 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); in radeon_emit_state()
503 OUT_RING(ctx->rb3d_colorpitch); in radeon_emit_state()
509 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0)); in radeon_emit_state()
510 OUT_RING(ctx->se_coord_fmt); in radeon_emit_state()
516 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1)); in radeon_emit_state()
517 OUT_RING(ctx->re_line_pattern); in radeon_emit_state()
518 OUT_RING(ctx->re_line_state); in radeon_emit_state()
519 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0)); in radeon_emit_state()
520 OUT_RING(ctx->se_line_width); in radeon_emit_state()
526 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0)); in radeon_emit_state()
527 OUT_RING(ctx->pp_lum_matrix); in radeon_emit_state()
528 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1)); in radeon_emit_state()
529 OUT_RING(ctx->pp_rot_matrix_0); in radeon_emit_state()
530 OUT_RING(ctx->pp_rot_matrix_1); in radeon_emit_state()
536 OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2)); in radeon_emit_state()
537 OUT_RING(ctx->rb3d_stencilrefmask); in radeon_emit_state()
538 OUT_RING(ctx->rb3d_ropcntl); in radeon_emit_state()
539 OUT_RING(ctx->rb3d_planemask); in radeon_emit_state()
545 OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5)); in radeon_emit_state()
546 OUT_RING(ctx->se_vport_xscale); in radeon_emit_state()
547 OUT_RING(ctx->se_vport_xoffset); in radeon_emit_state()
548 OUT_RING(ctx->se_vport_yscale); in radeon_emit_state()
549 OUT_RING(ctx->se_vport_yoffset); in radeon_emit_state()
550 OUT_RING(ctx->se_vport_zscale); in radeon_emit_state()
551 OUT_RING(ctx->se_vport_zoffset); in radeon_emit_state()
557 OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0)); in radeon_emit_state()
558 OUT_RING(ctx->se_cntl); in radeon_emit_state()
559 OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0)); in radeon_emit_state()
560 OUT_RING(ctx->se_cntl_status); in radeon_emit_state()
566 OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0)); in radeon_emit_state()
567 OUT_RING(ctx->re_misc); in radeon_emit_state()
579 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5)); in radeon_emit_state()
580 OUT_RING(tex[0].pp_txfilter); in radeon_emit_state()
581 OUT_RING(tex[0].pp_txformat); in radeon_emit_state()
582 OUT_RING(tex[0].pp_txoffset); in radeon_emit_state()
583 OUT_RING(tex[0].pp_txcblend); in radeon_emit_state()
584 OUT_RING(tex[0].pp_txablend); in radeon_emit_state()
585 OUT_RING(tex[0].pp_tfactor); in radeon_emit_state()
586 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0)); in radeon_emit_state()
587 OUT_RING(tex[0].pp_border_color); in radeon_emit_state()
599 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5)); in radeon_emit_state()
600 OUT_RING(tex[1].pp_txfilter); in radeon_emit_state()
601 OUT_RING(tex[1].pp_txformat); in radeon_emit_state()
602 OUT_RING(tex[1].pp_txoffset); in radeon_emit_state()
603 OUT_RING(tex[1].pp_txcblend); in radeon_emit_state()
604 OUT_RING(tex[1].pp_txablend); in radeon_emit_state()
605 OUT_RING(tex[1].pp_tfactor); in radeon_emit_state()
606 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0)); in radeon_emit_state()
607 OUT_RING(tex[1].pp_border_color); in radeon_emit_state()
619 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5)); in radeon_emit_state()
620 OUT_RING(tex[2].pp_txfilter); in radeon_emit_state()
621 OUT_RING(tex[2].pp_txformat); in radeon_emit_state()
622 OUT_RING(tex[2].pp_txoffset); in radeon_emit_state()
623 OUT_RING(tex[2].pp_txcblend); in radeon_emit_state()
624 OUT_RING(tex[2].pp_txablend); in radeon_emit_state()
625 OUT_RING(tex[2].pp_tfactor); in radeon_emit_state()
626 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0)); in radeon_emit_state()
627 OUT_RING(tex[2].pp_border_color); in radeon_emit_state()
644 OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1)); in radeon_emit_state2()
645 OUT_RING(state->context2.se_zbias_factor); in radeon_emit_state2()
646 OUT_RING(state->context2.se_zbias_constant); in radeon_emit_state2()
790 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); in radeon_clear_box()
791 OUT_RING(0xffffffff); in radeon_clear_box()
796 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); in radeon_clear_box()
797 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_clear_box()
804 OUT_RING(dev_priv->front_pitch_offset); in radeon_clear_box()
806 OUT_RING(dev_priv->back_pitch_offset); in radeon_clear_box()
809 OUT_RING(color); in radeon_clear_box()
811 OUT_RING((x << 16) | y); in radeon_clear_box()
812 OUT_RING((w << 16) | h); in radeon_clear_box()
918 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); in radeon_cp_dispatch_clear()
919 OUT_RING(clear->color_mask); in radeon_cp_dispatch_clear()
939 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
941 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_clear()
949 OUT_RING(dev_priv->front_pitch_offset); in radeon_cp_dispatch_clear()
950 OUT_RING(clear->clear_color); in radeon_cp_dispatch_clear()
952 OUT_RING((x << 16) | y); in radeon_cp_dispatch_clear()
953 OUT_RING((w << 16) | h); in radeon_cp_dispatch_clear()
961 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
963 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_clear()
971 OUT_RING(dev_priv->back_pitch_offset); in radeon_cp_dispatch_clear()
972 OUT_RING(clear->clear_color); in radeon_cp_dispatch_clear()
974 OUT_RING((x << 16) | y); in radeon_cp_dispatch_clear()
975 OUT_RING((w << 16) | h); in radeon_cp_dispatch_clear()
1068 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
1071 OUT_RING(tileoffset * 8); in radeon_cp_dispatch_clear()
1073 OUT_RING(nrtilesx + 4); in radeon_cp_dispatch_clear()
1075 OUT_RING(clearmask); in radeon_cp_dispatch_clear()
1091 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
1098 OUT_RING(tileoffset * 16); in radeon_cp_dispatch_clear()
1100 OUT_RING(nrtilesx + 1); in radeon_cp_dispatch_clear()
1102 OUT_RING(clearmask); in radeon_cp_dispatch_clear()
1119 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
1121 OUT_RING(tileoffset * 128); in radeon_cp_dispatch_clear()
1123 OUT_RING(nrtilesx + 4); in radeon_cp_dispatch_clear()
1125 OUT_RING(clearmask); in radeon_cp_dispatch_clear()
1142 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2)); in radeon_cp_dispatch_clear()
1143 OUT_RING(0x0); /* First tile */ in radeon_cp_dispatch_clear()
1144 OUT_RING(0x3cc0); in radeon_cp_dispatch_clear()
1145 OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f); in radeon_cp_dispatch_clear()
1259 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12)); in radeon_cp_dispatch_clear()
1260 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | in radeon_cp_dispatch_clear()
1263 OUT_RING(depth_boxes[i].ui[CLEAR_X1]); in radeon_cp_dispatch_clear()
1264 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); in radeon_cp_dispatch_clear()
1265 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); in radeon_cp_dispatch_clear()
1266 OUT_RING(0x3f800000); in radeon_cp_dispatch_clear()
1267 OUT_RING(depth_boxes[i].ui[CLEAR_X1]); in radeon_cp_dispatch_clear()
1268 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); in radeon_cp_dispatch_clear()
1269 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); in radeon_cp_dispatch_clear()
1270 OUT_RING(0x3f800000); in radeon_cp_dispatch_clear()
1271 OUT_RING(depth_boxes[i].ui[CLEAR_X2]); in radeon_cp_dispatch_clear()
1272 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); in radeon_cp_dispatch_clear()
1273 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); in radeon_cp_dispatch_clear()
1274 OUT_RING(0x3f800000); in radeon_cp_dispatch_clear()
1308 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1)); in radeon_cp_dispatch_clear()
1309 OUT_RING(0x00000000); in radeon_cp_dispatch_clear()
1310 OUT_RING(rb3d_cntl); in radeon_cp_dispatch_clear()
1331 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13)); in radeon_cp_dispatch_clear()
1332 OUT_RING(RADEON_VTX_Z_PRESENT | in radeon_cp_dispatch_clear()
1334 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | in radeon_cp_dispatch_clear()
1340 OUT_RING(depth_boxes[i].ui[CLEAR_X1]); in radeon_cp_dispatch_clear()
1341 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); in radeon_cp_dispatch_clear()
1342 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); in radeon_cp_dispatch_clear()
1343 OUT_RING(0x0); in radeon_cp_dispatch_clear()
1345 OUT_RING(depth_boxes[i].ui[CLEAR_X1]); in radeon_cp_dispatch_clear()
1346 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); in radeon_cp_dispatch_clear()
1347 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); in radeon_cp_dispatch_clear()
1348 OUT_RING(0x0); in radeon_cp_dispatch_clear()
1350 OUT_RING(depth_boxes[i].ui[CLEAR_X2]); in radeon_cp_dispatch_clear()
1351 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); in radeon_cp_dispatch_clear()
1352 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); in radeon_cp_dispatch_clear()
1353 OUT_RING(0x0); in radeon_cp_dispatch_clear()
1408 OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0)); in radeon_cp_dispatch_swap()
1409 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_swap()
1420 OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1)); in radeon_cp_dispatch_swap()
1422 OUT_RING(dev_priv->back_pitch_offset); in radeon_cp_dispatch_swap()
1423 OUT_RING(dev_priv->front_pitch_offset); in radeon_cp_dispatch_swap()
1425 OUT_RING(dev_priv->front_pitch_offset); in radeon_cp_dispatch_swap()
1426 OUT_RING(dev_priv->back_pitch_offset); in radeon_cp_dispatch_swap()
1429 OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2)); in radeon_cp_dispatch_swap()
1430 OUT_RING((x << 16) | y); in radeon_cp_dispatch_swap()
1431 OUT_RING((x << 16) | y); in radeon_cp_dispatch_swap()
1432 OUT_RING((w << 16) | h); in radeon_cp_dispatch_swap()
1563 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3)); in radeon_cp_dispatch_vertex()
1564 OUT_RING(offset); in radeon_cp_dispatch_vertex()
1565 OUT_RING(numverts); in radeon_cp_dispatch_vertex()
1566 OUT_RING(prim->vc_format); in radeon_cp_dispatch_vertex()
1567 OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST | in radeon_cp_dispatch_vertex()
1628 OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1)); in radeon_cp_dispatch_indirect()
1629 OUT_RING(offset); in radeon_cp_dispatch_indirect()
1630 OUT_RING(dwords); in radeon_cp_dispatch_indirect()
1900 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5)); in radeon_cp_dispatch_texture()
1901 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_texture()
1909 OUT_RING((spitch << 22) | (offset >> 10)); in radeon_cp_dispatch_texture()
1910 OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10))); in radeon_cp_dispatch_texture()
1911 OUT_RING(0); in radeon_cp_dispatch_texture()
1912 OUT_RING((image->x << 16) | (image->y % 2048)); in radeon_cp_dispatch_texture()
1913 OUT_RING((image->width << 16) | height); in radeon_cp_dispatch_texture()
1948 OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0)); in radeon_cp_dispatch_stipple()
1949 OUT_RING(0x00000000); in radeon_cp_dispatch_stipple()
1951 OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31)); in radeon_cp_dispatch_stipple()
1953 OUT_RING(stipple[i]); in radeon_cp_dispatch_stipple()
2193 OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0)); in radeon_do_init_pageflip()
2194 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) | in radeon_do_init_pageflip()
2196 OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0)); in radeon_do_init_pageflip()
2197 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) | in radeon_do_init_pageflip()
2663 OUT_RING(CP_PACKET0(reg, (sz - 1))); in radeon_emit_packets()
2680 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); in radeon_emit_scalars()
2681 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); in radeon_emit_scalars()
2682 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); in radeon_emit_scalars()
2700 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); in radeon_emit_scalars2()
2701 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); in radeon_emit_scalars2()
2702 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); in radeon_emit_scalars2()
2719 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); in radeon_emit_vectors()
2720 OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); in radeon_emit_vectors()
2721 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); in radeon_emit_vectors()
2743 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); in radeon_emit_veclinear()
2744 OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); in radeon_emit_veclinear()
2745 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); in radeon_emit_veclinear()