| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/ |
| D | anx9805.c | 36 struct nvkm_i2c_port *mast = (void *)nv_object(chan)->parent; in anx9805_train() local
41 nv_wri2cr(mast, chan->addr, 0xa0, link_bw); in anx9805_train()
42 nv_wri2cr(mast, chan->addr, 0xa1, link_nr | (enh ? 0x80 : 0x00)); in anx9805_train()
43 nv_wri2cr(mast, chan->addr, 0xa2, 0x01); in anx9805_train()
44 nv_wri2cr(mast, chan->addr, 0xa8, 0x01); in anx9805_train()
47 while ((tmp = nv_rdi2cr(mast, chan->addr, 0xa8)) & 0x01) { in anx9805_train()
68 struct nvkm_i2c_port *mast = (void *)nv_object(chan)->parent; in anx9805_aux() local
75 tmp = nv_rdi2cr(mast, chan->ctrl, 0x07) & ~0x04; in anx9805_aux()
76 nv_wri2cr(mast, chan->ctrl, 0x07, tmp | 0x04); in anx9805_aux()
77 nv_wri2cr(mast, chan->ctrl, 0x07, tmp); in anx9805_aux()
[all …]
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | nv50.c | 127 u32 src, mast = nv_rd32(priv, 0x00c040); in read_pll_ref() local
131 src = !!(mast & 0x00200000); in read_pll_ref()
134 src = !!(mast & 0x00400000); in read_pll_ref()
137 src = !!(mast & 0x00010000); in read_pll_ref()
140 src = !!(mast & 0x02000000); in read_pll_ref()
159 u32 mast = nv_rd32(priv, 0x00c040); in read_pll() local
166 if (base == 0x004028 && (mast & 0x00100000)) { in read_pll()
193 u32 mast = nv_rd32(priv, 0x00c040); in nv50_clk_read() local
208 switch (mast & 0x30000000) { in nv50_clk_read()
216 if (!(mast & 0x00100000)) in nv50_clk_read()
[all …]
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| D | mcp77.c | 82 u32 mast = nv_rd32(clk, 0x00c054); in mcp77_clk_read() local
95 switch (mast & 0x000c0000) { in mcp77_clk_read()
105 switch (mast & 0x00000003) { in mcp77_clk_read()
113 if ((mast & 0x03000000) != 0x03000000) in mcp77_clk_read()
116 if ((mast & 0x00000200) == 0x00000000) in mcp77_clk_read()
119 switch (mast & 0x00000c00) { in mcp77_clk_read()
127 switch (mast & 0x00000030) { in mcp77_clk_read()
129 if (mast & 0x00000040) in mcp77_clk_read()
143 switch (mast & 0x00400000) { in mcp77_clk_read()
156 nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); in mcp77_clk_read()
[all …]
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| D | nv40.c | 108 u32 mast = nv_rd32(priv, 0x00c040); in nv40_clk_read() local
116 return read_clk(priv, (mast & 0x00000003) >> 0); in nv40_clk_read()
118 return read_clk(priv, (mast & 0x00000030) >> 4); in nv40_clk_read()
125 nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); in nv40_clk_read()
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/ |
| D | nv50_display.c | 388 struct nv50_mast mast; member
401 #define nv50_mast(d) (&nv50_disp(d)->mast)
473 struct nv50_mast *mast = nv50_mast(dev); in evo_sync() local
474 u32 *push = evo_wait(mast, 8); in evo_sync()
482 evo_kick(push, mast); in evo_sync()
676 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); in nv50_crtc_set_dither() local
697 push = evo_wait(mast, 4); in nv50_crtc_set_dither()
699 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { in nv50_crtc_set_dither()
703 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) { in nv50_crtc_set_dither()
715 evo_kick(push, mast); in nv50_crtc_set_dither()
[all …]
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | gf110.c | 296 struct nv50_disp_dmac *mast = (void *)object; in gf110_disp_core_init() local
299 ret = nv50_disp_chan_init(&mast->base); in gf110_disp_core_init()
307 nv_wr32(priv, 0x610494, mast->push); in gf110_disp_core_init()
316 nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610490)); in gf110_disp_core_init()
327 struct nv50_disp_dmac *mast = (void *)object; in gf110_disp_core_fini() local
333 nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610490)); in gf110_disp_core_fini()
342 return nv50_disp_chan_fini(&mast->base, suspend); in gf110_disp_core_fini()
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| D | nv50.c | 496 struct nv50_disp_dmac *mast; in nv50_disp_core_ctor() local
508 0, sizeof(*mast), (void **)&mast); in nv50_disp_core_ctor()
509 *pobject = nv_object(mast); in nv50_disp_core_ctor()
520 struct nv50_disp_dmac *mast = (void *)object; in nv50_disp_core_init() local
523 ret = nv50_disp_chan_init(&mast->base); in nv50_disp_core_init()
537 nv_wr32(priv, 0x610204, mast->push); in nv50_disp_core_init()
546 nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200)); in nv50_disp_core_init()
557 struct nv50_disp_dmac *mast = (void *)object; in nv50_disp_core_fini() local
563 nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610200)); in nv50_disp_core_fini()
571 return nv50_disp_chan_fini(&mast->base, suspend); in nv50_disp_core_fini()
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