| /linux-4.1.27/drivers/clk/socfpga/ |
| D | clk-periph.c | 37 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
38 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
63 u32 div_reg[3]; in __socfpga_periph_init() local
73 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
75 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_periph_init()
76 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
77 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
79 periph_clk->div_reg = 0; in __socfpga_periph_init()
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| D | clk-gate.c | 111 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()
112 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()
115 if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_recalc_rate()
188 u32 div_reg[3]; in __socfpga_gate_init() local
221 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
223 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_gate_init()
224 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
225 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
227 socfpga_clk->div_reg = 0; in __socfpga_gate_init()
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| D | clk.h | 46 void __iomem *div_reg; member
56 void __iomem *div_reg; member
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| /linux-4.1.27/sound/soc/jz4740/ |
| D | jz4740-i2s.c | 260 uint32_t ctrl, div_reg; in jz4740_i2s_hw_params() local
265 div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV); in jz4740_i2s_hw_params()
287 div_reg &= ~I2SDIV_DV_MASK; in jz4740_i2s_hw_params()
288 div_reg |= (div - 1) << I2SDIV_DV_SHIFT; in jz4740_i2s_hw_params()
294 div_reg &= ~I2SDIV_IDV_MASK; in jz4740_i2s_hw_params()
295 div_reg |= (div - 1) << I2SDIV_IDV_SHIFT; in jz4740_i2s_hw_params()
297 div_reg &= ~I2SDIV_DV_MASK; in jz4740_i2s_hw_params()
298 div_reg |= (div - 1) << I2SDIV_DV_SHIFT; in jz4740_i2s_hw_params()
303 jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg); in jz4740_i2s_hw_params()
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| /linux-4.1.27/arch/arm/mach-davinci/ |
| D | dm365.c | 90 .div_reg = BPDIV
103 .div_reg = PLLDIV1,
110 .div_reg = PLLDIV2,
117 .div_reg = PLLDIV3,
124 .div_reg = PLLDIV4,
131 .div_reg = PLLDIV5,
138 .div_reg = PLLDIV6,
145 .div_reg = PLLDIV7,
152 .div_reg = PLLDIV8,
159 .div_reg = PLLDIV9,
[all …]
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| D | dm646x.c | 86 .div_reg = PLLDIV1,
93 .div_reg = PLLDIV2,
100 .div_reg = PLLDIV3,
107 .div_reg = PLLDIV4,
114 .div_reg = PLLDIV5,
121 .div_reg = PLLDIV6,
128 .div_reg = PLLDIV8,
135 .div_reg = PLLDIV9,
142 .div_reg = BPDIV,
162 .div_reg = PLLDIV1,
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| D | dm644x.c | 71 .div_reg = PLLDIV1,
78 .div_reg = PLLDIV2,
85 .div_reg = PLLDIV3,
92 .div_reg = PLLDIV5,
105 .div_reg = BPDIV
119 .div_reg = PLLDIV1,
126 .div_reg = PLLDIV2,
133 .div_reg = BPDIV
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| D | dm355.c | 80 .div_reg = PLLDIV1,
87 .div_reg = PLLDIV2,
94 .div_reg = PLLDIV3,
101 .div_reg = PLLDIV4,
108 .div_reg = BPDIV
152 .div_reg = PLLDIV1,
159 .div_reg = BPDIV
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| D | clock.c | 308 if (!clk->div_reg) in clk_sysclk_recalc()
311 v = __raw_readl(pll->base + clk->div_reg); in clk_sysclk_recalc()
341 if (WARN_ON(!clk->div_reg)) in davinci_set_sysclk_rate()
377 v = __raw_readl(pll->base + clk->div_reg); in davinci_set_sysclk_rate()
380 __raw_writel(v, pll->base + clk->div_reg); in davinci_set_sysclk_rate()
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| D | da850.c | 83 .div_reg = PLLDIV1,
90 .div_reg = PLLDIV2,
97 .div_reg = PLLDIV3,
106 .div_reg = PLLDIV4,
113 .div_reg = PLLDIV5,
120 .div_reg = PLLDIV6,
127 .div_reg = PLLDIV7,
153 .div_reg = PLLDIV2,
160 .div_reg = PLLDIV3,
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| D | clock.h | 102 u32 div_reg; member
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| D | da830.c | 68 .div_reg = PLLDIV2,
75 .div_reg = PLLDIV3,
82 .div_reg = PLLDIV4,
89 .div_reg = PLLDIV5,
96 .div_reg = PLLDIV6,
103 .div_reg = PLLDIV7,
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| /linux-4.1.27/drivers/clk/ |
| D | clk-vt8500.c | 31 void __iomem *div_reg; member
127 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
198 writel(divisor, cdev->div_reg); in vt8500_dclk_set_rate()
234 u32 en_reg, div_reg; in vtwm_device_clk_init() local
264 rc = of_property_read_u32(node, "divisor-reg", &div_reg); in vtwm_device_clk_init()
266 dev_clk->div_reg = pmc_base + div_reg; in vtwm_device_clk_init()
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| /linux-4.1.27/drivers/clk/hisilicon/ |
| D | clk-hi3620.c | 242 u32 div_reg; member
258 void __iomem *div_reg; member
393 val = readl_relaxed(mclk->div_reg); in mmc_clk_set_timing()
395 writel_relaxed(val, mclk->div_reg); in mmc_clk_set_timing()
455 mclk->div_reg = base + mmc_clk->div_reg; in hisi_register_clk_mmc()
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