| /linux-4.1.27/drivers/net/dsa/ |
| H A D | mv88e6xxx.c | 171 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); mv88e6xxx_config_prio()
172 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); mv88e6xxx_config_prio()
173 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); mv88e6xxx_config_prio()
174 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); mv88e6xxx_config_prio()
175 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); mv88e6xxx_config_prio()
176 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); mv88e6xxx_config_prio()
177 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); mv88e6xxx_config_prio()
178 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); mv88e6xxx_config_prio()
181 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); mv88e6xxx_config_prio()
188 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); mv88e6xxx_set_addr_direct()
189 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); mv88e6xxx_set_addr_direct()
190 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); mv88e6xxx_set_addr_direct()
243 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); mv88e6xxx_ppu_disable()
244 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, mv88e6xxx_ppu_disable()
249 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); mv88e6xxx_ppu_disable()
264 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); mv88e6xxx_ppu_enable()
265 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE); mv88e6xxx_ppu_enable()
269 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); mv88e6xxx_ppu_enable()
456 ret = REG_READ(REG_GLOBAL, GLOBAL_STATS_OP); mv88e6xxx_stats_wait()
472 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, mv88e6xxx_stats_snapshot()
491 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP, mv88e6xxx_stats_read()
501 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); mv88e6xxx_stats_read()
507 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); mv88e6xxx_stats_read()
791 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP, _mv88e6xxx_atu_wait()
878 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid); _mv88e6xxx_atu_cmd()
882 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd); _mv88e6xxx_atu_cmd()
1095 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, __mv88e6xxx_write_addr()
1109 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, __mv88e6xxx_read_addr()
1135 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, __mv88e6xxx_port_fdb_cmd()
1195 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA); __mv88e6xxx_port_getnext()
1323 REG_WRITE(REG_GLOBAL, 0x04, 0xc000); mv88e6xxx_switch_reset()
1325 REG_WRITE(REG_GLOBAL, 0x04, 0xc400); mv88e6xxx_switch_reset()
1330 ret = REG_READ(REG_GLOBAL, 0x00); mv88e6xxx_switch_reset()
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| H A D | mv88e6060.c | 20 #define REG_GLOBAL 0x0f macro
99 REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); mv88e6060_switch_reset()
104 ret = REG_READ(REG_GLOBAL, 0x00); mv88e6060_switch_reset()
122 REG_WRITE(REG_GLOBAL, 0x04, 0x0800); mv88e6060_setup_global()
128 REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); mv88e6060_setup_global()
191 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); mv88e6060_set_addr()
192 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); mv88e6060_set_addr()
193 REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); mv88e6060_set_addr()
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| H A D | mv88e6131.c | 55 REG_WRITE(REG_GLOBAL, 0x04, 0x4400); mv88e6131_setup_global()
61 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); mv88e6131_setup_global()
69 REG_WRITE(REG_GLOBAL, 0x19, 0x8100); mv88e6131_setup_global()
75 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0); mv88e6131_setup_global()
82 REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f)); mv88e6131_setup_global()
84 REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f)); mv88e6131_setup_global()
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| H A D | mv88e6171.c | 48 REG_WRITE(REG_GLOBAL, 0x04, 0x6000); mv88e6171_setup_global()
54 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); mv88e6171_setup_global()
66 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1111)); mv88e6171_setup_global()
68 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); mv88e6171_setup_global()
73 REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); mv88e6171_setup_global()
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| H A D | mv88e6123_61_65.c | 64 REG_WRITE(REG_GLOBAL, 0x04, 0x0000); mv88e6123_61_65_setup_global()
70 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); mv88e6123_61_65_setup_global()
81 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); mv88e6123_61_65_setup_global()
86 REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); mv88e6123_61_65_setup_global()
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| H A D | mv88e6352.c | 57 REG_WRITE(REG_GLOBAL, 0x04, 0x6000); mv88e6352_setup_global()
63 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); mv88e6352_setup_global()
74 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); mv88e6352_setup_global()
79 REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); mv88e6352_setup_global()
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| H A D | mv88e6xxx.h | 87 #define REG_GLOBAL 0x1b macro
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