Searched refs:R4600_V1_HIT_CACHEOP_WAR (Results 1 - 16 of 16) sorted by relevance

/linux-4.1.27/arch/mips/include/asm/mach-cavium-octeon/
H A Dwar.h13 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-generic/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-ip22/
H A Dwar.h16 #define R4600_V1_HIT_CACHEOP_WAR 1 macro
/linux-4.1.27/arch/mips/include/asm/mach-ip27/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-ip28/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-ip32/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-malta/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-pmcs-msp71xx/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-rc32434/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-rm/
H A Dwar.h16 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-sead3/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-tx49xx/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-sibyte/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/
H A Dwar.h111 #ifndef R4600_V1_HIT_CACHEOP_WAR
112 #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
/linux-4.1.27/arch/mips/mm/
H A Dpage.c246 if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) { build_clear_pref()
398 if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) { build_copy_store_pref()
H A Dc-r4k.c103 if (R4600_V1_HIT_CACHEOP_WAR) \

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