1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
9#define __ASM_MIPS_MACH_SIBYTE_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR	0
12#define R4600_V1_HIT_CACHEOP_WAR	0
13#define R4600_V2_HIT_CACHEOP_WAR	0
14#define R5432_CP0_INTERRUPT_WAR		0
15
16#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
17    defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
18
19#ifndef __ASSEMBLY__
20extern int sb1250_m3_workaround_needed(void);
21#endif
22
23#define BCM1250_M3_WAR	sb1250_m3_workaround_needed()
24#define SIBYTE_1956_WAR 1
25
26#else
27
28#define BCM1250_M3_WAR	0
29#define SIBYTE_1956_WAR 0
30
31#endif
32
33#define MIPS4K_ICACHE_REFILL_WAR	0
34#define MIPS_CACHE_SYNC_WAR		0
35#define TX49XX_ICACHE_INDEX_INV_WAR	0
36#define ICACHE_REFILLS_WORKAROUND_WAR	0
37#define R10000_LLSC_WAR			0
38#define MIPS34K_MISSED_ITLB_WAR		0
39
40#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
41