Searched refs:x2 (Results 1 - 200 of 2605) sorted by relevance

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/linux-4.4.14/arch/x86/crypto/
H A Dserpent-avx-x86_64-asm_64.S68 #define S0_1(x0, x1, x2, x3, x4) \
71 vpxor x2, x3, x4; \
76 vpxor x0, x2, x2;
77 #define S0_2(x0, x1, x2, x3, x4) \
80 vpxor x2, x0, x0; \
81 vpand x1, x2, x2; \
82 vpxor x2, x3, x3; \
84 vpxor x4, x2, x2; \
85 vpxor x2, x1, x1;
87 #define S1_1(x0, x1, x2, x3, x4) \
93 vpxor x2, x3, x3; \
96 #define S1_2(x0, x1, x2, x3, x4) \
99 vpxor x2, x4, x4; \
100 vpand x0, x2, x2; \
101 vpxor x1, x2, x2; \
104 vpxor x2, x0, x0; \
107 #define S2_1(x0, x1, x2, x3, x4) \
110 vpand x2, x0, tp; \
113 vpxor x1, x2, x2; \
116 #define S2_2(x0, x1, x2, x3, x4) \
117 vpxor x2, tp, tp; \
118 vpand x3, x2, x2; \
123 vpxor x2, tp, x0; \
124 vpor x2, x1, x1;
126 #define S3_1(x0, x1, x2, x3, x4) \
130 vpxor x2, x0, x0; \
131 vpxor tp, x2, x2; \
133 vpxor x3, x2, x2; \
136 #define S3_2(x0, x1, x2, x3, x4) \
140 vpxor x2, x3, x3; \
142 vpand x1, x2, x2; \
145 vpxor x2, x3, x3;
147 #define S4_1(x0, x1, x2, x3, x4) \
150 vpxor x2, tp, tp; \
151 vpor x3, x2, x2; \
154 vpor x0, x2, x2; \
155 vpxor x1, x2, x2;
156 #define S4_2(x0, x1, x2, x3, x4) \
159 vpand x2, x4, x4; \
160 vpxor tp, x2, x2; \
166 #define S5_1(x0, x1, x2, x3, x4) \
168 vpxor tp, x2, x2; \
171 vpxor x2, x0, x0; \
175 #define S5_2(x0, x1, x2, x3, x4) \
178 vpxor x2, x3, x3; \
180 vpand x4, x2, x2; \
181 vpxor x2, x1, x1; \
182 vpand x0, x2, x2; \
183 vpxor x2, x3, x3;
185 #define S6_1(x0, x1, x2, x3, x4) \
187 vpxor x2, x1, tp; \
188 vpxor x0, x2, x2; \
193 vpxor x2, tp, x1;
194 #define S6_2(x0, x1, x2, x3, x4) \
197 vpand x0, x2, x2; \
199 vpxor x3, x2, x2; \
202 vpxor x2, x1, x1;
204 #define S7_1(x0, x1, x2, x3, x4) \
207 vpand x2, tp, x1; \
210 vpxor x2, tp, x4; \
211 vpxor x3, x2, x2; \
214 #define S7_2(x0, x1, x2, x3, x4) \
215 vpand x0, x2, x2; \
220 vpxor x4, x2, x2; \
225 #define SI0_1(x0, x1, x2, x3, x4) \
230 vpxor tp, x2, x2; \
233 vpxor x2, x0, x0;
234 #define SI0_2(x0, x1, x2, x3, x4) \
235 vpand x3, x2, x2; \
237 vpxor x3, x2, x2; \
241 vpxor x2, x0, x0; \
244 #define SI1_1(x0, x1, x2, x3, x4) \
246 vpxor x2, x0, tp; \
247 vpxor RNOT, x2, x2; \
251 vpxor x2, x1, x1; \
252 vpand x4, x2, x2;
253 #define SI1_2(x0, x1, x2, x3, x4) \
257 vpxor tp, x2, x2; \
259 vpxor x4, x2, x2; \
263 #define SI2_1(x0, x1, x2, x3, x4) \
264 vpxor x1, x2, x2; \
266 vpor x2, tp, tp; \
267 vpxor x3, x2, x2; \
270 vpor x2, x1, x1; \
271 vpxor x0, x2, x2;
272 #define SI2_2(x0, x1, x2, x3, x4) \
275 vpxor x3, x2, x2; \
276 vpxor x2, x4, x4; \
277 vpand x1, x2, x2; \
278 vpxor x3, x2, x2; \
282 #define SI3_1(x0, x1, x2, x3, x4) \
283 vpxor x1, x2, x2; \
284 vpand x2, x1, tp; \
290 vpxor x2, tp, x1;
291 #define SI3_2(x0, x1, x2, x3, x4) \
293 vpxor x2, x0, x0; \
294 vpxor x3, x2, x2; \
297 vpand x2, x0, x0; \
302 #define SI4_1(x0, x1, x2, x3, x4) \
303 vpxor x3, x2, x2; \
305 vpxor x2, tp, tp; \
306 vpor x3, x2, x2; \
309 vpxor x2, tp, x0; \
310 vpand x4, x2, x2;
311 #define SI4_2(x0, x1, x2, x3, x4) \
312 vpxor x0, x2, x2; \
315 vpand x2, x3, x3; \
322 #define SI5_1(x0, x1, x2, x3, x4) \
323 vpor x2, x1, tp; \
324 vpxor x1, x2, x2; \
327 vpxor x3, x2, x2; \
330 vpxor x2, x3, x3; \
331 vpor x0, x2, x2;
332 #define SI5_2(x0, x1, x2, x3, x4) \
334 vpxor x4, x2, x2; \
338 vpand x2, x0, x0; \
339 vpxor x3, x2, x2; \
340 vpxor x2, x0, x0; \
341 vpxor x4, x2, x2; \
344 #define SI6_1(x0, x1, x2, x3, x4) \
345 vpxor x2, x0, x0; \
347 vpxor x3, x2, x2; \
348 vpxor x2, tp, tp; \
350 vpor x0, x2, x2; \
351 vpxor x3, x2, x2; \
353 #define SI6_2(x0, x1, x2, x3, x4) \
356 vpand x2, x1, x1; \
359 vpxor x2, x4, x4; \
361 vpxor x0, x2, x2;
363 #define SI7_1(x0, x1, x2, x3, x4) \
365 vpxor x2, x0, x0; \
366 vpor x3, x2, x2; \
371 vpand x2, x0, x0; \
373 #define SI7_2(x0, x1, x2, x3, x4) \
374 vpand x2, x1, x1; \
375 vpxor x2, tp, x3; \
377 vpand x3, x2, x2; \
382 vpxor x2, x4, x4;
387 #define K2(x0, x1, x2, x3, x4, i) \
394 vpxor RK2, x2 ## 1, x2 ## 1; \
398 vpxor RK2, x2 ## 2, x2 ## 2; \
401 #define LK2(x0, x1, x2, x3, x4, i) \
406 vpslld $3, x2 ## 1, x4 ## 1; \
407 vpsrld $(32 - 3), x2 ## 1, x2 ## 1; \
408 vpor x4 ## 1, x2 ## 1, x2 ## 1; \
409 vpxor x2 ## 1, x1 ## 1, x1 ## 1; \
414 vpslld $3, x2 ## 2, x4 ## 2; \
415 vpsrld $(32 - 3), x2 ## 2, x2 ## 2; \
416 vpor x4 ## 2, x2 ## 2, x2 ## 2; \
417 vpxor x2 ## 2, x1 ## 2, x1 ## 2; \
422 vpxor x2 ## 1, x3 ## 1, x3 ## 1; \
429 vpxor x2 ## 2, x3 ## 2, x3 ## 2; \
438 vpxor x3 ## 1, x2 ## 1, x2 ## 1; \
439 vpxor x4 ## 1, x2 ## 1, x2 ## 1; \
447 vpxor x3 ## 2, x2 ## 2, x2 ## 2; \
448 vpxor x4 ## 2, x2 ## 2, x2 ## 2; \
455 vpslld $22, x2 ## 1, x4 ## 1; \
456 vpsrld $(32 - 22), x2 ## 1, x2 ## 1; \
457 vpor x4 ## 1, x2 ## 1, x2 ## 1; \
459 vpxor RK2, x2 ## 1, x2 ## 1; \
465 vpslld $22, x2 ## 2, x4 ## 2; \
466 vpsrld $(32 - 22), x2 ## 2, x2 ## 2; \
467 vpor x4 ## 2, x2 ## 2, x2 ## 2; \
469 vpxor RK2, x2 ## 2, x2 ## 2;
471 #define KL2(x0, x1, x2, x3, x4, i) \
473 vpxor RK2, x2 ## 1, x2 ## 1; \
479 vpsrld $22, x2 ## 1, x4 ## 1; \
480 vpslld $(32 - 22), x2 ## 1, x2 ## 1; \
481 vpor x4 ## 1, x2 ## 1, x2 ## 1; \
482 vpxor x3 ## 1, x2 ## 1, x2 ## 1; \
484 vpxor RK2, x2 ## 2, x2 ## 2; \
490 vpsrld $22, x2 ## 2, x4 ## 2; \
491 vpslld $(32 - 22), x2 ## 2, x2 ## 2; \
492 vpor x4 ## 2, x2 ## 2, x2 ## 2; \
493 vpxor x3 ## 2, x2 ## 2, x2 ## 2; \
497 vpxor x4 ## 1, x2 ## 1, x2 ## 1; \
504 vpxor x4 ## 2, x2 ## 2, x2 ## 2; \
523 vpxor x2 ## 1, x1 ## 1, x1 ## 1; \
524 vpxor x2 ## 1, x3 ## 1, x3 ## 1; \
525 vpsrld $3, x2 ## 1, x4 ## 1; \
526 vpslld $(32 - 3), x2 ## 1, x2 ## 1; \
527 vpor x4 ## 1, x2 ## 1, x2 ## 1; \
531 vpxor x2 ## 2, x1 ## 2, x1 ## 2; \
532 vpxor x2 ## 2, x3 ## 2, x3 ## 2; \
533 vpsrld $3, x2 ## 2, x4 ## 2; \
534 vpslld $(32 - 3), x2 ## 2, x2 ## 2; \
535 vpor x4 ## 2, x2 ## 2, x2 ## 2;
537 #define S(SBOX, x0, x1, x2, x3, x4) \
538 SBOX ## _1(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
539 SBOX ## _2(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
540 SBOX ## _1(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
541 SBOX ## _2(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2);
543 #define SP(SBOX, x0, x1, x2, x3, x4, i) \
545 SBOX ## _1(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
547 SBOX ## _2(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
549 SBOX ## _1(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
551 SBOX ## _2(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
553 #define transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
556 vpunpckldq x3, x2, t1; \
557 vpunpckhdq x3, x2, x3; \
561 vpunpcklqdq x3, t2, x2; \
564 #define read_blocks(x0, x1, x2, x3, t0, t1, t2) \
565 transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
567 #define write_blocks(x0, x1, x2, x3, t0, t1, t2) \
568 transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
H A Dserpent-avx2-asm_64.S60 #define S0_1(x0, x1, x2, x3, x4) \
63 vpxor x2, x3, x4; \
68 vpxor x0, x2, x2;
69 #define S0_2(x0, x1, x2, x3, x4) \
72 vpxor x2, x0, x0; \
73 vpand x1, x2, x2; \
74 vpxor x2, x3, x3; \
76 vpxor x4, x2, x2; \
77 vpxor x2, x1, x1;
79 #define S1_1(x0, x1, x2, x3, x4) \
85 vpxor x2, x3, x3; \
88 #define S1_2(x0, x1, x2, x3, x4) \
91 vpxor x2, x4, x4; \
92 vpand x0, x2, x2; \
93 vpxor x1, x2, x2; \
96 vpxor x2, x0, x0; \
99 #define S2_1(x0, x1, x2, x3, x4) \
102 vpand x2, x0, tp; \
105 vpxor x1, x2, x2; \
108 #define S2_2(x0, x1, x2, x3, x4) \
109 vpxor x2, tp, tp; \
110 vpand x3, x2, x2; \
115 vpxor x2, tp, x0; \
116 vpor x2, x1, x1;
118 #define S3_1(x0, x1, x2, x3, x4) \
122 vpxor x2, x0, x0; \
123 vpxor tp, x2, x2; \
125 vpxor x3, x2, x2; \
128 #define S3_2(x0, x1, x2, x3, x4) \
132 vpxor x2, x3, x3; \
134 vpand x1, x2, x2; \
137 vpxor x2, x3, x3;
139 #define S4_1(x0, x1, x2, x3, x4) \
142 vpxor x2, tp, tp; \
143 vpor x3, x2, x2; \
146 vpor x0, x2, x2; \
147 vpxor x1, x2, x2;
148 #define S4_2(x0, x1, x2, x3, x4) \
151 vpand x2, x4, x4; \
152 vpxor tp, x2, x2; \
158 #define S5_1(x0, x1, x2, x3, x4) \
160 vpxor tp, x2, x2; \
163 vpxor x2, x0, x0; \
167 #define S5_2(x0, x1, x2, x3, x4) \
170 vpxor x2, x3, x3; \
172 vpand x4, x2, x2; \
173 vpxor x2, x1, x1; \
174 vpand x0, x2, x2; \
175 vpxor x2, x3, x3;
177 #define S6_1(x0, x1, x2, x3, x4) \
179 vpxor x2, x1, tp; \
180 vpxor x0, x2, x2; \
185 vpxor x2, tp, x1;
186 #define S6_2(x0, x1, x2, x3, x4) \
189 vpand x0, x2, x2; \
191 vpxor x3, x2, x2; \
194 vpxor x2, x1, x1;
196 #define S7_1(x0, x1, x2, x3, x4) \
199 vpand x2, tp, x1; \
202 vpxor x2, tp, x4; \
203 vpxor x3, x2, x2; \
206 #define S7_2(x0, x1, x2, x3, x4) \
207 vpand x0, x2, x2; \
212 vpxor x4, x2, x2; \
217 #define SI0_1(x0, x1, x2, x3, x4) \
222 vpxor tp, x2, x2; \
225 vpxor x2, x0, x0;
226 #define SI0_2(x0, x1, x2, x3, x4) \
227 vpand x3, x2, x2; \
229 vpxor x3, x2, x2; \
233 vpxor x2, x0, x0; \
236 #define SI1_1(x0, x1, x2, x3, x4) \
238 vpxor x2, x0, tp; \
239 vpxor RNOT, x2, x2; \
243 vpxor x2, x1, x1; \
244 vpand x4, x2, x2;
245 #define SI1_2(x0, x1, x2, x3, x4) \
249 vpxor tp, x2, x2; \
251 vpxor x4, x2, x2; \
255 #define SI2_1(x0, x1, x2, x3, x4) \
256 vpxor x1, x2, x2; \
258 vpor x2, tp, tp; \
259 vpxor x3, x2, x2; \
262 vpor x2, x1, x1; \
263 vpxor x0, x2, x2;
264 #define SI2_2(x0, x1, x2, x3, x4) \
267 vpxor x3, x2, x2; \
268 vpxor x2, x4, x4; \
269 vpand x1, x2, x2; \
270 vpxor x3, x2, x2; \
274 #define SI3_1(x0, x1, x2, x3, x4) \
275 vpxor x1, x2, x2; \
276 vpand x2, x1, tp; \
282 vpxor x2, tp, x1;
283 #define SI3_2(x0, x1, x2, x3, x4) \
285 vpxor x2, x0, x0; \
286 vpxor x3, x2, x2; \
289 vpand x2, x0, x0; \
294 #define SI4_1(x0, x1, x2, x3, x4) \
295 vpxor x3, x2, x2; \
297 vpxor x2, tp, tp; \
298 vpor x3, x2, x2; \
301 vpxor x2, tp, x0; \
302 vpand x4, x2, x2;
303 #define SI4_2(x0, x1, x2, x3, x4) \
304 vpxor x0, x2, x2; \
307 vpand x2, x3, x3; \
314 #define SI5_1(x0, x1, x2, x3, x4) \
315 vpor x2, x1, tp; \
316 vpxor x1, x2, x2; \
319 vpxor x3, x2, x2; \
322 vpxor x2, x3, x3; \
323 vpor x0, x2, x2;
324 #define SI5_2(x0, x1, x2, x3, x4) \
326 vpxor x4, x2, x2; \
330 vpand x2, x0, x0; \
331 vpxor x3, x2, x2; \
332 vpxor x2, x0, x0; \
333 vpxor x4, x2, x2; \
336 #define SI6_1(x0, x1, x2, x3, x4) \
337 vpxor x2, x0, x0; \
339 vpxor x3, x2, x2; \
340 vpxor x2, tp, tp; \
342 vpor x0, x2, x2; \
343 vpxor x3, x2, x2; \
345 #define SI6_2(x0, x1, x2, x3, x4) \
348 vpand x2, x1, x1; \
351 vpxor x2, x4, x4; \
353 vpxor x0, x2, x2;
355 #define SI7_1(x0, x1, x2, x3, x4) \
357 vpxor x2, x0, x0; \
358 vpor x3, x2, x2; \
363 vpand x2, x0, x0; \
365 #define SI7_2(x0, x1, x2, x3, x4) \
366 vpand x2, x1, x1; \
367 vpxor x2, tp, x3; \
369 vpand x3, x2, x2; \
374 vpxor x2, x4, x4;
379 #define K2(x0, x1, x2, x3, x4, i) \
386 vpxor RK2, x2 ## 1, x2 ## 1; \
390 vpxor RK2, x2 ## 2, x2 ## 2; \
393 #define LK2(x0, x1, x2, x3, x4, i) \
398 vpslld $3, x2 ## 1, x4 ## 1; \
399 vpsrld $(32 - 3), x2 ## 1, x2 ## 1; \
400 vpor x4 ## 1, x2 ## 1, x2 ## 1; \
401 vpxor x2 ## 1, x1 ## 1, x1 ## 1; \
406 vpslld $3, x2 ## 2, x4 ## 2; \
407 vpsrld $(32 - 3), x2 ## 2, x2 ## 2; \
408 vpor x4 ## 2, x2 ## 2, x2 ## 2; \
409 vpxor x2 ## 2, x1 ## 2, x1 ## 2; \
414 vpxor x2 ## 1, x3 ## 1, x3 ## 1; \
421 vpxor x2 ## 2, x3 ## 2, x3 ## 2; \
430 vpxor x3 ## 1, x2 ## 1, x2 ## 1; \
431 vpxor x4 ## 1, x2 ## 1, x2 ## 1; \
439 vpxor x3 ## 2, x2 ## 2, x2 ## 2; \
440 vpxor x4 ## 2, x2 ## 2, x2 ## 2; \
447 vpslld $22, x2 ## 1, x4 ## 1; \
448 vpsrld $(32 - 22), x2 ## 1, x2 ## 1; \
449 vpor x4 ## 1, x2 ## 1, x2 ## 1; \
451 vpxor RK2, x2 ## 1, x2 ## 1; \
457 vpslld $22, x2 ## 2, x4 ## 2; \
458 vpsrld $(32 - 22), x2 ## 2, x2 ## 2; \
459 vpor x4 ## 2, x2 ## 2, x2 ## 2; \
461 vpxor RK2, x2 ## 2, x2 ## 2;
463 #define KL2(x0, x1, x2, x3, x4, i) \
465 vpxor RK2, x2 ## 1, x2 ## 1; \
471 vpsrld $22, x2 ## 1, x4 ## 1; \
472 vpslld $(32 - 22), x2 ## 1, x2 ## 1; \
473 vpor x4 ## 1, x2 ## 1, x2 ## 1; \
474 vpxor x3 ## 1, x2 ## 1, x2 ## 1; \
476 vpxor RK2, x2 ## 2, x2 ## 2; \
482 vpsrld $22, x2 ## 2, x4 ## 2; \
483 vpslld $(32 - 22), x2 ## 2, x2 ## 2; \
484 vpor x4 ## 2, x2 ## 2, x2 ## 2; \
485 vpxor x3 ## 2, x2 ## 2, x2 ## 2; \
489 vpxor x4 ## 1, x2 ## 1, x2 ## 1; \
496 vpxor x4 ## 2, x2 ## 2, x2 ## 2; \
515 vpxor x2 ## 1, x1 ## 1, x1 ## 1; \
516 vpxor x2 ## 1, x3 ## 1, x3 ## 1; \
517 vpsrld $3, x2 ## 1, x4 ## 1; \
518 vpslld $(32 - 3), x2 ## 1, x2 ## 1; \
519 vpor x4 ## 1, x2 ## 1, x2 ## 1; \
523 vpxor x2 ## 2, x1 ## 2, x1 ## 2; \
524 vpxor x2 ## 2, x3 ## 2, x3 ## 2; \
525 vpsrld $3, x2 ## 2, x4 ## 2; \
526 vpslld $(32 - 3), x2 ## 2, x2 ## 2; \
527 vpor x4 ## 2, x2 ## 2, x2 ## 2;
529 #define S(SBOX, x0, x1, x2, x3, x4) \
530 SBOX ## _1(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
531 SBOX ## _2(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
532 SBOX ## _1(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
533 SBOX ## _2(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2);
535 #define SP(SBOX, x0, x1, x2, x3, x4, i) \
537 SBOX ## _1(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
539 SBOX ## _2(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
541 SBOX ## _1(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
543 SBOX ## _2(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
545 #define transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
548 vpunpckldq x3, x2, t1; \
549 vpunpckhdq x3, x2, x3; \
553 vpunpcklqdq x3, t2, x2; \
556 #define read_blocks(x0, x1, x2, x3, t0, t1, t2) \
557 transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
559 #define write_blocks(x0, x1, x2, x3, t0, t1, t2) \
560 transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
H A Dserpent-sse2-i586-asm_32.S57 #define K(x0, x1, x2, x3, x4, i) \
63 pxor RT1, x2; \
67 #define LK(x0, x1, x2, x3, x4, i) \
73 movdqa x2, x4; \
74 pslld $3, x2; \
76 por x4, x2; \
77 pxor x2, x1; \
84 pxor x2, x3; \
94 pxor x3, x2; \
95 pxor x4, x2; \
104 movdqa x2, x4; \
105 pslld $22, x2; \
107 por x4, x2; \
111 pxor RT0, x2;
113 #define KL(x0, x1, x2, x3, x4, i) \
114 K(x0, x1, x2, x3, x4, i); \
119 movdqa x2, x4; \
120 psrld $22, x2; \
122 por x4, x2; \
123 pxor x3, x2; \
128 pxor x4, x2; \
145 pxor x2, x1; \
146 pxor x2, x3; \
147 movdqa x2, x4; \
148 psrld $3, x2; \
150 por x4, x2;
152 #define S0(x0, x1, x2, x3, x4) \
156 pxor x2, x4; \
161 pxor x0, x2; \
164 pxor x2, x0; \
165 pand x1, x2; \
166 pxor x2, x3; \
168 pxor x4, x2; \
169 pxor x2, x1;
171 #define S1(x0, x1, x2, x3, x4) \
178 pxor x2, x3; \
183 pxor x2, x4; \
184 pand x0, x2; \
185 pxor x1, x2; \
188 pxor x2, x0; \
191 #define S2(x0, x1, x2, x3, x4) \
195 pand x2, x0; \
198 pxor x1, x2; \
201 pxor x2, x0; \
202 pand x3, x2; \
207 pxor x2, x0; \
208 por x2, x1;
210 #define S3(x0, x1, x2, x3, x4) \
215 pxor x2, x0; \
216 pxor x1, x2; \
218 pxor x3, x2; \
224 pxor x2, x3; \
226 pand x1, x2; \
229 pxor x2, x3;
231 #define S4(x0, x1, x2, x3, x4) \
235 pxor x2, x3; \
236 por x4, x2; \
239 por x0, x2; \
240 pxor x1, x2; \
243 pand x2, x4; \
244 pxor x3, x2; \
250 #define S5(x0, x1, x2, x3, x4) \
253 pxor x1, x2; \
256 pxor x2, x0; \
262 pxor x2, x3; \
264 pand x4, x2; \
265 pxor x2, x1; \
266 pand x0, x2; \
267 pxor x2, x3;
269 #define S6(x0, x1, x2, x3, x4) \
272 pxor x2, x1; \
273 pxor x0, x2; \
278 pxor x2, x1; \
281 pand x0, x2; \
283 pxor x3, x2; \
286 pxor x2, x1;
288 #define S7(x0, x1, x2, x3, x4) \
292 pand x2, x1; \
295 pxor x2, x4; \
296 pxor x3, x2; \
299 pand x0, x2; \
304 pxor x4, x2; \
309 #define SI0(x0, x1, x2, x3, x4) \
315 pxor x3, x2; \
318 pxor x2, x0; \
319 pand x3, x2; \
321 pxor x3, x2; \
325 pxor x2, x0; \
328 #define SI1(x0, x1, x2, x3, x4) \
331 pxor x2, x0; \
332 pxor RNOT, x2; \
336 pxor x2, x1; \
337 pand x4, x2; \
341 pxor x0, x2; \
343 pxor x4, x2; \
347 #define SI2(x0, x1, x2, x3, x4) \
348 pxor x1, x2; \
351 por x2, x3; \
352 pxor x4, x2; \
355 por x2, x1; \
356 pxor x0, x2; \
359 pxor x3, x2; \
360 pxor x2, x4; \
361 pand x1, x2; \
362 pxor x3, x2; \
366 #define SI3(x0, x1, x2, x3, x4) \
367 pxor x1, x2; \
369 pand x2, x1; \
375 pxor x2, x1; \
377 pxor x2, x0; \
378 pxor x3, x2; \
381 pand x2, x0; \
386 #define SI4(x0, x1, x2, x3, x4) \
387 pxor x3, x2; \
390 pxor x2, x0; \
391 por x3, x2; \
394 pxor x2, x0; \
395 pand x4, x2; \
396 pxor x0, x2; \
399 pand x2, x3; \
406 #define SI5(x0, x1, x2, x3, x4) \
408 por x2, x1; \
409 pxor x4, x2; \
412 pxor x3, x2; \
415 pxor x2, x3; \
416 por x0, x2; \
418 pxor x4, x2; \
422 pand x2, x0; \
423 pxor x3, x2; \
424 pxor x2, x0; \
425 pxor x4, x2; \
428 #define SI6(x0, x1, x2, x3, x4) \
429 pxor x2, x0; \
432 pxor x3, x2; \
433 pxor x2, x0; \
435 por x4, x2; \
436 pxor x3, x2; \
440 pand x2, x1; \
443 pxor x2, x4; \
445 pxor x0, x2;
447 #define SI7(x0, x1, x2, x3, x4) \
450 pxor x2, x0; \
451 por x4, x2; \
456 pand x2, x0; \
458 pand x2, x1; \
459 pxor x2, x3; \
461 pand x3, x2; \
466 pxor x2, x4;
468 #define transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
472 movdqa x2, t1; \
473 punpckhdq x3, x2; \
479 punpcklqdq x2, t2; \
480 punpckhqdq x2, x3; \
481 movdqa t2, x2;
483 #define read_blocks(in, x0, x1, x2, x3, t0, t1, t2) \
486 movdqu (2*4*4)(in), x2; \
489 transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
491 #define write_blocks(out, x0, x1, x2, x3, t0, t1, t2) \
492 transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
496 movdqu x2, (2*4*4)(out); \
499 #define xor_blocks(out, x0, x1, x2, x3, t0, t1, t2) \
500 transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
509 pxor t0, x2; \
510 movdqu x2, (2*4*4)(out); \
H A Dserpent-sse2-x86_64-asm_64.S56 #define S0_1(x0, x1, x2, x3, x4) \
60 pxor x2, x4; \
65 pxor x0, x2;
66 #define S0_2(x0, x1, x2, x3, x4) \
69 pxor x2, x0; \
70 pand x1, x2; \
71 pxor x2, x3; \
73 pxor x4, x2; \
74 pxor x2, x1;
76 #define S1_1(x0, x1, x2, x3, x4) \
83 pxor x2, x3; \
86 #define S1_2(x0, x1, x2, x3, x4) \
89 pxor x2, x4; \
90 pand x0, x2; \
91 pxor x1, x2; \
94 pxor x2, x0; \
97 #define S2_1(x0, x1, x2, x3, x4) \
101 pand x2, x0; \
104 pxor x1, x2; \
107 #define S2_2(x0, x1, x2, x3, x4) \
108 pxor x2, x0; \
109 pand x3, x2; \
114 pxor x2, x0; \
115 por x2, x1;
117 #define S3_1(x0, x1, x2, x3, x4) \
122 pxor x2, x0; \
123 pxor x1, x2; \
125 pxor x3, x2; \
128 #define S3_2(x0, x1, x2, x3, x4) \
132 pxor x2, x3; \
134 pand x1, x2; \
137 pxor x2, x3;
139 #define S4_1(x0, x1, x2, x3, x4) \
143 pxor x2, x3; \
144 por x4, x2; \
147 por x0, x2; \
148 pxor x1, x2;
149 #define S4_2(x0, x1, x2, x3, x4) \
152 pand x2, x4; \
153 pxor x3, x2; \
159 #define S5_1(x0, x1, x2, x3, x4) \
162 pxor x1, x2; \
165 pxor x2, x0; \
169 #define S5_2(x0, x1, x2, x3, x4) \
172 pxor x2, x3; \
174 pand x4, x2; \
175 pxor x2, x1; \
176 pand x0, x2; \
177 pxor x2, x3;
179 #define S6_1(x0, x1, x2, x3, x4) \
182 pxor x2, x1; \
183 pxor x0, x2; \
188 pxor x2, x1;
189 #define S6_2(x0, x1, x2, x3, x4) \
192 pand x0, x2; \
194 pxor x3, x2; \
197 pxor x2, x1;
199 #define S7_1(x0, x1, x2, x3, x4) \
203 pand x2, x1; \
206 pxor x2, x4; \
207 pxor x3, x2; \
210 #define S7_2(x0, x1, x2, x3, x4) \
211 pand x0, x2; \
216 pxor x4, x2; \
221 #define SI0_1(x0, x1, x2, x3, x4) \
227 pxor x3, x2; \
230 pxor x2, x0;
231 #define SI0_2(x0, x1, x2, x3, x4) \
232 pand x3, x2; \
234 pxor x3, x2; \
238 pxor x2, x0; \
241 #define SI1_1(x0, x1, x2, x3, x4) \
244 pxor x2, x0; \
245 pxor RNOT, x2; \
249 pxor x2, x1; \
250 pand x4, x2;
251 #define SI1_2(x0, x1, x2, x3, x4) \
255 pxor x0, x2; \
257 pxor x4, x2; \
261 #define SI2_1(x0, x1, x2, x3, x4) \
262 pxor x1, x2; \
265 por x2, x3; \
266 pxor x4, x2; \
269 por x2, x1; \
270 pxor x0, x2;
271 #define SI2_2(x0, x1, x2, x3, x4) \
274 pxor x3, x2; \
275 pxor x2, x4; \
276 pand x1, x2; \
277 pxor x3, x2; \
281 #define SI3_1(x0, x1, x2, x3, x4) \
282 pxor x1, x2; \
284 pand x2, x1; \
290 pxor x2, x1;
291 #define SI3_2(x0, x1, x2, x3, x4) \
293 pxor x2, x0; \
294 pxor x3, x2; \
297 pand x2, x0; \
302 #define SI4_1(x0, x1, x2, x3, x4) \
303 pxor x3, x2; \
306 pxor x2, x0; \
307 por x3, x2; \
310 pxor x2, x0; \
311 pand x4, x2;
312 #define SI4_2(x0, x1, x2, x3, x4) \
313 pxor x0, x2; \
316 pand x2, x3; \
323 #define SI5_1(x0, x1, x2, x3, x4) \
325 por x2, x1; \
326 pxor x4, x2; \
329 pxor x3, x2; \
332 pxor x2, x3; \
333 por x0, x2;
334 #define SI5_2(x0, x1, x2, x3, x4) \
336 pxor x4, x2; \
340 pand x2, x0; \
341 pxor x3, x2; \
342 pxor x2, x0; \
343 pxor x4, x2; \
346 #define SI6_1(x0, x1, x2, x3, x4) \
347 pxor x2, x0; \
350 pxor x3, x2; \
351 pxor x2, x0; \
353 por x4, x2; \
354 pxor x3, x2; \
356 #define SI6_2(x0, x1, x2, x3, x4) \
359 pand x2, x1; \
362 pxor x2, x4; \
364 pxor x0, x2;
366 #define SI7_1(x0, x1, x2, x3, x4) \
369 pxor x2, x0; \
370 por x4, x2; \
375 pand x2, x0; \
377 #define SI7_2(x0, x1, x2, x3, x4) \
378 pand x2, x1; \
379 pxor x2, x3; \
381 pand x3, x2; \
386 pxor x2, x4;
392 #define K2(x0, x1, x2, x3, x4, i) \
399 pxor RK2, x2 ## 1; \
403 pxor RK2, x2 ## 2; \
406 #define LK2(x0, x1, x2, x3, x4, i) \
412 movdqa x2 ## 1, x4 ## 1; \
413 pslld $3, x2 ## 1; \
415 por x4 ## 1, x2 ## 1; \
416 pxor x2 ## 1, x1 ## 1; \
422 movdqa x2 ## 2, x4 ## 2; \
423 pslld $3, x2 ## 2; \
425 por x4 ## 2, x2 ## 2; \
426 pxor x2 ## 2, x1 ## 2; \
433 pxor x2 ## 1, x3 ## 1; \
443 pxor x2 ## 2, x3 ## 2; \
454 pxor x3 ## 1, x2 ## 1; \
455 pxor x4 ## 1, x2 ## 1; \
464 pxor x3 ## 2, x2 ## 2; \
465 pxor x4 ## 2, x2 ## 2; \
473 movdqa x2 ## 1, x4 ## 1; \
474 pslld $22, x2 ## 1; \
476 por x4 ## 1, x2 ## 1; \
478 pxor RK2, x2 ## 1; \
485 movdqa x2 ## 2, x4 ## 2; \
486 pslld $22, x2 ## 2; \
488 por x4 ## 2, x2 ## 2; \
490 pxor RK2, x2 ## 2;
492 #define KL2(x0, x1, x2, x3, x4, i) \
494 pxor RK2, x2 ## 1; \
501 movdqa x2 ## 1, x4 ## 1; \
502 psrld $22, x2 ## 1; \
504 por x4 ## 1, x2 ## 1; \
505 pxor x3 ## 1, x2 ## 1; \
507 pxor RK2, x2 ## 2; \
514 movdqa x2 ## 2, x4 ## 2; \
515 psrld $22, x2 ## 2; \
517 por x4 ## 2, x2 ## 2; \
518 pxor x3 ## 2, x2 ## 2; \
523 pxor x4 ## 1, x2 ## 1; \
532 pxor x4 ## 2, x2 ## 2; \
558 pxor x2 ## 1, x1 ## 1; \
559 pxor x2 ## 1, x3 ## 1; \
560 movdqa x2 ## 1, x4 ## 1; \
561 psrld $3, x2 ## 1; \
563 por x4 ## 1, x2 ## 1; \
567 pxor x2 ## 2, x1 ## 2; \
568 pxor x2 ## 2, x3 ## 2; \
569 movdqa x2 ## 2, x4 ## 2; \
570 psrld $3, x2 ## 2; \
572 por x4 ## 2, x2 ## 2;
574 #define S(SBOX, x0, x1, x2, x3, x4) \
575 SBOX ## _1(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
576 SBOX ## _2(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
577 SBOX ## _1(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
578 SBOX ## _2(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2);
580 #define SP(SBOX, x0, x1, x2, x3, x4, i) \
582 SBOX ## _1(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
584 SBOX ## _1(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
586 SBOX ## _2(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
588 SBOX ## _2(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
590 #define transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
594 movdqa x2, t1; \
595 punpckhdq x3, x2; \
601 punpcklqdq x2, t2; \
602 punpckhqdq x2, x3; \
603 movdqa t2, x2;
605 #define read_blocks(in, x0, x1, x2, x3, t0, t1, t2) \
608 movdqu (2*4*4)(in), x2; \
611 transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
613 #define write_blocks(out, x0, x1, x2, x3, t0, t1, t2) \
614 transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
618 movdqu x2, (2*4*4)(out); \
621 #define xor_blocks(out, x0, x1, x2, x3, t0, t1, t2) \
622 transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
631 pxor t0, x2; \
632 movdqu x2, (2*4*4)(out); \
H A Dglue_helper-asm-avx.S18 #define load_8way(src, x0, x1, x2, x3, x4, x5, x6, x7) \
21 vmovdqu (2*16)(src), x2; \
28 #define store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \
31 vmovdqu x2, (2*16)(dst); \
38 #define store_cbc_8way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \
40 vpxor (1*16)(src), x2, x2; \
46 store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
54 #define load_ctr_8way(iv, bswap, x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2) \
67 vpshufb t1, x7, x2; \
82 #define store_ctr_8way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \
85 vpxor (2*16)(src), x2, x2; \
91 store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
100 #define load_xts_8way(iv, src, dst, x0, x1, x2, x3, x4, x5, x6, x7, tiv, t0, \
115 vpxor (2*16)(src), tiv, x2; \
141 #define store_xts_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \
144 vpxor (2*16)(dst), x2, x2; \
150 store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
H A Dglue_helper-asm-avx2.S13 #define load_16way(src, x0, x1, x2, x3, x4, x5, x6, x7) \
16 vmovdqu (2*32)(src), x2; \
23 #define store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \
26 vmovdqu x2, (2*32)(dst); \
33 #define store_cbc_16way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7, t0) \
38 vpxor (1*32+16)(src), x2, x2; \
44 store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
60 #define load_ctr_16way(iv, bswap, x0, x1, x2, x3, x4, x5, x6, x7, t0, t0x, t1, \
78 vpshufb t1, t2, x2; \
93 #define store_ctr_16way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \
96 vpxor (2*32)(src), x2, x2; \
102 store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
123 #define load_xts_16way(iv, src, dst, x0, x1, x2, x3, x4, x5, x6, x7, tiv, \
144 vpxor (2*32)(src), tiv, x2; \
171 #define store_xts_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \
174 vpxor (2*32)(dst), x2, x2; \
180 store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
H A Dtwofish-avx-x86_64-asm_64.S132 #define round_head_2(a, b, x1, y1, x2, y2) \
148 G(RGI1, RGI2, x2, s0, s1, s2, s3); \
149 vmovq RGS2, x2; \
150 vpinsrq $1, RGS3, x2, x2; \
221 #define transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
224 vpunpckldq x3, x2, t1; \
225 vpunpckhdq x3, x2, x3; \
229 vpunpcklqdq x3, t2, x2; \
232 #define inpack_blocks(x0, x1, x2, x3, wkey, t0, t1, t2) \
235 vpxor x2, wkey, x2; \
238 transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
240 #define outunpack_blocks(x0, x1, x2, x3, wkey, t0, t1, t2) \
241 transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
245 vpxor x2, wkey, x2; \
H A Dcamellia-aesni-avx-asm_64.S49 #define roundsm16(x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2, t3, t4, t5, t6, \
64 vpshufb t4, x2, x2; \
76 filter_8bit(x2, t0, t1, t7, t6); \
91 vaesenclast t4, x2, x2; \
107 filter_8bit(x2, t2, t3, t7, t6); \
135 vpxor x7, x2, x2; \
138 vpxor x2, x4, x4; \
145 vpxor x5, x2, x2; \
151 vpxor x2, x7, x7; /* note: high and low parts swapped */ \
179 vpxor t5, x2, x2; \
180 vpxor 6 * 16(mem_cd), x2, x2; \
211 #define two_roundsm16(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
222 vmovdqu x2, 6 * 16(mem_cd); \
228 store_ab(x0, x1, x2, x3, x4, x5, x6, x7, mem_ab);
230 #define dummy_store(x0, x1, x2, x3, x4, x5, x6, x7, mem_ab) /* do nothing */
232 #define store_ab_state(x0, x1, x2, x3, x4, x5, x6, x7, mem_ab) \
236 vmovdqu x2, 2 * 16(mem_ab); \
243 #define enc_rounds16(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
245 two_roundsm16(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
247 two_roundsm16(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
249 two_roundsm16(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
252 #define dec_rounds16(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
254 two_roundsm16(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
256 two_roundsm16(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
258 two_roundsm16(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
418 #define transpose_4x4(x0, x1, x2, x3, t1, t2) \
422 vpunpckldq x3, x2, t1; \
423 vpunpckhdq x3, x2, x2; \
428 vpunpckhqdq x2, t2, x3; \
429 vpunpcklqdq x2, t2, x2;
481 #define inpack16_pre(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
499 vpxor 13 * 16(rio), x0, x2; \
504 #define inpack16_post(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
506 byteslice_16x16b(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, \
511 vmovdqu x2, 2 * 16(mem_ab); \
527 #define outunpack16(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, \
529 byteslice_16x16b(y0, y4, x0, x4, y1, y5, x1, x5, y2, y6, x2, x6, y3, \
550 vpxor x0, x2, x2; \
554 #define write_output(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
558 vmovdqu x2, 2 * 16(rio); \
H A Dcamellia-aesni-avx2-asm_64.S66 #define roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2, t3, t4, t5, t6, \
83 vpshufb t4, x2, x2; \
98 filter_8bit(x2, t5, t6, t7, t4); \
106 vextracti128 $1, x2, t6##_x; \
124 vaesenclast t4##_x, x2##_x, x2##_x; \
126 vinserti128 $1, t6##_x, x2, x2; \
148 filter_8bit(x2, t2, t3, t7, t6); \
166 vpxor x7, x2, x2; \
175 vpxor x2, x4, x4; \
186 vpxor x5, x2, x2; \
192 vpxor x2, x7, x7; /* note: high and low parts swapped */ \
206 vpxor t5, x2, x2; \
207 vpxor 6 * 32(mem_cd), x2, x2; \
250 #define two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
257 vmovdqu x2, 6 * 32(mem_cd); \
267 store_ab(x0, x1, x2, x3, x4, x5, x6, x7, mem_ab);
269 #define dummy_store(x0, x1, x2, x3, x4, x5, x6, x7, mem_ab) /* do nothing */
271 #define store_ab_state(x0, x1, x2, x3, x4, x5, x6, x7, mem_ab) \
279 vmovdqu x2, 2 * 32(mem_ab); \
282 #define enc_rounds32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
284 two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
286 two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
288 two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
291 #define dec_rounds32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
293 two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
295 two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
297 two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
457 #define transpose_4x4(x0, x1, x2, x3, t1, t2) \
461 vpunpckldq x3, x2, t1; \
462 vpunpckhdq x3, x2, x2; \
467 vpunpckhqdq x2, t2, x3; \
468 vpunpcklqdq x2, t2, x2;
520 #define inpack32_pre(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
538 vpxor 13 * 32(rio), x0, x2; \
543 #define inpack32_post(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
545 byteslice_16x16b_fast(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, \
550 vmovdqu x2, 2 * 32(mem_ab); \
566 #define outunpack32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, \
568 byteslice_16x16b_fast(y0, y4, x0, x4, y1, y5, x1, x5, y2, y6, x2, x6, \
589 vpxor x0, x2, x2; \
593 #define write_output(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
597 vmovdqu x2, 2 * 32(rio); \
H A Dcast6-avx-x86_64-asm_64.S200 #define transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
203 vpunpckldq x3, x2, t1; \
204 vpunpckhdq x3, x2, x3; \
208 vpunpcklqdq x3, t2, x2; \
211 #define inpack_blocks(x0, x1, x2, x3, t0, t1, t2, rmask) \
214 vpshufb rmask, x2, x2; \
217 transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
219 #define outunpack_blocks(x0, x1, x2, x3, t0, t1, t2, rmask) \
220 transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
224 vpshufb rmask, x2, x2; \
H A Dchacha20-ssse3-x86_64.S57 # x2 += x3, x1 = rotl32(x1 ^ x2, 12)
70 # x2 += x3, x1 = rotl32(x1 ^ x2, 7)
80 # x2 = shuffle32(x2, MASK(1, 0, 3, 2))
90 # x2 += x3, x1 = rotl32(x1 ^ x2, 12)
103 # x2 += x3, x1 = rotl32(x1 ^ x2, 7)
113 # x2 = shuffle32(x2, MASK(1, 0, 3, 2))
131 # o2 = i2 ^ (x2 + s2)
217 # x2 += x6, x14 = rotl32(x14 ^ x2, 16)
271 # x2 += x6, x14 = rotl32(x14 ^ x2, 8)
325 # x2 += x7, x13 = rotl32(x13 ^ x2, 16)
379 # x2 += x7, x13 = rotl32(x13 ^ x2, 8)
433 # x2[0-3] += s0[2]
/linux-4.4.14/drivers/pinctrl/sunxi/
H A Dpinctrl-sun8i-a23.c29 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
35 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
41 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
47 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
53 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
58 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
63 SUNXI_FUNCTION(0x2, "uart4"), /* RTS */
68 SUNXI_FUNCTION(0x2, "uart4"), /* CTS */
74 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
79 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
84 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
89 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
94 SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
99 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
104 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
115 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
120 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
125 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
130 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
135 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
139 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
144 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
149 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
153 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
158 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
163 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
168 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
173 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
178 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
183 SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
188 SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
193 SUNXI_FUNCTION(0x2, "nand"), /* DQS */
198 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
202 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
207 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
211 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
215 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
220 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
225 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
230 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
235 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
240 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
245 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
250 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
255 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
260 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
265 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
270 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
275 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
280 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
285 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
290 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
295 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
300 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
305 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
310 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
315 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
320 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
325 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
330 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
335 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
340 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
346 SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
350 SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
354 SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
358 SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
362 SUNXI_FUNCTION(0x2, "csi")), /* D0 */
366 SUNXI_FUNCTION(0x2, "csi")), /* D1 */
370 SUNXI_FUNCTION(0x2, "csi")), /* D2 */
374 SUNXI_FUNCTION(0x2, "csi")), /* D3 */
378 SUNXI_FUNCTION(0x2, "csi")), /* D4 */
382 SUNXI_FUNCTION(0x2, "csi")), /* D5 */
386 SUNXI_FUNCTION(0x2, "csi")), /* D6 */
390 SUNXI_FUNCTION(0x2, "csi")), /* D7 */
394 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
399 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
417 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
422 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
427 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
432 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
437 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
442 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
448 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
453 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
458 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
463 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
468 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
473 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
478 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
483 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
488 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
493 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
498 SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
503 SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
508 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
513 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
519 SUNXI_FUNCTION(0x2, "pwm0")),
523 SUNXI_FUNCTION(0x2, "pwm1")),
527 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
531 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
535 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
539 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
543 SUNXI_FUNCTION(0x2, "spi0"), /* CS */
548 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
553 SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
558 SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
H A Dpinctrl-sun6i-a31s.c26 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
38 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
44 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
50 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
56 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
62 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
68 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
74 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
79 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
86 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
93 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
100 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
107 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
114 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
121 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
127 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
133 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
139 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
145 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
151 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
157 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
163 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
169 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
175 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
181 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
187 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
193 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
199 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
205 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
210 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
215 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
220 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
226 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
233 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
246 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
251 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
256 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
261 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
265 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
269 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
273 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
279 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
285 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
291 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
297 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
303 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
309 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
315 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
321 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
327 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
334 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
340 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
344 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
353 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
358 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
363 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
368 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
373 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
378 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
383 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
388 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
393 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
398 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
403 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
407 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
411 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
415 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
419 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
423 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
427 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
431 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
435 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
439 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
443 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
447 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
451 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
455 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
459 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
463 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
467 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
471 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
476 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
482 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
488 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
494 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
500 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
506 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
512 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
518 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
524 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
530 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
536 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
542 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
548 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
554 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
560 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
566 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
573 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
578 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
583 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
588 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
593 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
598 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
604 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
609 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
614 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
619 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
624 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
629 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
634 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
639 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
644 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
649 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
654 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
659 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
664 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
670 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
676 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
682 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
688 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
694 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
699 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
705 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
711 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
717 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
723 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
729 SUNXI_FUNCTION(0x2, "pwm0")),
733 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
737 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
741 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
745 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
749 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
753 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
757 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
761 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
H A Dpinctrl-sun8i-a33.c28 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
34 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
40 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
45 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
50 SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
56 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
62 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
68 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
75 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
80 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
85 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
90 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
95 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
99 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
104 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
109 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
113 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
118 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
123 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
128 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
133 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
138 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
143 SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
148 SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
153 SUNXI_FUNCTION(0x2, "nand"), /* DQS */
159 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
164 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
169 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
174 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
179 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
184 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
189 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
194 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
199 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
204 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
209 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
213 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
217 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
222 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
227 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
232 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
237 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
242 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
247 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
252 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
257 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
262 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
268 SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
272 SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
276 SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
280 SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
284 SUNXI_FUNCTION(0x2, "csi")), /* D0 */
288 SUNXI_FUNCTION(0x2, "csi")), /* D1 */
292 SUNXI_FUNCTION(0x2, "csi")), /* D2 */
296 SUNXI_FUNCTION(0x2, "csi")), /* D3 */
300 SUNXI_FUNCTION(0x2, "csi")), /* D4 */
304 SUNXI_FUNCTION(0x2, "csi")), /* D5 */
308 SUNXI_FUNCTION(0x2, "csi")), /* D6 */
312 SUNXI_FUNCTION(0x2, "csi")), /* D7 */
316 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
321 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
339 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
344 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
349 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
354 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
359 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
364 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
370 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
375 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
380 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
385 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
390 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
395 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
400 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
405 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
410 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
415 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
420 SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
425 SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
430 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
435 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
441 SUNXI_FUNCTION(0x2, "pwm0")),
445 SUNXI_FUNCTION(0x2, "pwm1")),
449 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
453 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
457 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
461 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
465 SUNXI_FUNCTION(0x2, "spi0"), /* CS */
470 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
475 SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
480 SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
H A Dpinctrl-sun9i-a80.c25 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
31 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
37 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
43 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
49 SUNXI_FUNCTION(0x2, "gmac"), /* RXCK */
55 SUNXI_FUNCTION(0x2, "gmac"), /* RXCTL */
61 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
67 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
73 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
79 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
85 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
91 SUNXI_FUNCTION(0x2, "gmac"), /* MII-CRS */
97 SUNXI_FUNCTION(0x2, "gmac"), /* TXCK */
103 SUNXI_FUNCTION(0x2, "gmac"), /* RGMII-TXCK / GMII-TXEN */
109 SUNXI_FUNCTION(0x2, "gmac"), /* MII-TXERR */
115 SUNXI_FUNCTION(0x2, "gmac"), /* RGMII-CLKIN / MII-COL */
121 SUNXI_FUNCTION(0x2, "gmac"), /* EMDC */
127 SUNXI_FUNCTION(0x2, "gmac"), /* EMDIO */
166 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
171 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
176 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
181 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
185 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
189 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
193 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
198 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
203 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
208 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
213 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
218 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
223 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
228 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
233 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
238 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
243 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
248 SUNXI_FUNCTION(0x2, "nand0"), /* CE2 */
253 SUNXI_FUNCTION(0x2, "nand0"), /* CE3 */
264 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
269 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
274 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
279 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
284 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
289 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
294 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
299 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
304 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
309 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
314 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
319 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
324 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
329 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
334 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
339 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
344 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
349 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
354 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
359 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
364 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
368 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
372 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
376 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
380 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
384 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
388 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
392 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
398 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
404 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
410 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
416 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
422 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
429 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
436 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
443 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
450 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
456 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
462 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
468 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
474 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
480 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
486 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
492 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
498 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
504 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
512 SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
516 SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
520 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
525 SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
529 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
534 SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
540 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
545 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
550 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
555 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
560 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
565 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
570 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
575 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
580 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
585 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
590 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
595 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
600 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
605 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
610 SUNXI_FUNCTION(0x2, "uart4"), /* RTS */
615 SUNXI_FUNCTION(0x2, "uart4"), /* CTS */
622 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
626 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
630 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
634 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
638 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
642 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
646 SUNXI_FUNCTION(0x2, "pwm0")),
672 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
678 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
684 SUNXI_FUNCTION(0x2, "spi3"), /* CLK */
689 SUNXI_FUNCTION(0x2, "spi3"), /* MOSI */
694 SUNXI_FUNCTION(0x2, "spi3"), /* MISO */
699 SUNXI_FUNCTION(0x2, "spi3"), /* CS0 */
704 SUNXI_FUNCTION(0x2, "spi3"), /* CS1 */
709 SUNXI_FUNCTION(0x2, "hdmi")), /* SCL */
713 SUNXI_FUNCTION(0x2, "hdmi")), /* SDA */
717 SUNXI_FUNCTION(0x2, "hdmi")), /* CEC */
H A Dpinctrl-sun5i-a13.c26 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
30 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
34 SUNXI_FUNCTION(0x2, "pwm"),
39 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
44 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
50 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
56 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
60 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
64 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
68 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
73 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
78 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
83 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
88 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
93 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
97 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
101 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
106 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
111 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
116 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
121 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
126 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
131 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
136 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
141 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
146 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
152 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
158 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
162 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
166 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
170 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
174 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
178 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
183 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
187 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
191 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
195 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
199 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
203 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
208 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
212 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
216 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
220 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
224 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
228 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
232 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
236 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
240 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
244 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
309 SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
313 SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
317 SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */
321 SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
325 SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */
329 SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
343 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
349 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
356 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
362 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
368 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
374 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
H A Dpinctrl-sun5i-a10s.c25 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
31 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
37 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
43 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
49 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
55 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
61 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
67 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
73 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
80 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
87 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
94 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
101 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
107 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
113 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
120 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
127 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
132 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
139 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
143 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
147 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
152 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
157 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
162 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
167 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
172 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
177 SUNXI_FUNCTION(0x2, "i2s"), /* DO */
182 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
187 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
192 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
198 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
204 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
210 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
216 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
220 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
224 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
228 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
232 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
237 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
243 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
248 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
253 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
258 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
263 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
267 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
271 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
276 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
281 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
286 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
291 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
296 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
301 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
306 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
311 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
316 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
321 SUNXI_FUNCTION(0x2, "nand0"), /* NWP */
326 SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */
331 SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */
337 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
344 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
348 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
352 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
357 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
362 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
367 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
372 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
377 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
382 SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */
386 SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */
390 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
395 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
400 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
405 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
410 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
415 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
420 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
424 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
428 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
433 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
438 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
443 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
448 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
453 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
458 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
463 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
468 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
473 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
478 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
484 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
490 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
496 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
502 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
508 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
514 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
520 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
526 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
532 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
538 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
544 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
551 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
556 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
561 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
566 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
571 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
576 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
581 SUNXI_FUNCTION(0x2, "gps"), /* CLK */
585 SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
589 SUNXI_FUNCTION(0x2, "gps"), /* MAG */
594 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
600 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
606 SUNXI_FUNCTION(0x2, "mmc1"), /* DO */
612 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
619 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
625 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
631 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
637 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
643 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
649 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
655 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
H A Dpinctrl-sun4i-a10.c25 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
31 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
37 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
43 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
49 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
54 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
59 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
64 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
69 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
74 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
79 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
84 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
89 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
95 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
101 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
107 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
113 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
119 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
126 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
130 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
134 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
138 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
149 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
153 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
158 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
163 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
168 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
173 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
177 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
181 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
185 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
192 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
198 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
203 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
208 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
213 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
218 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
222 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
226 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
230 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
234 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
239 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
245 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
250 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
255 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
260 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
264 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
268 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
272 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
277 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
282 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
287 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
292 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
297 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
302 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
306 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
310 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
314 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
318 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
322 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
326 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
330 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
335 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
340 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
345 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
354 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
359 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
364 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
369 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
374 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
379 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
384 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
389 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
394 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
399 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
404 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
409 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
414 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
419 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
424 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
429 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
434 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
439 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
444 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
449 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
454 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
459 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
464 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
469 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
474 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
479 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
484 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
489 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
494 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
500 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
505 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
510 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
515 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
520 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
525 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
531 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
536 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
541 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
546 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
551 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
556 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
562 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
567 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
572 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
577 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
582 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
587 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
593 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
599 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
605 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
611 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
617 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
624 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
631 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
638 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
645 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
652 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
659 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
666 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
674 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
682 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
690 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
698 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
706 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
714 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
722 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
731 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
740 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
749 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
758 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
767 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
776 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
784 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
793 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
802 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
811 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
819 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
828 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
837 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
846 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
854 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
862 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
870 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
878 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
886 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
894 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
902 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
920 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
924 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
928 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
932 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
936 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
940 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
944 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
948 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
954 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
960 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
966 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
972 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
979 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
986 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
992 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
998 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1004 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1010 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
1016 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
H A Dpinctrl-sun7i-a20.c25 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
32 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
39 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
46 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
53 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
59 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
65 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
71 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
77 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
83 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
90 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
96 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
102 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
109 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
116 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
124 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
132 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
140 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
149 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
153 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
157 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
161 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
166 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
170 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
175 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
180 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
185 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
190 SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */
194 SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */
198 SUNXI_FUNCTION(0x2, "i2s0")), /* DO3 */
202 SUNXI_FUNCTION(0x2, "i2s0"), /* DI */
208 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
213 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
218 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
223 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
228 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
233 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
237 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
241 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
245 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
249 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
254 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
260 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
265 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
270 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
275 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
279 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
283 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
287 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
292 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
297 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
302 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
307 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
312 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
317 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
321 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
325 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
329 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
333 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
337 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
341 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
345 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
351 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
357 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
363 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
373 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
378 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
383 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
388 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
393 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
398 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
403 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
408 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
413 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
418 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
423 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
428 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
433 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
438 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
443 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
448 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
453 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
458 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
463 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
468 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
473 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
478 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
483 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
488 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
493 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
498 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
503 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
508 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
513 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
519 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
524 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
529 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
534 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
539 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
544 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
550 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
555 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
560 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
565 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
570 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
575 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
581 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
586 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
591 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
596 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
601 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
606 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
612 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
618 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
624 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
630 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
636 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
643 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
650 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
657 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
664 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
671 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
678 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
685 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
693 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
700 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
707 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
714 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
721 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
728 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
735 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
743 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
751 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
760 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
769 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
778 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
787 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
794 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
802 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
811 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
820 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
828 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
837 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
846 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
855 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
863 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
871 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
879 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
887 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
895 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
903 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
911 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
932 SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
937 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
941 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
945 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
949 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
953 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
957 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
961 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
967 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
973 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
980 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
987 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
994 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
1001 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1007 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1013 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1019 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1025 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
1031 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
H A Dpinctrl-sun6i-a31.c25 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
39 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
46 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
53 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
60 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
67 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
74 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
81 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
87 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
95 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
103 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
111 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
119 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
127 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
142 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
149 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
156 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
163 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
170 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
177 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
184 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
191 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
198 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
205 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
212 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
219 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
226 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
233 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
238 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
243 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
248 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
254 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
261 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
274 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
279 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
284 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
289 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
293 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
297 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
301 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
307 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
313 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
319 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
325 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
331 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
337 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
343 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
349 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
355 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
361 SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */
366 SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */
371 SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */
376 SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */
381 SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */
386 SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */
391 SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */
396 SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */
401 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
407 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
411 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
420 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
425 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
430 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
435 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
440 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
445 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
450 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
455 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
460 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
465 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
470 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
475 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
480 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
485 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
490 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
495 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
500 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
505 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
510 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
515 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
520 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
524 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
528 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
532 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
536 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
540 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
544 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
548 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
553 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
559 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
565 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
571 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
577 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
583 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
589 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
595 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
601 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
607 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
613 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
619 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
625 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
631 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
637 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
643 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
649 SUNXI_FUNCTION(0x2, "csi"), /* MIPI CSI MCLK */
655 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
660 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
665 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
670 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
675 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
680 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
686 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
691 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
696 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
701 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
706 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
711 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
716 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
721 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
726 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
731 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
736 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
742 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
748 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
754 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
760 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
766 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
772 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
778 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
783 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
789 SUNXI_FUNCTION(0x2, "nand1")), /* WE */
793 SUNXI_FUNCTION(0x2, "nand1")), /* ALE */
797 SUNXI_FUNCTION(0x2, "nand1")), /* CLE */
801 SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */
805 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
809 SUNXI_FUNCTION(0x2, "nand1")), /* RE */
813 SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */
817 SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */
821 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
825 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
831 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
837 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
843 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
849 SUNXI_FUNCTION(0x2, "pwm0")),
853 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
857 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
861 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
865 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
869 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
873 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
877 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
881 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
906 SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */
910 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
H A Dpinctrl-sun8i-a83t.c28 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
34 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
40 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
46 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
52 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
58 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
64 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
70 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
76 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
82 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
87 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
93 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
98 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
103 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
108 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
113 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
117 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
122 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
127 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
131 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
136 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
141 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
146 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
151 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
156 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
161 SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
166 SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
171 SUNXI_FUNCTION(0x2, "nand"), /* DQS */
176 SUNXI_FUNCTION(0x2, "nand")), /* CE2 */
180 SUNXI_FUNCTION(0x2, "nand")), /* CE3 */
185 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
190 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
195 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
200 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
205 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
210 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
215 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
220 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
225 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
230 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
235 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
240 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
245 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
251 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
257 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
263 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
269 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
275 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
281 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
286 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
291 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
296 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
301 SUNXI_FUNCTION(0x2, "pwm")), /* PWM */
309 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
314 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
319 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
324 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
329 SUNXI_FUNCTION(0x2, "csi")), /* D0 */
333 SUNXI_FUNCTION(0x2, "csi")), /* D1 */
337 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
342 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
347 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
352 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
357 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
363 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
369 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
375 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
381 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
386 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
405 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
410 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
415 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
420 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
425 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
430 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
439 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
444 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
449 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
454 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
459 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
464 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
469 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
475 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
481 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
487 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
493 SUNXI_FUNCTION(0x2, "i2s1"), /* BCLK */
499 SUNXI_FUNCTION(0x2, "i2s1"), /* LRCK */
505 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
511 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
518 SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
523 SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
528 SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
533 SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
538 SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
543 SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
548 SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */
553 SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */
558 SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */
H A Dpinctrl-sun6i-a31-r.c28 SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
33 SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
38 SUNXI_FUNCTION(0x2, "s_uart")), /* TX */
42 SUNXI_FUNCTION(0x2, "s_uart")), /* RX */
46 SUNXI_FUNCTION(0x2, "s_ir")), /* RX */
50 SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 0), /* PL_EINT0 */
55 SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 1), /* PL_EINT1 */
60 SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 2), /* PL_EINT2 */
65 SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 3), /* PL_EINT3 */
71 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 0)), /* PM_EINT0 */
75 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 1)), /* PM_EINT1 */
79 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 2), /* PM_EINT2 */
84 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 3)), /* PM_EINT3 */
88 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 4)), /* PM_EINT4 */
92 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 5)), /* PM_EINT5 */
96 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 6)), /* PM_EINT6 */
100 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 7), /* PM_EINT7 */
H A Dpinctrl-sun8i-a23-r.c31 SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
37 SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
43 SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
48 SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
73 SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
78 SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
83 SUNXI_FUNCTION(0x2, "s_pwm"),
/linux-4.4.14/arch/arm64/kvm/
H A Dvgic-v2-switch.S39 /* Get VGIC VCTRL base into x2 */
40 ldr x2, [x0, #VCPU_KVM]
41 kern_hyp_va x2
42 ldr x2, [x2, #KVM_VGIC_VCTRL]
43 kern_hyp_va x2
44 cbz x2, 2f // disabled
50 ldr w5, [x2, #GICH_VMCR]
51 ldr w6, [x2, #GICH_MISR]
52 ldr w7, [x2, #GICH_EISR0]
53 ldr w8, [x2, #GICH_EISR1]
54 ldr w9, [x2, #GICH_ELRSR0]
55 ldr w10, [x2, #GICH_ELRSR1]
56 ldr w11, [x2, #GICH_APR]
78 str wzr, [x2, #GICH_HCR]
81 add x2, x2, #GICH_LR0
84 1: ldr w5, [x2], #4
99 /* Get VGIC VCTRL base into x2 */
100 ldr x2, [x0, #VCPU_KVM]
101 kern_hyp_va x2
102 ldr x2, [x2, #KVM_VGIC_VCTRL]
103 kern_hyp_va x2
104 cbz x2, 2f // disabled
117 str w4, [x2, #GICH_HCR]
118 str w5, [x2, #GICH_VMCR]
119 str w6, [x2, #GICH_APR]
122 add x2, x2, #GICH_LR0
127 str w5, [x2], #4
H A Dhyp.S43 // x2: base address for cpu context
46 add x3, x2, #CPU_XREG_OFFSET(19)
65 str x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
66 str x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
67 str x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
71 // x2: base address for cpu context
74 ldr x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
75 ldr x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
76 ldr x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
82 add x3, x2, #CPU_XREG_OFFSET(31) // SP_EL0
90 add x3, x2, #CPU_XREG_OFFSET(19)
108 // x2: cpu context address
110 add x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
115 // x2: cpu context address
117 add x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
124 // x2 is the cpu context
129 add x3, x2, #CPU_XREG_OFFSET(4)
139 pop x6, x7 // x2, x3
142 add x3, x2, #CPU_XREG_OFFSET(0)
151 // x2 is the cpu context
155 add x3, x2, #CPU_XREG_OFFSET(0)
175 pop x2, x3
192 // x2: base address for cpu context
195 add x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
282 // x2: base address for cpu context
285 add x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
423 add x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
431 add x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
449 add x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
457 add x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
469 ldr x2, [x0, #VCPU_HCR_EL2]
478 tbnz x2, #HCR_RW_SHIFT, 99f // open code skip_32bit_state
483 msr hcr_el2, x2
484 mov x2, #CPTR_EL2_TTA
485 orr x2, x2, #CPTR_EL2_TFP
486 msr cptr_el2, x2
488 mov x2, #(1 << 15) // Trap CP15 Cr=15
489 msr hstr_el2, x2
492 ldr x2, [x0, #VCPU_MDCR_EL2]
493 msr mdcr_el2, x2
497 mov x2, #HCR_RW
498 msr hcr_el2, x2
501 mrs x2, mdcr_el2
502 and x2, x2, #MDCR_EL2_HPMN_MASK
503 msr mdcr_el2, x2
509 ldr x2, [x1, #KVM_VTTBR]
510 msr vttbr_el2, x2
551 ldr x2, [x0, #VCPU_KVM]
552 kern_hyp_va x2
553 ldr w3, [x2, #KVM_TIMER_ENABLED]
570 mrs x2, cnthctl_el2
571 orr x2, x2, #3
572 msr cnthctl_el2, x2
582 mrs x2, cnthctl_el2
583 orr x2, x2, #1
584 bic x2, x2, #2
585 msr cnthctl_el2, x2
587 ldr x2, [x0, #VCPU_KVM]
588 kern_hyp_va x2
589 ldr w3, [x2, #KVM_TIMER_ENABLED]
592 ldr x3, [x2, #KVM_TIMER_CNTVOFF]
594 ldr x2, [x0, #VCPU_TIMER_CNTV_CVAL]
595 msr cntv_cval_el0, x2
599 and x2, x2, #3
600 msr cntv_ctl_el0, x2
614 // x2: ptr to CPU context
638 str x21, [x2, #CPU_SYSREG_OFFSET(MDCCINT_EL1)]
643 // x2: ptr to CPU context
666 ldr x21, [x2, #CPU_SYSREG_OFFSET(MDCCINT_EL1)]
684 mrs x2, cptr_el2
685 bic x2, x2, #CPTR_EL2_TFP
686 msr cptr_el2, x2
691 ldr x2, [x0, #VCPU_HOST_CONTEXT]
692 kern_hyp_va x2
695 add x2, x0, #VCPU_CONTEXT
699 ldr x4, [x2, #CPU_SYSREG_OFFSET(FPEXC32_EL2)]
703 pop x2, x3
717 * In both cases, x2 points to the CPU context we're saving/restoring from/to.
724 ldr x2, [x0, #VCPU_HOST_CONTEXT]
725 kern_hyp_va x2
741 add x2, x0, #VCPU_CONTEXT
763 add x2, x0, #VCPU_CONTEXT
783 ldr x2, [x0, #VCPU_HOST_CONTEXT]
784 kern_hyp_va x2
810 ldr x2, [x0, #KVM_VTTBR]
811 msr vttbr_el2, x2
846 ldr x2, [x0, #KVM_VTTBR]
847 msr vttbr_el2, x2
882 ldr x2, [x0, #VCPU_HOST_CONTEXT]
883 kern_hyp_va x2
891 ldr x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
897 ldp x2, x3, [x1]
898 sub x0, x0, x2
901 mrs x2, elr_el2
934 * passed as x0, x1, and x2 (a maximum of 3 arguments in addition to the
971 push x2, x3
974 lsr x2, x1, #ESR_ELx_EC_SHIFT
976 cmp x2, #ESR_ELx_EC_HVC64
983 pop x2, x3
999 mov x1, x2
1000 mov x2, x3
1009 * x2: ESR_EC
1013 cmp x2, #ESR_ELx_EC_FP_ASIMD
1016 cmp x2, #ESR_ELx_EC_DABT_LOW
1018 ccmp x2, x0, #4, ne
1023 and x2, x1, #ESR_ELx_FSC_TYPE
1024 cmp x2, #FSC_PERM
1049 mrs x2, far_el2
1050 at s1e1r, x2
1063 mrs x2, far_el2
1067 str x2, [x0, #VCPU_FAR_EL2]
1078 3: pop x2, x3
1085 push x2, x3
/linux-4.4.14/drivers/pinctrl/berlin/
H A Dberlin-bg2.c25 BERLIN_PINCTRL_GROUP("G1", 0x00, 0x2, 0x01,
28 BERLIN_PINCTRL_FUNCTION(0x2, "usb1")),
29 BERLIN_PINCTRL_GROUP("G2", 0x00, 0x2, 0x02,
32 BERLIN_PINCTRL_FUNCTION(0x2, "pwm"),
34 BERLIN_PINCTRL_GROUP("G3", 0x00, 0x2, 0x04,
37 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
39 BERLIN_PINCTRL_GROUP("G4", 0x00, 0x2, 0x06,
42 BERLIN_PINCTRL_FUNCTION(0x2, "pwm")),
46 BERLIN_PINCTRL_FUNCTION(0x2, "et"),
54 BERLIN_PINCTRL_GROUP("G6", 0x00, 0x2, 0x0b,
57 BERLIN_PINCTRL_FUNCTION(0x2, "et")),
61 BERLIN_PINCTRL_FUNCTION(0x2, "et"),
66 BERLIN_PINCTRL_FUNCTION(0x2, "et"),
73 BERLIN_PINCTRL_FUNCTION(0x2, "et"),
77 BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x16,
80 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
82 BERLIN_PINCTRL_GROUP("G11", 0x00, 0x2, 0x18,
85 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
90 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"),
97 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"),
103 BERLIN_PINCTRL_GROUP("G15", 0x04, 0x2, 0x04,
105 BERLIN_PINCTRL_FUNCTION(0x2, "et"),
110 BERLIN_PINCTRL_FUNCTION(0x2, "fp")),
114 BERLIN_PINCTRL_FUNCTION(0x2, "fp")),
127 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
134 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
140 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
144 BERLIN_PINCTRL_GROUP("G24", 0x04, 0x2, 0x18,
147 BERLIN_PINCTRL_GROUP("G25", 0x04, 0x2, 0x1a,
150 BERLIN_PINCTRL_FUNCTION(0x2, "i2s2")),
157 BERLIN_PINCTRL_GROUP("G28", 0x04, 0x2, 0x1e,
159 BERLIN_PINCTRL_FUNCTION(0x2, "sp")),
164 BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00,
167 BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
168 BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02,
171 BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
172 BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04,
175 BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06,
178 BERLIN_PINCTRL_FUNCTION(0x2, "uart2"), /* RX/TX */
180 BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x2, 0x08,
183 BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x2, 0x0a,
186 BERLIN_PINCTRL_FUNCTION(0x2, "irda1"),
188 BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x2, 0x0c,
H A Dberlin-bg2cd.c25 BERLIN_PINCTRL_FUNCTION(0x2, "led"),
35 BERLIN_PINCTRL_FUNCTION(0x2, "fe"),
42 BERLIN_PINCTRL_FUNCTION(0x2, "twsi2"),
50 BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"),
58 BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"),
69 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
77 BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x1e,
80 BERLIN_PINCTRL_GROUP("G11", 0x04, 0x2, 0x00,
89 BERLIN_PINCTRL_FUNCTION(0x2, "usb1_dbg")),
100 BERLIN_PINCTRL_GROUP("G18", 0x04, 0x2, 0x12,
102 BERLIN_PINCTRL_GROUP("G19", 0x04, 0x2, 0x14,
104 BERLIN_PINCTRL_GROUP("G20", 0x04, 0x2, 0x16,
112 BERLIN_PINCTRL_GROUP("G24", 0x08, 0x2, 0x03,
114 BERLIN_PINCTRL_GROUP("G25", 0x08, 0x2, 0x05,
118 BERLIN_PINCTRL_GROUP("G27", 0x08, 0x2, 0x08,
128 BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00,
130 BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02,
132 BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04,
134 BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06,
136 BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x2, 0x08,
138 BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x2, 0x0a,
140 BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x2, 0x0c,
H A Dberlin-bg2q.c25 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
28 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
31 BERLIN_PINCTRL_FUNCTION(0x2, "arc"),
35 BERLIN_PINCTRL_FUNCTION(0x2, "i2s2"),
40 BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
48 BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
55 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
59 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
77 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
87 BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
112 BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
119 BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
124 BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
130 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
142 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
146 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
149 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
154 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
160 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
166 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
170 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
173 BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
179 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
183 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
187 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
191 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
196 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
201 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
206 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
213 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
219 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
225 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
230 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
235 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
240 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
245 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
250 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
255 BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
262 BERLIN_PINCTRL_FUNCTION(0x2, "i2s1")),
269 BERLIN_PINCTRL_FUNCTION(0x2, "i2s1")),
277 BERLIN_PINCTRL_FUNCTION(0x2, "i2s1"),
284 BERLIN_PINCTRL_FUNCTION(0x2, "i2s1"),
292 BERLIN_PINCTRL_FUNCTION(0x2, "arc")),
302 BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00,
305 BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
306 BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02,
309 BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
310 BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04,
313 BERLIN_PINCTRL_FUNCTION(0x2, "eddc")),
314 BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06,
317 BERLIN_PINCTRL_FUNCTION(0x2, "eddc")),
342 BERLIN_PINCTRL_GROUP("GSM12", 0x40, 0x2, 0x10,
345 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
346 BERLIN_PINCTRL_GROUP("GSM13", 0x40, 0x2, 0x12,
349 BERLIN_PINCTRL_FUNCTION(0x2, "uart1"), /* RX/TX */
351 BERLIN_PINCTRL_GROUP("GSM14", 0x40, 0x2, 0x14,
354 BERLIN_PINCTRL_FUNCTION(0x2, "irda1"),
356 BERLIN_PINCTRL_GROUP("GSM15", 0x40, 0x2, 0x16,
359 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
H A Dberlin-bg4ct.c35 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CLK */
40 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CDn */
45 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT0 */
50 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT1 */
55 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT2 */
60 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT3 */
65 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CMD */
70 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* WP */
102 BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* CLK */
108 BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* SOP */
114 BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* SD */
120 BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* VALD */
126 BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* CLK */
132 BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* SOP */
138 BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* SD */
144 BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* VALD */
150 BERLIN_PINCTRL_FUNCTION(0x2, "cpupll"), /* CLKO */
156 BERLIN_PINCTRL_FUNCTION(0x2, "syspll"), /* CLKO */
162 BERLIN_PINCTRL_FUNCTION(0x2, "mempll"), /* CLKO */
173 BERLIN_PINCTRL_FUNCTION(0x2, "pwm0"),
179 BERLIN_PINCTRL_FUNCTION(0x2, "pwm1"),
185 BERLIN_PINCTRL_FUNCTION(0x2, "pwm2"),
191 BERLIN_PINCTRL_FUNCTION(0x2, "pwm3"),
205 BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* DIO */
210 BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* CLK */
215 BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* DEN */
224 BERLIN_PINCTRL_FUNCTION(0x2, "sts2")), /* CLK */
228 BERLIN_PINCTRL_FUNCTION(0x2, "sts2"), /* SOP */
233 BERLIN_PINCTRL_FUNCTION(0x2, "sts2"), /* SD */
238 BERLIN_PINCTRL_FUNCTION(0x2, "sts2")), /* VALD */
242 BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* CLK */
246 BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* SOP */
250 BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* SD */
254 BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* VALD */
267 BERLIN_PINCTRL_FUNCTION(0x2, "tw1")), /* SCL */
271 BERLIN_PINCTRL_FUNCTION(0x2, "tw1")), /* SDA */
303 BERLIN_PINCTRL_FUNCTION(0x2, "avpll"), /* CLKO */
313 BERLIN_PINCTRL_FUNCTION(0x2, "pwm0"),
320 BERLIN_PINCTRL_FUNCTION(0x2, "pwm1"),
327 BERLIN_PINCTRL_FUNCTION(0x2, "pwm2"),
335 BERLIN_PINCTRL_FUNCTION(0x2, "pwm3"),
358 BERLIN_PINCTRL_FUNCTION(0x2, "pwm0")),
362 BERLIN_PINCTRL_FUNCTION(0x2, "pwm1")),
375 BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* RXCLK */
393 BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* MDC */
400 BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* MDIO */
414 BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED0 */
418 BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED1 */
421 BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED2 */
/linux-4.4.14/arch/arm64/lib/
H A Dbitops.S32 mov x2, #1
35 lsl x3, x2, x3 // Create mask
37 alt_lse "1: ldxr x2, [x1]", "\lse x3, [x1]"
38 alt_lse " \llsc x2, x2, x3", "nop"
39 alt_lse " stxr w0, x2, [x1]", "nop"
50 mov x2, #1
53 lsl x4, x2, x3 // Create mask
55 alt_lse "1: ldxr x2, [x1]", "\lse x4, x2, [x1]"
56 lsr x0, x2, x3
57 alt_lse " \llsc x2, x2, x4", "nop"
58 alt_lse " stlxr w5, x2, [x1]", "nop"
/linux-4.4.14/crypto/
H A Dserpent_generic.c36 #define loadkeys(x0, x1, x2, x3, i) \
37 ({ x0 = k[i]; x1 = k[i+1]; x2 = k[i+2]; x3 = k[i+3]; })
39 #define storekeys(x0, x1, x2, x3, i) \
40 ({ k[i] = x0; k[i+1] = x1; k[i+2] = x2; k[i+3] = x3; })
42 #define store_and_load_keys(x0, x1, x2, x3, s, l) \
43 ({ storekeys(x0, x1, x2, x3, s); loadkeys(x0, x1, x2, x3, l); })
45 #define K(x0, x1, x2, x3, i) ({ \
46 x3 ^= k[4*(i)+3]; x2 ^= k[4*(i)+2]; \
50 #define LK(x0, x1, x2, x3, x4, i) ({ \
52 x2 = rol32(x2, 3); x1 ^= x0; x4 = x0 << 3; \
53 x3 ^= x2; x1 ^= x2; \
56 x0 ^= x1; x4 <<= 7; x2 ^= x3; \
57 x0 ^= x3; x2 ^= x4; x3 ^= k[4*i+3]; \
58 x1 ^= k[4*i+1]; x0 = rol32(x0, 5); x2 = rol32(x2, 22);\
59 x0 ^= k[4*i+0]; x2 ^= k[4*i+2]; \
62 #define KL(x0, x1, x2, x3, x4, i) ({ \
63 x0 ^= k[4*i+0]; x1 ^= k[4*i+1]; x2 ^= k[4*i+2]; \
64 x3 ^= k[4*i+3]; x0 = ror32(x0, 5); x2 = ror32(x2, 22);\
65 x4 = x1; x2 ^= x3; x0 ^= x3; \
67 x2 ^= x4; x3 = ror32(x3, 7); x4 = x0 << 3; \
69 x1 ^= x2; x3 ^= x2; x2 = ror32(x2, 3); \
72 #define S0(x0, x1, x2, x3, x4) ({ \
74 x3 |= x0; x0 ^= x4; x4 ^= x2; \
76 x1 ^= x4; x2 ^= x0; x0 ^= x3; \
77 x4 |= x0; x0 ^= x2; x2 &= x1; \
78 x3 ^= x2; x1 = ~x1; x2 ^= x4; \
79 x1 ^= x2; \
82 #define S1(x0, x1, x2, x3, x4) ({ \
85 x4 &= x1; x0 |= x1; x3 ^= x2; \
87 x1 |= x4; x4 ^= x2; x2 &= x0; \
88 x2 ^= x1; x1 |= x0; x0 = ~x0; \
89 x0 ^= x2; x4 ^= x1; \
92 #define S2(x0, x1, x2, x3, x4) ({ \
94 x1 ^= x0; x4 = x0; x0 &= x2; \
95 x0 ^= x3; x3 |= x4; x2 ^= x1; \
96 x3 ^= x1; x1 &= x0; x0 ^= x2; \
97 x2 &= x3; x3 |= x1; x0 = ~x0; \
98 x3 ^= x0; x4 ^= x0; x0 ^= x2; \
99 x1 |= x2; \
102 #define S3(x0, x1, x2, x3, x4) ({ \
105 x0 ^= x2; x2 ^= x1; x1 &= x3; \
106 x2 ^= x3; x0 |= x4; x4 ^= x3; \
108 x3 ^= x2; x4 |= x1; x2 &= x1; \
109 x4 ^= x3; x0 ^= x3; x3 ^= x2; \
112 #define S4(x0, x1, x2, x3, x4) ({ \
115 x3 ^= x2; x2 |= x4; x0 ^= x1; \
116 x4 ^= x3; x2 |= x0; \
117 x2 ^= x1; x1 &= x0; \
118 x1 ^= x4; x4 &= x2; x2 ^= x3; \
123 #define S5(x0, x1, x2, x3, x4) ({ \
125 x2 ^= x1; x3 = ~x3; x4 ^= x0; \
126 x0 ^= x2; x1 &= x4; x4 |= x3; \
128 x3 ^= x2; x0 ^= x1; x2 &= x4; \
129 x1 ^= x2; x2 &= x0; \
130 x3 ^= x2; \
133 #define S6(x0, x1, x2, x3, x4) ({ \
135 x3 ^= x0; x1 ^= x2; x2 ^= x0; \
137 x0 ^= x1; x1 ^= x2; \
138 x3 ^= x4; x4 ^= x0; x2 &= x0; \
139 x4 ^= x1; x2 ^= x3; x3 &= x1; \
140 x3 ^= x0; x1 ^= x2; \
143 #define S7(x0, x1, x2, x3, x4) ({ \
145 x4 = x1; x0 = ~x0; x1 &= x2; \
146 x1 ^= x3; x3 |= x4; x4 ^= x2; \
147 x2 ^= x3; x3 ^= x0; x0 |= x1; \
148 x2 &= x0; x0 ^= x4; x4 ^= x3; \
150 x2 ^= x4; x3 ^= x1; x4 |= x0; \
154 #define SI0(x0, x1, x2, x3, x4) ({ \
157 x2 ^= x3; x3 ^= x0; x0 &= x1; \
158 x0 ^= x2; x2 &= x3; x3 ^= x4; \
159 x2 ^= x3; x1 ^= x3; x3 &= x0; \
160 x1 ^= x0; x0 ^= x2; x4 ^= x3; \
163 #define SI1(x0, x1, x2, x3, x4) ({ \
165 x0 ^= x2; x2 = ~x2; x4 |= x1; \
166 x4 ^= x3; x3 &= x1; x1 ^= x2; \
167 x2 &= x4; x4 ^= x1; x1 |= x3; \
168 x3 ^= x0; x2 ^= x0; x0 |= x4; \
169 x2 ^= x4; x1 ^= x0; \
173 #define SI2(x0, x1, x2, x3, x4) ({ \
174 x2 ^= x1; x4 = x3; x3 = ~x3; \
175 x3 |= x2; x2 ^= x4; x4 ^= x0; \
176 x3 ^= x1; x1 |= x2; x2 ^= x0; \
177 x1 ^= x4; x4 |= x3; x2 ^= x3; \
178 x4 ^= x2; x2 &= x1; \
179 x2 ^= x3; x3 ^= x4; x4 ^= x0; \
182 #define SI3(x0, x1, x2, x3, x4) ({ \
183 x2 ^= x1; \
184 x4 = x1; x1 &= x2; \
186 x0 ^= x3; x3 |= x1; x1 ^= x2; \
187 x1 ^= x3; x0 ^= x2; x2 ^= x3; \
188 x3 &= x1; x1 ^= x0; x0 &= x2; \
192 #define SI4(x0, x1, x2, x3, x4) ({ \
193 x2 ^= x3; x4 = x0; x0 &= x1; \
194 x0 ^= x2; x2 |= x3; x4 = ~x4; \
195 x1 ^= x0; x0 ^= x2; x2 &= x4; \
196 x2 ^= x0; x0 |= x4; \
197 x0 ^= x3; x3 &= x2; \
202 #define SI5(x0, x1, x2, x3, x4) ({ \
203 x4 = x1; x1 |= x2; \
204 x2 ^= x4; x1 ^= x3; x3 &= x4; \
205 x2 ^= x3; x3 |= x0; x0 = ~x0; \
206 x3 ^= x2; x2 |= x0; x4 ^= x1; \
207 x2 ^= x4; x4 &= x0; x0 ^= x1; \
208 x1 ^= x3; x0 &= x2; x2 ^= x3; \
209 x0 ^= x2; x2 ^= x4; x4 ^= x3; \
212 #define SI6(x0, x1, x2, x3, x4) ({ \
213 x0 ^= x2; \
214 x4 = x0; x0 &= x3; x2 ^= x3; \
215 x0 ^= x2; x3 ^= x1; x2 |= x4; \
216 x2 ^= x3; x3 &= x0; x0 = ~x0; \
217 x3 ^= x1; x1 &= x2; x4 ^= x0; \
218 x3 ^= x4; x4 ^= x2; x0 ^= x1; \
219 x2 ^= x0; \
222 #define SI7(x0, x1, x2, x3, x4) ({ \
223 x4 = x3; x3 &= x0; x0 ^= x2; \
224 x2 |= x4; x4 ^= x1; x0 = ~x0; \
225 x1 |= x3; x4 ^= x0; x0 &= x2; \
226 x0 ^= x1; x1 &= x2; x3 ^= x2; \
227 x4 ^= x3; x2 &= x3; x3 |= x0; \
229 x4 ^= x2; \
H A Dseed.c337 u32 i, t0, t1, x1, x2, x3, x4; seed_set_key() local
340 x2 = be32_to_cpu(key[1]); seed_set_key()
346 t1 = x2 + KC[i] - x4; seed_set_key()
354 x1 = (x1 >> 8) ^ (x2 << 24); seed_set_key()
355 x2 = (x2 >> 8) ^ (t0 << 24); seed_set_key()
373 u32 x1, x2, x3, x4, t0, t1; seed_encrypt() local
377 x2 = be32_to_cpu(src[1]); seed_encrypt()
381 OP(x1, x2, x3, x4, 0); seed_encrypt()
382 OP(x3, x4, x1, x2, 2); seed_encrypt()
383 OP(x1, x2, x3, x4, 4); seed_encrypt()
384 OP(x3, x4, x1, x2, 6); seed_encrypt()
385 OP(x1, x2, x3, x4, 8); seed_encrypt()
386 OP(x3, x4, x1, x2, 10); seed_encrypt()
387 OP(x1, x2, x3, x4, 12); seed_encrypt()
388 OP(x3, x4, x1, x2, 14); seed_encrypt()
389 OP(x1, x2, x3, x4, 16); seed_encrypt()
390 OP(x3, x4, x1, x2, 18); seed_encrypt()
391 OP(x1, x2, x3, x4, 20); seed_encrypt()
392 OP(x3, x4, x1, x2, 22); seed_encrypt()
393 OP(x1, x2, x3, x4, 24); seed_encrypt()
394 OP(x3, x4, x1, x2, 26); seed_encrypt()
395 OP(x1, x2, x3, x4, 28); seed_encrypt()
396 OP(x3, x4, x1, x2, 30); seed_encrypt()
401 dst[3] = cpu_to_be32(x2); seed_encrypt()
411 u32 x1, x2, x3, x4, t0, t1; seed_decrypt() local
415 x2 = be32_to_cpu(src[1]); seed_decrypt()
419 OP(x1, x2, x3, x4, 30); seed_decrypt()
420 OP(x3, x4, x1, x2, 28); seed_decrypt()
421 OP(x1, x2, x3, x4, 26); seed_decrypt()
422 OP(x3, x4, x1, x2, 24); seed_decrypt()
423 OP(x1, x2, x3, x4, 22); seed_decrypt()
424 OP(x3, x4, x1, x2, 20); seed_decrypt()
425 OP(x1, x2, x3, x4, 18); seed_decrypt()
426 OP(x3, x4, x1, x2, 16); seed_decrypt()
427 OP(x1, x2, x3, x4, 14); seed_decrypt()
428 OP(x3, x4, x1, x2, 12); seed_decrypt()
429 OP(x1, x2, x3, x4, 10); seed_decrypt()
430 OP(x3, x4, x1, x2, 8); seed_decrypt()
431 OP(x1, x2, x3, x4, 6); seed_decrypt()
432 OP(x3, x4, x1, x2, 4); seed_decrypt()
433 OP(x1, x2, x3, x4, 2); seed_decrypt()
434 OP(x3, x4, x1, x2, 0); seed_decrypt()
439 dst[3] = cpu_to_be32(x2); seed_decrypt()
/linux-4.4.14/arch/arm/mach-dove/
H A Dmpp.h11 #define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0)
16 #define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0)
22 #define MPP2_UA2_TXD MPP(2, 0x2, 0, 0)
28 #define MPP3_UA2_RXD MPP(3, 0x2, 0, 0)
34 #define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0)
39 #define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0)
44 #define MPP6_UA3_TXD MPP(6, 0x2, 0, 0)
49 #define MPP7_UA3_RXD MPP(7, 0x2, 0, 0)
64 #define MPP11_SATA_ACT MPP(11, 0x2, 0, 0)
71 #define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0)
76 #define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0)
82 #define MPP14_UA2_TXD MPP(14, 0x2, 0, 0)
87 #define MPP15_UA2_RXD MPP(15, 0x2, 0, 0)
92 #define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0)
99 #define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0)
105 #define MPP18_UA3_TXD MPP(18, 0x2, 0, 0)
111 #define MPP19_UA3_RXD MPP(19, 0x2, 0, 0)
117 #define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0)
124 #define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0)
132 #define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0)
139 #define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0)
184 #define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2
/linux-4.4.14/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-370.c48 MPP_FUNCTION(0x2, "uart0", "txd")),
52 MPP_FUNCTION(0x2, "uart0", "rxd")),
59 MPP_FUNCTION(0x2, "uart1", "txd"),
65 MPP_FUNCTION(0x2, "sata0", "prsnt"),
76 MPP_FUNCTION(0x2, "uart0", "rts"),
82 MPP_FUNCTION(0x2, "uart1", "txd"),
88 MPP_FUNCTION(0x2, "uart0", "cts"),
94 MPP_FUNCTION(0x2, "uart1", "rxd"),
102 MPP_FUNCTION(0x2, "i2c1", "sda"),
109 MPP_FUNCTION(0x2, "i2c1", "sck"),
116 MPP_FUNCTION(0x2, "pcie", "clkreq0"),
123 MPP_FUNCTION(0x2, "pcie", "clkreq1"),
130 MPP_FUNCTION(0x2, "uart1", "rxd"),
142 MPP_FUNCTION(0x2, "ge1", "txclkout"),
147 MPP_FUNCTION(0x2, "ge1", "txd0")),
151 MPP_FUNCTION(0x2, "ge1", "txd1"),
156 MPP_FUNCTION(0x2, "ge1", "txd2"),
161 MPP_FUNCTION(0x2, "ge1", "txd3"),
166 MPP_FUNCTION(0x2, "ge1", "txctl"),
171 MPP_FUNCTION(0x2, "ge1", "rxd0"),
176 MPP_FUNCTION(0x2, "ge1", "rxd1"),
181 MPP_FUNCTION(0x2, "ge1", "rxd2"),
186 MPP_FUNCTION(0x2, "ge1", "rxd3")),
190 MPP_FUNCTION(0x2, "ge1", "rxctl"),
195 MPP_FUNCTION(0x2, "ge1", "rxclk"),
207 MPP_FUNCTION(0x2, "spi0", "cs0")),
211 MPP_FUNCTION(0x2, "spi0", "mosi")),
215 MPP_FUNCTION(0x2, "spi0", "sck")),
219 MPP_FUNCTION(0x2, "spi0", "miso")),
223 MPP_FUNCTION(0x2, "sata0", "prsnt")),
227 MPP_FUNCTION(0x2, "uart1", "cts"),
232 MPP_FUNCTION(0x2, "audio", "spdifo")),
236 MPP_FUNCTION(0x2, "uart1", "rts"),
241 MPP_FUNCTION(0x2, "uart1", "rxd")),
245 MPP_FUNCTION(0x2, "uart1", "txd")),
249 MPP_FUNCTION(0x2, "audio", "bclk")),
253 MPP_FUNCTION(0x2, "audio", "mclk")),
257 MPP_FUNCTION(0x2, "audio", "lrclk")),
261 MPP_FUNCTION(0x2, "audio", "sdo")),
270 MPP_FUNCTION(0x2, "uart0", "rts"),
277 MPP_FUNCTION(0x2, "pcie", "clkreq1"),
284 MPP_FUNCTION(0x2, "uart0", "cts"),
291 MPP_FUNCTION(0x2, "i2c1", "sda"),
297 MPP_FUNCTION(0x2, "i2c1", "sck"),
303 MPP_FUNCTION(0x2, "sd0", "clk"),
314 MPP_FUNCTION(0x2, "uart1", "txd"),
321 MPP_FUNCTION(0x2, "uart1", "cts"),
329 MPP_FUNCTION(0x2, "uart1", "rxd"),
336 MPP_FUNCTION(0x2, "uart1", "rts"),
343 MPP_FUNCTION(0x2, "uart1", "rts"),
349 MPP_FUNCTION(0x2, "uart1", "rxd"),
356 MPP_FUNCTION(0x2, "uart1", "txd"),
361 MPP_FUNCTION(0x2, "uart1", "cts"),
369 MPP_FUNCTION(0x2, "tclk", NULL)),
373 MPP_FUNCTION(0x2, "spi0", "cs1")),
377 MPP_FUNCTION(0x2, "spi0", "cs2")),
H A Dpinctrl-armada-375.c42 MPP_FUNCTION(0x2, "spi0", "cs1"),
48 MPP_FUNCTION(0x2, "spi0", "mosi"),
54 MPP_FUNCTION(0x2, "ptp", "evreq"),
62 MPP_FUNCTION(0x2, "ptp", "trig"),
70 MPP_FUNCTION(0x2, "spi0", "miso"),
76 MPP_FUNCTION(0x2, "spi0", "cs2"),
89 MPP_FUNCTION(0x2, "ptp", "clk"),
96 MPP_FUNCTION(0x2, "spi0", "cs0"),
101 MPP_FUNCTION(0x2, "spi0", "sck"),
106 MPP_FUNCTION(0x2, "dram", "vttctrl"),
124 MPP_FUNCTION(0x2, "pcie0", "rstout"),
130 MPP_FUNCTION(0x2, "i2c0", "sda"),
134 MPP_FUNCTION(0x2, "i2c0", "sck"),
138 MPP_FUNCTION(0x2, "uart0", "txd")),
141 MPP_FUNCTION(0x2, "uart0", "rxd")),
144 MPP_FUNCTION(0x2, "tdm", "int")),
147 MPP_FUNCTION(0x2, "tdm", "rst")),
150 MPP_FUNCTION(0x2, "tdm", "pclk")),
153 MPP_FUNCTION(0x2, "tdm", "fsync")),
156 MPP_FUNCTION(0x2, "tdm", "drx")),
159 MPP_FUNCTION(0x2, "tdm", "dtx")),
163 MPP_FUNCTION(0x2, "ge1", "rxd0"),
171 MPP_FUNCTION(0x2, "ge1", "rxd1"),
179 MPP_FUNCTION(0x2, "ge1", "rxd2"),
187 MPP_FUNCTION(0x2, "ge1", "rxd3"),
195 MPP_FUNCTION(0x2, "ge1", "txctl"),
201 MPP_FUNCTION(0x2, "ge1", "rxclk"),
207 MPP_FUNCTION(0x2, "ge1", "txd0"),
213 MPP_FUNCTION(0x2, "ge1", "txd1"),
218 MPP_FUNCTION(0x2, "ge1", "txd2"),
224 MPP_FUNCTION(0x2, "ge1", "txd3"),
229 MPP_FUNCTION(0x2, "ge1", "txclkout"),
234 MPP_FUNCTION(0x2, "ge1", "rxctl"),
245 MPP_FUNCTION(0x2, "tdm", "int"),
270 MPP_FUNCTION(0x2, "sata0", "prsnt"),
278 MPP_FUNCTION(0x2, "spi0", "cs2"),
285 MPP_FUNCTION(0x2, "ge0", "txd0"),
291 MPP_FUNCTION(0x2, "ge0", "txd1"),
298 MPP_FUNCTION(0x2, "ge0", "txd2"),
304 MPP_FUNCTION(0x2, "ge0", "txd3"),
310 MPP_FUNCTION(0x2, "ge0", "rxd0"),
317 MPP_FUNCTION(0x2, "ge0", "rxd1"),
323 MPP_FUNCTION(0x2, "ge0", "rxd2"),
330 MPP_FUNCTION(0x2, "ge0", "rxd3"),
337 MPP_FUNCTION(0x2, "ge0", "rxctl"),
342 MPP_FUNCTION(0x2, "ge0", "rxclk"),
347 MPP_FUNCTION(0x2, "ge0", "txclkout"),
352 MPP_FUNCTION(0x2, "ge0", "txctl"),
363 MPP_FUNCTION(0x2, "uart1", "txd"),
369 MPP_FUNCTION(0x2, "uart1", "rxd"),
380 MPP_FUNCTION(0x2, "ptp", "trig"),
385 MPP_FUNCTION(0x2, "dram", "vttctrl"),
392 MPP_FUNCTION(0x2, "ptp", "evreq"),
H A Dpinctrl-kirkwood.c53 MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1))),
57 MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1, 1))),
61 MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1))),
65 MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1))),
69 MPP_VAR_FUNCTION(0x2, "uart0", "rxd", V(1, 1, 1, 1, 1, 1)),
76 MPP_VAR_FUNCTION(0x2, "uart0", "txd", V(1, 1, 1, 1, 1, 1)),
82 MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1, 1)),
87 MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1)),
93 MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1)),
102 MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1)),
109 MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1)),
115 MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1)),
145 MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1)),
152 MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1)),
166 MPP_VAR_FUNCTION(0x2, "pex", "clkreq", V(0, 0, 0, 0, 1, 0))),
173 MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)),
182 MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1, 0)),
191 MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1, 0)),
200 MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1, 0)),
209 MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1, 0)),
217 MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1, 0)),
225 MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1, 0)),
233 MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1, 0)),
241 MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1, 0)),
249 MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1, 0)),
256 MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 1, 1, 1, 0)),
262 MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 1, 1, 1, 0)),
268 MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 1, 1, 1, 0)),
273 MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1, 0)),
278 MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 1, 1, 1, 0)),
284 MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)),
292 MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1, 0)),
298 MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1, 0)),
304 MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1, 0)),
310 MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1, 0)),
316 MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1, 0)),
322 MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1, 0)),
328 MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1, 0)),
334 MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1, 0)),
340 MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1, 0)),
346 MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 0, 1, 1, 0)),
351 MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 0, 1, 1, 0)),
356 MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 0, 1, 1, 0)),
361 MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 0, 1, 1, 0)),
367 MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 0, 1, 1, 0)),
H A Dpinctrl-armada-xp.c106 MPP_VAR_FUNCTION(0x2, "ge1", "txclkout", V_MV78230_PLUS),
111 MPP_VAR_FUNCTION(0x2, "ge1", "txd0", V_MV78230_PLUS),
117 MPP_VAR_FUNCTION(0x2, "ge1", "txd1", V_MV78230_PLUS),
123 MPP_VAR_FUNCTION(0x2, "ge1", "txd2", V_MV78230_PLUS),
128 MPP_VAR_FUNCTION(0x2, "ge1", "txd3", V_MV78230_PLUS),
134 MPP_VAR_FUNCTION(0x2, "ge1", "txctl", V_MV78230_PLUS),
140 MPP_VAR_FUNCTION(0x2, "ge1", "rxd0", V_MV78230_PLUS),
146 MPP_VAR_FUNCTION(0x2, "ge1", "rxd1", V_MV78230_PLUS),
152 MPP_VAR_FUNCTION(0x2, "ge1", "rxd2", V_MV78230_PLUS),
158 MPP_VAR_FUNCTION(0x2, "ge1", "rxd3", V_MV78230_PLUS),
164 MPP_VAR_FUNCTION(0x2, "ge1", "rxctl", V_MV78230_PLUS),
170 MPP_VAR_FUNCTION(0x2, "ge1", "rxclk", V_MV78230_PLUS),
223 MPP_VAR_FUNCTION(0x2, "sata0", "prsnt", V_MV78230_PLUS),
229 MPP_VAR_FUNCTION(0x2, "sata1", "prsnt", V_MV78230_PLUS),
246 MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS),
253 MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS),
261 MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS),
267 MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS),
274 MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS),
282 MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS),
290 MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS),
297 MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS),
305 MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS),
H A Dpinctrl-orion.c80 MPP_VAR_FUNCTION(0x2, "pci", "req2", V_ALL),
84 MPP_VAR_FUNCTION(0x2, "pci", "gnt2", V_ALL)),
87 MPP_VAR_FUNCTION(0x2, "pci", "req3", V_ALL),
91 MPP_VAR_FUNCTION(0x2, "pci", "gnt3", V_ALL)),
94 MPP_VAR_FUNCTION(0x2, "pci", "req4", V_ALL),
99 MPP_VAR_FUNCTION(0x2, "pci", "gnt4", V_ALL),
104 MPP_VAR_FUNCTION(0x2, "pci", "req5", V_ALL),
110 MPP_VAR_FUNCTION(0x2, "pci", "gnt5", V_ALL),
/linux-4.4.14/drivers/crypto/
H A Datmel-aes-regs.h18 #define AES_MR_SMOD_IDATAR0 (0x2 << 8)
22 #define AES_MR_KEYSIZE_256 (0x2 << 10)
26 #define AES_MR_OPMOD_OFB (0x2 << 12)
33 #define AES_MR_CFBS_32b (0x2 << 16)
50 #define AES_ISR_URAT_MR_WR_PROC (0x2 << 12)
H A Datmel-tdes-regs.h15 #define TDES_MR_TDESMOD_XTEA (0x2 << 1)
21 #define TDES_MR_SMOD_PDC (0x2 << 8)
25 #define TDES_MR_OPMOD_OFB (0x2 << 12)
31 #define TDES_MR_CFBS_16b (0x2 << 16)
51 #define TDES_ISR_URAT_MR (0x2 << 12)
H A Datmel-sha-regs.h16 #define SHA_MR_MODE_PDC 0x2
36 #define SHA_ISR_URAT_MR (0x2 << 12)
/linux-4.4.14/arch/arm64/mm/
H A Dcache.S53 dcache_line_size x2, x3
54 sub x3, x2, #1
58 add x4, x4, x2
63 icache_line_size x2, x3
64 sub x3, x2, #1
68 add x4, x4, x2
91 dcache_line_size x2, x3
93 sub x3, x2, #1
96 add x0, x0, x2
117 dcache_line_size x2, x3
118 sub x3, x2, #1
129 3: add x0, x0, x2
143 dcache_line_size x2, x3
144 sub x3, x2, #1
152 add x0, x0, x2
165 dcache_line_size x2, x3
166 sub x3, x2, #1
169 add x0, x0, x2
/linux-4.4.14/drivers/media/usb/dvb-usb/
H A Daf9005-script.h57 {0xa009, 0x0, 0x2, 0x2},
59 {0xae1c, 0x0, 0x8, 0x2},
63 {0xa007, 0x0, 0x2, 0x0},
65 {0xa00d, 0x0, 0x2, 0x2},
67 {0xa60e, 0x0, 0x2, 0x2},
69 {0xa60e, 0x2, 0x2, 0x3},
71 {0xa00b, 0x0, 0x2, 0x0},
73 {0xa012, 0x0, 0x2, 0x0},
75 {0xa014, 0x0, 0x2, 0x2},
82 {0xa60e, 0x4, 0x2, 0x2},
84 {0xa60e, 0x6, 0x2, 0x3},
85 {0xa001, 0x2, 0x2, 0x1},
117 {0xa33d, 0x2, 0x1, 0x1},
132 {0xa080, 0x2, 0x5, 0x3},
179 {0xa171, 0x0, 0x2, 0x0},
183 {0xa391, 0x2, 0x1, 0x0},
191 {0xabc0, 0x4, 0x2, 0x0},
194 {0xabc0, 0x2, 0x1, 0x1},
199 {0xa347, 0x4, 0x4, 0x2},
202 {0xa349, 0x0, 0x6, 0x2},
/linux-4.4.14/arch/arm/boot/dts/
H A Dimx6sl-pinfunc.h19 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
26 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
27 #define MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x050 0x2a8 0x80c 0x2 0x0
34 #define MX6SL_PAD_AUD_RXD__UART4_RX_DATA 0x054 0x2ac 0x814 0x2 0x0
35 #define MX6SL_PAD_AUD_RXD__UART4_TX_DATA 0x054 0x2ac 0x000 0x2 0x0
41 #define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA 0x058 0x2b0 0x80c 0x2 0x1
42 #define MX6SL_PAD_AUD_RXFS__UART3_TX_DATA 0x058 0x2b0 0x000 0x2 0x0
49 #define MX6SL_PAD_AUD_TXC__UART4_TX_DATA 0x05c 0x2b4 0x000 0x2 0x0
50 #define MX6SL_PAD_AUD_TXC__UART4_RX_DATA 0x05c 0x2b4 0x814 0x2 0x1
56 #define MX6SL_PAD_AUD_TXD__UART4_CTS_B 0x060 0x2b8 0x000 0x2 0x0
57 #define MX6SL_PAD_AUD_TXD__UART4_RTS_B 0x060 0x2b8 0x810 0x2 0x0
63 #define MX6SL_PAD_AUD_TXFS__UART4_RTS_B 0x064 0x2bc 0x810 0x2 0x1
64 #define MX6SL_PAD_AUD_TXFS__UART4_CTS_B 0x064 0x2bc 0x000 0x2 0x0
70 #define MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x068 0x358 0x818 0x2 0x0
71 #define MX6SL_PAD_ECSPI1_MISO__UART5_CTS_B 0x068 0x358 0x000 0x2 0x0
77 #define MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x06c 0x35c 0x000 0x2 0x0
78 #define MX6SL_PAD_ECSPI1_MOSI__UART5_RX_DATA 0x06c 0x35c 0x81c 0x2 0x0
84 #define MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x070 0x360 0x81c 0x2 0x1
85 #define MX6SL_PAD_ECSPI1_SCLK__UART5_TX_DATA 0x070 0x360 0x000 0x2 0x0
92 #define MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x074 0x364 0x000 0x2 0x0
93 #define MX6SL_PAD_ECSPI1_SS0__UART5_RTS_B 0x074 0x364 0x818 0x2 0x1
100 #define MX6SL_PAD_ECSPI2_MISO__UART3_RTS_B 0x078 0x368 0x808 0x2 0x0
101 #define MX6SL_PAD_ECSPI2_MISO__UART3_CTS_B 0x078 0x368 0x000 0x2 0x0
108 #define MX6SL_PAD_ECSPI2_MOSI__UART3_TX_DATA 0x07c 0x36c 0x000 0x2 0x0
109 #define MX6SL_PAD_ECSPI2_MOSI__UART3_RX_DATA 0x07c 0x36c 0x80c 0x2 0x2
115 #define MX6SL_PAD_ECSPI2_SCLK__UART3_RX_DATA 0x080 0x370 0x80c 0x2 0x3
116 #define MX6SL_PAD_ECSPI2_SCLK__UART3_TX_DATA 0x080 0x370 0x000 0x2 0x0
123 #define MX6SL_PAD_ECSPI2_SS0__UART3_CTS_B 0x084 0x374 0x000 0x2 0x0
124 #define MX6SL_PAD_ECSPI2_SS0__UART3_RTS_B 0x084 0x374 0x808 0x2 0x1
131 #define MX6SL_PAD_EPDC_BDR0__UART3_RTS_B 0x088 0x378 0x808 0x2 0x2
132 #define MX6SL_PAD_EPDC_BDR0__UART3_CTS_B 0x088 0x378 0x000 0x2 0x0
139 #define MX6SL_PAD_EPDC_BDR1__UART3_CTS_B 0x08c 0x37c 0x000 0x2 0x0
140 #define MX6SL_PAD_EPDC_BDR1__UART3_RTS_B 0x08c 0x37c 0x808 0x2 0x3
147 #define MX6SL_PAD_EPDC_D0__LCD_DATA24 0x090 0x380 0x000 0x2 0x0
153 #define MX6SL_PAD_EPDC_D1__LCD_DATA25 0x094 0x384 0x000 0x2 0x0
159 #define MX6SL_PAD_EPDC_D10__EPDC_PWR_CTRL2 0x098 0x388 0x000 0x2 0x0
166 #define MX6SL_PAD_EPDC_D11__EPDC_PWR_CTRL3 0x09c 0x38c 0x000 0x2 0x0
174 #define MX6SL_PAD_EPDC_D12__EPDC_PWR_COM 0x0a0 0x390 0x000 0x2 0x0
182 #define MX6SL_PAD_EPDC_D13__EPDC_PWR_IRQ 0x0a4 0x394 0x6e8 0x2 0x0
190 #define MX6SL_PAD_EPDC_D14__EPDC_PWR_STAT 0x0a8 0x398 0x6ec 0x2 0x0
198 #define MX6SL_PAD_EPDC_D15__EPDC_PWR_WAKE 0x0ac 0x39c 0x000 0x2 0x0
205 #define MX6SL_PAD_EPDC_D2__LCD_DATA26 0x0b0 0x3a0 0x000 0x2 0x0
211 #define MX6SL_PAD_EPDC_D3__LCD_DATA27 0x0b4 0x3a4 0x000 0x2 0x0
217 #define MX6SL_PAD_EPDC_D4__LCD_DATA28 0x0b8 0x3a8 0x000 0x2 0x0
223 #define MX6SL_PAD_EPDC_D5__LCD_DATA29 0x0bc 0x3ac 0x000 0x2 0x0
229 #define MX6SL_PAD_EPDC_D6__LCD_DATA30 0x0c0 0x3b0 0x000 0x2 0x0
235 #define MX6SL_PAD_EPDC_D7__LCD_DATA31 0x0c4 0x3b4 0x000 0x2 0x0
241 #define MX6SL_PAD_EPDC_D8__EPDC_PWR_CTRL0 0x0c8 0x3b8 0x000 0x2 0x0
248 #define MX6SL_PAD_EPDC_D9__EPDC_PWR_CTRL1 0x0cc 0x3bc 0x000 0x2 0x0
255 #define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKR 0x0d0 0x3c0 0x000 0x2 0x0
262 #define MX6SL_PAD_EPDC_GDOE__SPDC_YOER 0x0d4 0x3c4 0x000 0x2 0x0
269 #define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUR 0x0d8 0x3c8 0x000 0x2 0x0
276 #define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODR 0x0dc 0x3cc 0x000 0x2 0x0
283 #define MX6SL_PAD_EPDC_PWRCOM__LCD_DATA20 0x0e0 0x3d0 0x7c8 0x2 0x0
290 #define MX6SL_PAD_EPDC_PWRCTRL0__LCD_DATA16 0x0e4 0x3d4 0x7b8 0x2 0x0
297 #define MX6SL_PAD_EPDC_PWRCTRL1__LCD_DATA17 0x0e8 0x3d8 0x7bc 0x2 0x0
304 #define MX6SL_PAD_EPDC_PWRCTRL2__LCD_DATA18 0x0ec 0x3dc 0x7c0 0x2 0x0
311 #define MX6SL_PAD_EPDC_PWRCTRL3__LCD_DATA19 0x0f0 0x3e0 0x7c4 0x2 0x0
318 #define MX6SL_PAD_EPDC_PWRINT__LCD_DATA21 0x0f4 0x3e4 0x7cc 0x2 0x0
325 #define MX6SL_PAD_EPDC_PWRSTAT__LCD_DATA22 0x0f8 0x3e8 0x7d0 0x2 0x0
332 #define MX6SL_PAD_EPDC_PWRWAKEUP__LCD_DATA23 0x0fc 0x3ec 0x7d4 0x2 0x0
339 #define MX6SL_PAD_EPDC_SDCE0__PWM3_OUT 0x100 0x3f0 0x000 0x2 0x0
345 #define MX6SL_PAD_EPDC_SDCE1__PWM4_OUT 0x104 0x3f4 0x000 0x2 0x0
351 #define MX6SL_PAD_EPDC_SDCE2__PWM1_OUT 0x108 0x3f8 0x000 0x2 0x0
357 #define MX6SL_PAD_EPDC_SDCE3__PWM2_OUT 0x10c 0x3fc 0x000 0x2 0x0
363 #define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL 0x110 0x400 0x724 0x2 0x0
369 #define MX6SL_PAD_EPDC_SDLE__I2C2_SDA 0x114 0x404 0x728 0x2 0x0
375 #define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOR 0x118 0x408 0x000 0x2 0x0
381 #define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x11c 0x40c 0x000 0x2 0x0
387 #define MX6SL_PAD_EPDC_VCOM0__UART3_RX_DATA 0x120 0x410 0x80c 0x2 0x4
388 #define MX6SL_PAD_EPDC_VCOM0__UART3_TX_DATA 0x120 0x410 0x000 0x2 0x0
395 #define MX6SL_PAD_EPDC_VCOM1__UART3_TX_DATA 0x124 0x414 0x000 0x2 0x0
396 #define MX6SL_PAD_EPDC_VCOM1__UART3_RX_DATA 0x124 0x414 0x80c 0x2 0x5
403 #define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC 0x128 0x418 0x624 0x2 0x0
410 #define MX6SL_PAD_FEC_MDC__AUDIO_CLK_OUT 0x12c 0x41c 0x000 0x2 0x0
417 #define MX6SL_PAD_FEC_MDIO__AUD6_RXFS 0x130 0x420 0x620 0x2 0x0
424 #define MX6SL_PAD_FEC_REF_CLK__WDOG1_B 0x134 0x424 0x000 0x2 0x0
428 #define MX6SL_PAD_FEC_REF_CLK__SPDIF_EXT_CLK 0x134 0x424 0x7f4 0x6 0x2
431 #define MX6SL_PAD_FEC_RX_ER__AUD6_RXD 0x138 0x428 0x614 0x2 0x0
438 #define MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x13c 0x42c 0x5dc 0x2 0x1
445 #define MX6SL_PAD_FEC_RXD1__AUD6_TXFS 0x140 0x430 0x628 0x2 0x0
452 #define MX6SL_PAD_FEC_TX_CLK__AUD6_RXC 0x144 0x434 0x61c 0x2 0x0
459 #define MX6SL_PAD_FEC_TX_EN__SPDIF_IN 0x148 0x438 0x7f0 0x2 0x0
466 #define MX6SL_PAD_FEC_TXD0__AUD6_TXD 0x14c 0x43c 0x618 0x2 0x0
473 #define MX6SL_PAD_FEC_TXD1__SPDIF_OUT 0x150 0x440 0x000 0x2 0x0
480 #define MX6SL_PAD_HSIC_DAT__PWM1_OUT 0x154 0x444 0x000 0x2 0x0
485 #define MX6SL_PAD_HSIC_STROBE__PWM2_OUT 0x158 0x448 0x000 0x2 0x0
488 #define MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x15c 0x44c 0x71c 0x0 0x2
491 #define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2 0x15c 0x44c 0x6c8 0x2 0x1
496 #define MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x160 0x450 0x720 0x0 0x2
499 #define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3 0x160 0x450 0x6cc 0x2 0x1
506 #define MX6SL_PAD_I2C2_SCL__SPDIF_IN 0x164 0x454 0x7f0 0x2 0x1
508 #define MX6SL_PAD_I2C2_SCL__SD3_WP 0x164 0x454 0x84c 0x4 0x2
513 #define MX6SL_PAD_I2C2_SDA__SPDIF_OUT 0x168 0x458 0x000 0x2 0x0
515 #define MX6SL_PAD_I2C2_SDA__SD3_CD_B 0x168 0x458 0x838 0x4 0x2
518 #define MX6SL_PAD_KEY_COL0__I2C2_SCL 0x16c 0x474 0x724 0x1 0x2
519 #define MX6SL_PAD_KEY_COL0__LCD_DATA00 0x16c 0x474 0x778 0x2 0x0
521 #define MX6SL_PAD_KEY_COL0__SD1_CD_B 0x16c 0x474 0x828 0x4 0x2
524 #define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI 0x170 0x478 0x6d8 0x1 0x2
525 #define MX6SL_PAD_KEY_COL1__LCD_DATA02 0x170 0x478 0x780 0x2 0x0
530 #define MX6SL_PAD_KEY_COL2__ECSPI4_SS0 0x174 0x47c 0x6dc 0x1 0x2
531 #define MX6SL_PAD_KEY_COL2__LCD_DATA04 0x174 0x47c 0x788 0x2 0x0
537 #define MX6SL_PAD_KEY_COL3__LCD_DATA06 0x178 0x480 0x790 0x2 0x0
544 #define MX6SL_PAD_KEY_COL4__LCD_DATA08 0x17c 0x484 0x798 0x2 0x0
546 #define MX6SL_PAD_KEY_COL4__SD4_CLK 0x17c 0x484 0x850 0x4 0x2
551 #define MX6SL_PAD_KEY_COL5__LCD_DATA10 0x180 0x488 0x7a0 0x2 0x0
553 #define MX6SL_PAD_KEY_COL5__SD4_DATA0 0x180 0x488 0x85c 0x4 0x2
557 #define MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x184 0x48c 0x814 0x1 0x2
559 #define MX6SL_PAD_KEY_COL6__LCD_DATA12 0x184 0x48c 0x7a8 0x2 0x0
561 #define MX6SL_PAD_KEY_COL6__SD4_DATA2 0x184 0x48c 0x864 0x4 0x2
565 #define MX6SL_PAD_KEY_COL7__UART4_RTS_B 0x188 0x490 0x810 0x1 0x2
567 #define MX6SL_PAD_KEY_COL7__LCD_DATA14 0x188 0x490 0x7b0 0x2 0x0
571 #define MX6SL_PAD_KEY_COL7__SD1_WP 0x188 0x490 0x82c 0x6 0x2
573 #define MX6SL_PAD_KEY_ROW0__I2C2_SDA 0x18c 0x494 0x728 0x1 0x2
574 #define MX6SL_PAD_KEY_ROW0__LCD_DATA01 0x18c 0x494 0x77c 0x2 0x0
579 #define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO 0x190 0x498 0x6d4 0x1 0x2
580 #define MX6SL_PAD_KEY_ROW1__LCD_DATA03 0x190 0x498 0x784 0x2 0x0
585 #define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK 0x194 0x49c 0x6d0 0x1 0x2
586 #define MX6SL_PAD_KEY_ROW2__LCD_DATA05 0x194 0x49c 0x78c 0x2 0x0
592 #define MX6SL_PAD_KEY_ROW3__LCD_DATA07 0x198 0x4a0 0x794 0x2 0x0
599 #define MX6SL_PAD_KEY_ROW4__LCD_DATA09 0x19c 0x4a4 0x79c 0x2 0x0
601 #define MX6SL_PAD_KEY_ROW4__SD4_CMD 0x19c 0x4a4 0x858 0x4 0x2
606 #define MX6SL_PAD_KEY_ROW5__LCD_DATA11 0x1a0 0x4a8 0x7a4 0x2 0x0
608 #define MX6SL_PAD_KEY_ROW5__SD4_DATA1 0x1a0 0x4a8 0x860 0x4 0x2
610 #define MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x1a0 0x4a8 0x820 0x6 0x2
614 #define MX6SL_PAD_KEY_ROW6__LCD_DATA13 0x1a4 0x4ac 0x7ac 0x2 0x0
616 #define MX6SL_PAD_KEY_ROW6__SD4_DATA3 0x1a4 0x4ac 0x868 0x4 0x2
622 #define MX6SL_PAD_KEY_ROW7__LCD_DATA15 0x1a8 0x4b0 0x7b4 0x2 0x0
628 #define MX6SL_PAD_LCD_CLK__SD4_DATA4 0x1ac 0x4b4 0x86c 0x1 0x2
629 #define MX6SL_PAD_LCD_CLK__LCD_WR_RWN 0x1ac 0x4b4 0x000 0x2 0x0
635 #define MX6SL_PAD_LCD_DAT0__USB_OTG2_ID 0x1b0 0x4b8 0x5e0 0x2 0x1
643 #define MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x1b4 0x4bc 0x5dc 0x2 0x2
651 #define MX6SL_PAD_LCD_DAT10__CSI_DATA07 0x1b8 0x4c0 0x64c 0x2 0x1
653 #define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO 0x1b8 0x4c0 0x6a0 0x4 0x2
659 #define MX6SL_PAD_LCD_DAT11__CSI_DATA06 0x1bc 0x4c4 0x648 0x2 0x1
667 #define MX6SL_PAD_LCD_DAT12__CSI_DATA05 0x1c0 0x4c8 0x644 0x2 0x1
669 #define MX6SL_PAD_LCD_DAT12__UART5_RTS_B 0x1c0 0x4c8 0x818 0x4 0x2
676 #define MX6SL_PAD_LCD_DAT13__CSI_DATA04 0x1c4 0x4cc 0x640 0x2 0x1
685 #define MX6SL_PAD_LCD_DAT14__CSI_DATA03 0x1c8 0x4d0 0x63c 0x2 0x1
687 #define MX6SL_PAD_LCD_DAT14__UART5_RX_DATA 0x1c8 0x4d0 0x81c 0x4 0x2
694 #define MX6SL_PAD_LCD_DAT15__CSI_DATA02 0x1cc 0x4d4 0x638 0x2 0x1
703 #define MX6SL_PAD_LCD_DAT16__CSI_DATA01 0x1d0 0x4d8 0x634 0x2 0x1
711 #define MX6SL_PAD_LCD_DAT17__CSI_DATA00 0x1d4 0x4dc 0x630 0x2 0x1
719 #define MX6SL_PAD_LCD_DAT18__CSI_DATA15 0x1d8 0x4e0 0x66c 0x2 0x0
727 #define MX6SL_PAD_LCD_DAT19__CSI_DATA14 0x1dc 0x4e4 0x668 0x2 0x0
735 #define MX6SL_PAD_LCD_DAT2__EPIT2_OUT 0x1e0 0x4e8 0x000 0x2 0x0
743 #define MX6SL_PAD_LCD_DAT20__CSI_DATA13 0x1e4 0x4ec 0x664 0x2 0x0
751 #define MX6SL_PAD_LCD_DAT21__CSI_DATA12 0x1e8 0x4f0 0x660 0x2 0x0
759 #define MX6SL_PAD_LCD_DAT22__CSI_DATA11 0x1ec 0x4f4 0x65c 0x2 0x1
767 #define MX6SL_PAD_LCD_DAT23__CSI_DATA10 0x1f0 0x4f8 0x658 0x2 0x1
775 #define MX6SL_PAD_LCD_DAT3__UART5_DSR_B 0x1f4 0x4fc 0x000 0x2 0x0
783 #define MX6SL_PAD_LCD_DAT4__CSI_VSYNC 0x1f8 0x500 0x678 0x2 0x2
791 #define MX6SL_PAD_LCD_DAT5__CSI_HSYNC 0x1fc 0x504 0x670 0x2 0x2
799 #define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK 0x200 0x508 0x674 0x2 0x2
807 #define MX6SL_PAD_LCD_DAT7__CSI_MCLK 0x204 0x50c 0x000 0x2 0x0
815 #define MX6SL_PAD_LCD_DAT8__CSI_DATA09 0x208 0x510 0x654 0x2 0x1
817 #define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK 0x208 0x510 0x69c 0x4 0x2
823 #define MX6SL_PAD_LCD_DAT9__CSI_DATA08 0x20c 0x514 0x650 0x2 0x1
825 #define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI 0x20c 0x514 0x6a4 0x4 0x2
830 #define MX6SL_PAD_LCD_ENABLE__SD4_DATA5 0x210 0x518 0x870 0x1 0x2
831 #define MX6SL_PAD_LCD_ENABLE__LCD_RD_E 0x210 0x518 0x000 0x2 0x0
833 #define MX6SL_PAD_LCD_ENABLE__UART2_RX_DATA 0x210 0x518 0x804 0x4 0x2
837 #define MX6SL_PAD_LCD_HSYNC__SD4_DATA6 0x214 0x51c 0x874 0x1 0x2
838 #define MX6SL_PAD_LCD_HSYNC__LCD_CS 0x214 0x51c 0x000 0x2 0x0
846 #define MX6SL_PAD_LCD_RESET__LCD_BUSY 0x218 0x520 0x774 0x2 0x1
849 #define MX6SL_PAD_LCD_RESET__UART2_RTS_B 0x218 0x520 0x800 0x4 0x2
853 #define MX6SL_PAD_LCD_VSYNC__SD4_DATA7 0x21c 0x524 0x878 0x1 0x2
854 #define MX6SL_PAD_LCD_VSYNC__LCD_RS 0x21c 0x524 0x000 0x2 0x0
862 #define MX6SL_PAD_PWM1__AUDIO_CLK_OUT 0x220 0x528 0x000 0x2 0x0
868 #define MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x224 0x52c 0x72c 0x1 0x2
869 #define MX6SL_PAD_REF_CLK_24M__PWM3_OUT 0x224 0x52c 0x000 0x2 0x0
870 #define MX6SL_PAD_REF_CLK_24M__USB_OTG2_ID 0x224 0x52c 0x5e0 0x3 0x2
871 #define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x224 0x52c 0x62c 0x4 0x2
875 #define MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x228 0x530 0x730 0x1 0x2
876 #define MX6SL_PAD_REF_CLK_32K__PWM4_OUT 0x228 0x530 0x000 0x2 0x0
882 #define MX6SL_PAD_SD1_CLK__FEC_MDIO 0x22c 0x534 0x6f4 0x1 0x2
883 #define MX6SL_PAD_SD1_CLK__KEY_COL0 0x22c 0x534 0x734 0x2 0x2
887 #define MX6SL_PAD_SD1_CMD__FEC_TX_CLK 0x230 0x538 0x70c 0x1 0x2
888 #define MX6SL_PAD_SD1_CMD__KEY_ROW0 0x230 0x538 0x754 0x2 0x2
892 #define MX6SL_PAD_SD1_DAT0__FEC_RX_ER 0x234 0x53c 0x708 0x1 0x2
893 #define MX6SL_PAD_SD1_DAT0__KEY_COL1 0x234 0x53c 0x738 0x2 0x2
897 #define MX6SL_PAD_SD1_DAT1__FEC_RX_DV 0x238 0x540 0x704 0x1 0x2
898 #define MX6SL_PAD_SD1_DAT1__KEY_ROW1 0x238 0x540 0x758 0x2 0x2
902 #define MX6SL_PAD_SD1_DAT2__FEC_RX_DATA1 0x23c 0x544 0x6fc 0x1 0x2
903 #define MX6SL_PAD_SD1_DAT2__KEY_COL2 0x23c 0x544 0x73c 0x2 0x2
908 #define MX6SL_PAD_SD1_DAT3__KEY_ROW2 0x240 0x548 0x75c 0x2 0x2
913 #define MX6SL_PAD_SD1_DAT4__KEY_COL3 0x244 0x54c 0x740 0x2 0x2
919 #define MX6SL_PAD_SD1_DAT5__FEC_RX_DATA0 0x248 0x550 0x6f8 0x1 0x2
920 #define MX6SL_PAD_SD1_DAT5__KEY_ROW3 0x248 0x550 0x760 0x2 0x2
927 #define MX6SL_PAD_SD1_DAT6__KEY_COL4 0x24c 0x554 0x744 0x2 0x2
934 #define MX6SL_PAD_SD1_DAT7__KEY_ROW4 0x250 0x558 0x764 0x2 0x2
940 #define MX6SL_PAD_SD2_CLK__AUD4_RXFS 0x254 0x55c 0x5f0 0x1 0x2
941 #define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK 0x254 0x55c 0x6b0 0x2 0x2
942 #define MX6SL_PAD_SD2_CLK__CSI_DATA00 0x254 0x55c 0x630 0x3 0x2
945 #define MX6SL_PAD_SD2_CMD__AUD4_RXC 0x258 0x560 0x5ec 0x1 0x2
946 #define MX6SL_PAD_SD2_CMD__ECSPI3_SS0 0x258 0x560 0x6c0 0x2 0x2
947 #define MX6SL_PAD_SD2_CMD__CSI_DATA01 0x258 0x560 0x634 0x3 0x2
951 #define MX6SL_PAD_SD2_DAT0__AUD4_RXD 0x25c 0x564 0x5e4 0x1 0x2
952 #define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI 0x25c 0x564 0x6bc 0x2 0x2
953 #define MX6SL_PAD_SD2_DAT0__CSI_DATA02 0x25c 0x564 0x638 0x3 0x2
958 #define MX6SL_PAD_SD2_DAT1__AUD4_TXC 0x260 0x568 0x5f4 0x1 0x2
959 #define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO 0x260 0x568 0x6b8 0x2 0x2
960 #define MX6SL_PAD_SD2_DAT1__CSI_DATA03 0x260 0x568 0x63c 0x3 0x2
965 #define MX6SL_PAD_SD2_DAT2__AUD4_TXFS 0x264 0x56c 0x5f8 0x1 0x2
966 #define MX6SL_PAD_SD2_DAT2__FEC_COL 0x264 0x56c 0x6f0 0x2 0x1
967 #define MX6SL_PAD_SD2_DAT2__CSI_DATA04 0x264 0x56c 0x640 0x3 0x2
972 #define MX6SL_PAD_SD2_DAT3__AUD4_TXD 0x268 0x570 0x5e8 0x1 0x2
973 #define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK 0x268 0x570 0x700 0x2 0x1
974 #define MX6SL_PAD_SD2_DAT3__CSI_DATA05 0x268 0x570 0x644 0x3 0x2
980 #define MX6SL_PAD_SD2_DAT4__UART2_RX_DATA 0x26c 0x574 0x804 0x2 0x4
981 #define MX6SL_PAD_SD2_DAT4__UART2_TX_DATA 0x26c 0x574 0x000 0x2 0x0
982 #define MX6SL_PAD_SD2_DAT4__CSI_DATA06 0x26c 0x574 0x648 0x3 0x2
987 #define MX6SL_PAD_SD2_DAT5__UART2_TX_DATA 0x270 0x578 0x000 0x2 0x0
988 #define MX6SL_PAD_SD2_DAT5__UART2_RX_DATA 0x270 0x578 0x804 0x2 0x5
989 #define MX6SL_PAD_SD2_DAT5__CSI_DATA07 0x270 0x578 0x64c 0x3 0x2
990 #define MX6SL_PAD_SD2_DAT5__SPDIF_IN 0x270 0x578 0x7f0 0x4 0x2
994 #define MX6SL_PAD_SD2_DAT6__UART2_RTS_B 0x274 0x57c 0x800 0x2 0x4
995 #define MX6SL_PAD_SD2_DAT6__UART2_CTS_B 0x274 0x57c 0x000 0x2 0x0
996 #define MX6SL_PAD_SD2_DAT6__CSI_DATA08 0x274 0x57c 0x650 0x3 0x2
997 #define MX6SL_PAD_SD2_DAT6__SD2_WP 0x274 0x57c 0x834 0x4 0x2
1001 #define MX6SL_PAD_SD2_DAT7__UART2_CTS_B 0x278 0x580 0x000 0x2 0x0
1002 #define MX6SL_PAD_SD2_DAT7__UART2_RTS_B 0x278 0x580 0x800 0x2 0x5
1003 #define MX6SL_PAD_SD2_DAT7__CSI_DATA09 0x278 0x580 0x654 0x3 0x2
1004 #define MX6SL_PAD_SD2_DAT7__SD2_CD_B 0x278 0x580 0x830 0x4 0x2
1008 #define MX6SL_PAD_SD2_RST__WDOG2_B 0x27c 0x584 0x000 0x2 0x0
1014 #define MX6SL_PAD_SD3_CLK__KEY_COL5 0x280 0x588 0x748 0x2 0x2
1015 #define MX6SL_PAD_SD3_CLK__CSI_DATA10 0x280 0x588 0x658 0x3 0x2
1021 #define MX6SL_PAD_SD3_CMD__KEY_ROW5 0x284 0x58c 0x768 0x2 0x2
1022 #define MX6SL_PAD_SD3_CMD__CSI_DATA11 0x284 0x58c 0x65c 0x3 0x2
1028 #define MX6SL_PAD_SD3_DAT0__KEY_COL6 0x288 0x590 0x74c 0x2 0x2
1034 #define MX6SL_PAD_SD3_DAT1__KEY_ROW6 0x28c 0x594 0x76c 0x2 0x2
1041 #define MX6SL_PAD_SD3_DAT2__KEY_COL7 0x290 0x598 0x750 0x2 0x2
1048 #define MX6SL_PAD_SD3_DAT3__KEY_ROW7 0x294 0x59c 0x770 0x2 0x2
1052 #define MX6SL_PAD_SD3_DAT3__USB_OTG1_OC 0x294 0x59c 0x824 0x6 0x2
1056 #define MX6SL_PAD_UART1_RXD__UART4_RX_DATA 0x298 0x5a0 0x814 0x2 0x6
1057 #define MX6SL_PAD_UART1_RXD__UART4_TX_DATA 0x298 0x5a0 0x000 0x2 0x0
1058 #define MX6SL_PAD_UART1_RXD__FEC_COL 0x298 0x5a0 0x6f0 0x3 0x2
1065 #define MX6SL_PAD_UART1_TXD__UART4_TX_DATA 0x29c 0x5a4 0x000 0x2 0x0
1066 #define MX6SL_PAD_UART1_TXD__UART4_RX_DATA 0x29c 0x5a4 0x814 0x2 0x7
1067 #define MX6SL_PAD_UART1_TXD__FEC_RX_CLK 0x29c 0x5a4 0x700 0x3 0x2
1074 #define MX6SL_PAD_WDOG_B__UART5_RI_B 0x2a0 0x5a8 0x000 0x2 0x0
H A Dimx6q-pinfunc.h19 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
25 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
37 #define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0
76 #define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0
90 #define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0
97 #define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0
104 #define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0
111 #define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0
119 #define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0
127 #define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0
135 #define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0
142 #define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0
143 #define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0
151 #define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1
152 #define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0
160 #define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0
161 #define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0
169 #define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1
170 #define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0
178 #define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0
187 #define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0
196 #define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0
207 #define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
217 #define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0
220 #define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2
225 #define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0
233 #define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1
240 #define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1
247 #define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1
252 #define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1
257 #define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1
262 #define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1
267 #define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1
272 #define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1
277 #define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1
282 #define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0
286 #define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0
290 #define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0
294 #define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0
299 #define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0
304 #define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1
310 #define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1
315 #define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0
320 #define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0
325 #define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0
330 #define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0
335 #define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0
340 #define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0
345 #define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0
350 #define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0
355 #define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0
360 #define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0
365 #define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1
370 #define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1
375 #define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1
388 #define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0
403 #define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0
407 #define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0
411 #define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0
415 #define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0
420 #define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0
424 #define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0
428 #define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0
432 #define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0
436 #define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0
440 #define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0
445 #define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0
450 #define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0
454 #define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0
459 #define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0
481 #define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1
486 #define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1
492 #define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1
498 #define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1
505 #define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1
512 #define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1
517 #define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1
522 #define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1
527 #define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1
531 #define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0
536 #define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0
541 #define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0
546 #define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0
551 #define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0
555 #define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0
559 #define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0
563 #define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0
567 #define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0
571 #define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0
574 #define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2
576 #define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1
582 #define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2
584 #define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1
590 #define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2
592 #define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1
598 #define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2
600 #define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1
606 #define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2
608 #define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0
615 #define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0
622 #define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1
626 #define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2
628 #define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1
635 #define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1
642 #define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0
648 #define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0
656 #define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0
663 #define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0
669 #define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1
677 #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1
682 #define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1
687 #define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1
691 #define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1
694 #define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2
698 #define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0
701 #define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2
707 #define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0
716 #define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1
720 #define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2
724 #define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1
730 #define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0
732 #define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2
737 #define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0
759 #define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3
760 #define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2
766 #define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3
773 #define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3
780 #define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3
781 #define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2
787 #define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2
788 #define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2
794 #define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2
795 #define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2
801 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2
808 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2
816 #define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2
828 #define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2
851 #define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2
862 #define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2
878 #define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2
879 #define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0
884 #define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2
888 #define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2
889 #define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0
894 #define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1
922 #define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0
926 #define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1
933 #define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1
939 #define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0
940 #define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2
944 #define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3
945 #define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0
972 #define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0
975 #define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0
978 #define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0
983 #define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6
984 #define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0
987 #define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4
988 #define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0
991 #define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0
992 #define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5
995 #define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0
996 #define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7
1000 #define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0
1009 #define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0
1016 #define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
1021 #define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0
1028 #define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0
1033 #define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3
1038 #define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2
1043 #define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2
H A Dimx51-pinfunc.h23 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
29 #define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0
35 #define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0
42 #define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0
47 #define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0
52 #define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0
56 #define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0
61 #define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0
67 #define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0
72 #define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0
77 #define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0
83 #define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0
87 #define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0
91 #define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0
95 #define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0
99 #define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0
125 #define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0
129 #define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0
134 #define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0
139 #define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0
165 #define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0
171 #define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0
177 #define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0
184 #define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0
195 #define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0
199 #define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0
209 #define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0
214 #define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0
216 #define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0
222 #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0
229 #define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0
242 #define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0
248 #define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0
254 #define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0
260 #define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0
267 #define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0
276 #define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0
281 #define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0
286 #define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0
291 #define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0
296 #define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1
301 #define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0
310 #define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0
315 #define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0
327 #define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0
332 #define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0
337 #define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0
342 #define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0
347 #define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0
352 #define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0
357 #define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0
405 #define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2
440 #define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2
444 #define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0
448 #define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0
470 #define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4
474 #define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0
476 #define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0
477 #define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2
480 #define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0
481 #define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2
484 #define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0
488 #define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0
491 #define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0
494 #define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0
497 #define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0
500 #define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0
504 #define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0
507 #define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0
510 #define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0
514 #define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0
526 #define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0
529 #define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1
535 #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0
539 #define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK 0x2c8 0x6c8 0x000 0x2 0x0
540 #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0
602 #define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1
605 #define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0
608 #define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1
610 #define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0
612 #define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1
614 #define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1
618 #define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1
620 #define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1
625 #define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1
634 #define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0
639 #define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0
644 #define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0
650 #define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0
655 #define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1
660 #define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1
665 #define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1
669 #define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1
673 #define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1
678 #define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0
681 #define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2
684 #define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2
686 #define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2
687 #define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1
693 #define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2
699 #define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2
705 #define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2
706 #define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1
708 #define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0
711 #define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2
718 #define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3
719 #define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2
721 #define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3
722 #define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2
724 #define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3
729 #define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0
732 #define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0
733 #define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1
738 #define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3
742 #define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3
750 #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0
754 #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0
761 #define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0
762 #define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2
767 #define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0
H A Dimx7d-pinfunc.h20 #define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
25 #define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
31 #define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
38 #define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
45 #define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
47 #define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
51 #define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
53 #define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
57 #define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
59 #define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
64 #define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
66 #define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
71 #define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0
79 #define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0
88 #define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0
97 #define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0
106 #define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0
114 #define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0
122 #define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0
129 #define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0
136 #define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0
144 #define MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x0038 0x02A8 0x0000 0x2 0x0
152 #define MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x003C 0x02AC 0x0000 0x2 0x0
160 #define MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x0040 0x02B0 0x0000 0x2 0x0
168 #define MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x0044 0x02B4 0x0000 0x2 0x0
176 #define MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x0048 0x02B8 0x0000 0x2 0x0
184 #define MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x004C 0x02BC 0x0000 0x2 0x0
192 #define MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x0050 0x02C0 0x0000 0x2 0x0
200 #define MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x0054 0x02C4 0x0000 0x2 0x0
210 #define MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x0058 0x02C8 0x0000 0x2 0x0
220 #define MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x005C 0x02CC 0x0000 0x2 0x0
230 #define MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x0060 0x02D0 0x0000 0x2 0x0
240 #define MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x0064 0x02D4 0x0000 0x2 0x0
250 #define MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x0068 0x02D8 0x0000 0x2 0x0
260 #define MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x006C 0x02DC 0x0000 0x2 0x0
270 #define MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x0070 0x02E0 0x0000 0x2 0x0
280 #define MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x0074 0x02E4 0x0000 0x2 0x0
288 #define MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x0078 0x02E8 0x0000 0x2 0x0
296 #define MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x007C 0x02EC 0x0000 0x2 0x0
304 #define MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x0080 0x02F0 0x0000 0x2 0x0
312 #define MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x0084 0x02F4 0x0000 0x2 0x0
319 #define MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x0088 0x02F8 0x0578 0x2 0x0
327 #define MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x008C 0x02FC 0x0000 0x2 0x0
335 #define MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x0090 0x0300 0x0000 0x2 0x0
343 #define MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x0094 0x0304 0x0000 0x2 0x0
351 #define MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x0098 0x0308 0x0000 0x2 0x0
359 #define MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x009C 0x030C 0x0000 0x2 0x0
366 #define MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x00A0 0x0310 0x0000 0x2 0x0
373 #define MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK 0x00A4 0x0314 0x0000 0x2 0x0
381 #define MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK 0x00A8 0x0318 0x0578 0x2 0x1
388 #define MX7D_PAD_EPDC_PWR_COM__ENET2_CRS 0x00AC 0x031C 0x0000 0x2 0x0
395 #define MX7D_PAD_EPDC_PWR_STAT__ENET2_COL 0x00B0 0x0320 0x0000 0x2 0x0
402 #define MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN 0x00B4 0x0324 0x0000 0x2 0x0
409 #define MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN 0x00B8 0x0328 0x0000 0x2 0x0
416 #define MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN 0x00BC 0x032C 0x0000 0x2 0x0
421 #define MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x00C0 0x0330 0x0698 0x0 0x2
423 #define MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN 0x00C0 0x0330 0x0000 0x2 0x0
430 #define MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI 0x00C4 0x0334 0x0000 0x2 0x0
434 #define MX7D_PAD_LCD_DATA00__LCD_DATA0 0x00C8 0x0338 0x0638 0x0 0x2
440 #define MX7D_PAD_LCD_DATA01__LCD_DATA1 0x00CC 0x033C 0x063C 0x0 0x2
446 #define MX7D_PAD_LCD_DATA02__LCD_DATA2 0x00D0 0x0340 0x0640 0x0 0x2
452 #define MX7D_PAD_LCD_DATA03__LCD_DATA3 0x00D4 0x0344 0x0644 0x0 0x2
458 #define MX7D_PAD_LCD_DATA04__LCD_DATA4 0x00D8 0x0348 0x0648 0x0 0x2
464 #define MX7D_PAD_LCD_DATA05__LCD_DATA5 0x00DC 0x034C 0x064C 0x0 0x2
469 #define MX7D_PAD_LCD_DATA06__LCD_DATA6 0x00E0 0x0350 0x0650 0x0 0x2
474 #define MX7D_PAD_LCD_DATA07__LCD_DATA7 0x00E4 0x0354 0x0654 0x0 0x2
479 #define MX7D_PAD_LCD_DATA08__LCD_DATA8 0x00E8 0x0358 0x0658 0x0 0x2
484 #define MX7D_PAD_LCD_DATA09__LCD_DATA9 0x00EC 0x035C 0x065C 0x0 0x2
489 #define MX7D_PAD_LCD_DATA10__LCD_DATA10 0x00F0 0x0360 0x0660 0x0 0x2
494 #define MX7D_PAD_LCD_DATA11__LCD_DATA11 0x00F4 0x0364 0x0664 0x0 0x2
499 #define MX7D_PAD_LCD_DATA12__LCD_DATA12 0x00F8 0x0368 0x0668 0x0 0x2
519 #define MX7D_PAD_LCD_DATA16__LCD_DATA16 0x0108 0x0378 0x0678 0x0 0x2
525 #define MX7D_PAD_LCD_DATA17__LCD_DATA17 0x010C 0x037C 0x067C 0x0 0x2
531 #define MX7D_PAD_LCD_DATA18__LCD_DATA18 0x0110 0x0380 0x0680 0x0 0x2
533 #define MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO 0x0110 0x0380 0x0000 0x2 0x0
541 #define MX7D_PAD_LCD_DATA19__LCD_DATA19 0x0114 0x0384 0x0684 0x0 0x2
547 #define MX7D_PAD_LCD_DATA20__LCD_DATA20 0x0118 0x0388 0x0688 0x0 0x2
549 #define MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT 0x0118 0x0388 0x0000 0x2 0x0
551 #define MX7D_PAD_LCD_DATA21__LCD_DATA21 0x011C 0x038C 0x068C 0x0 0x2
553 #define MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT 0x011C 0x038C 0x0000 0x2 0x0
558 #define MX7D_PAD_LCD_DATA22__LCD_DATA22 0x0120 0x0390 0x0690 0x0 0x2
560 #define MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT 0x0120 0x0390 0x0000 0x2 0x0
565 #define MX7D_PAD_LCD_DATA23__LCD_DATA23 0x0124 0x0394 0x0694 0x0 0x2
567 #define MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT 0x0124 0x0394 0x0000 0x2 0x0
575 #define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY 0x0128 0x0398 0x0000 0x2 0x0
583 #define MX7D_PAD_UART1_TX_DATA__SAI3_MCLK 0x012C 0x039C 0x0000 0x2 0x0
588 #define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2
591 #define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x0000 0x2 0x0
599 #define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 0x0134 0x03A4 0x06C8 0x2 0x0
604 #define MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0138 0x03A8 0x0704 0x0 0x2
607 #define MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC 0x0138 0x03A8 0x06CC 0x2 0x0
615 #define MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x013C 0x03AC 0x06D0 0x2 0x0
620 #define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0700 0x0 0x2
623 #define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x0140 0x03B0 0x0000 0x2 0x0
631 #define MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x0144 0x03B4 0x06D4 0x2 0x0
639 #define MX7D_PAD_I2C1_SCL__FLEXCAN1_RX 0x0148 0x03B8 0x04DC 0x2 0x1
646 #define MX7D_PAD_I2C1_SDA__FLEXCAN1_TX 0x014C 0x03BC 0x0000 0x2 0x0
654 #define MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B 0x0150 0x03C0 0x0000 0x2 0x0
656 #define MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 0x0150 0x03C0 0x0570 0x4 0x2
662 #define MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB 0x0154 0x03C4 0x0000 0x2 0x0
667 #define MX7D_PAD_I2C3_SCL__I2C3_SCL 0x0158 0x03C8 0x05E4 0x0 0x2
670 #define MX7D_PAD_I2C3_SCL__FLEXCAN2_RX 0x0158 0x03C8 0x04E0 0x2 0x1
675 #define MX7D_PAD_I2C3_SDA__I2C3_SDA 0x015C 0x03CC 0x05E8 0x0 0x2
678 #define MX7D_PAD_I2C3_SDA__FLEXCAN2_TX 0x015C 0x03CC 0x0000 0x2 0x0
683 #define MX7D_PAD_I2C4_SCL__I2C4_SCL 0x0160 0x03D0 0x05EC 0x0 0x2
686 #define MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B 0x0160 0x03D0 0x0000 0x2 0x0
691 #define MX7D_PAD_I2C4_SDA__I2C4_SDA 0x0164 0x03D4 0x05F0 0x0 0x2
694 #define MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB 0x0164 0x03D4 0x0000 0x2 0x0
700 #define MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x0168 0x03D8 0x071C 0x1 0x2
702 #define MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x0168 0x03D8 0x0000 0x2 0x0
709 #define MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x016C 0x03DC 0x0000 0x2 0x0
714 #define MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x0170 0x03E0 0x0718 0x1 0x2
716 #define MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x0170 0x03E0 0x0000 0x2 0x0
723 #define MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x0174 0x03E4 0x0000 0x2 0x0
728 #define MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x0178 0x03E8 0x0724 0x1 0x2
730 #define MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x0178 0x03E8 0x0000 0x2 0x0
732 #define MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 0x0178 0x03E8 0x066C 0x4 0x2
738 #define MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x017C 0x03EC 0x0000 0x2 0x0
740 #define MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 0x017C 0x03EC 0x0670 0x4 0x2
746 #define MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x0180 0x03F0 0x0720 0x1 0x2
748 #define MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x0180 0x03F0 0x0000 0x2 0x0
750 #define MX7D_PAD_ECSPI2_MISO__LCD_DATA15 0x0180 0x03F0 0x0674 0x4 0x2
754 #define MX7D_PAD_ECSPI2_SS0__SD1_DATA7 0x0184 0x03F4 0x0000 0x2 0x0
760 #define MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x0188 0x03F8 0x071C 0x2 0x4
761 #define MX7D_PAD_SD1_CD_B__UART6_DTE_TX 0x0188 0x03F8 0x0000 0x2 0x0
767 #define MX7D_PAD_SD1_WP__UART6_DCE_TX 0x018C 0x03FC 0x0000 0x2 0x0
768 #define MX7D_PAD_SD1_WP__UART6_DTE_RX 0x018C 0x03FC 0x071C 0x2 0x5
775 #define MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS 0x0190 0x0400 0x0718 0x2 0x4
776 #define MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS 0x0190 0x0400 0x0000 0x2 0x0
782 #define MX7D_PAD_SD1_CLK__UART6_DCE_CTS 0x0194 0x0404 0x0000 0x2 0x0
783 #define MX7D_PAD_SD1_CLK__UART6_DTE_RTS 0x0194 0x0404 0x0718 0x2 0x5
794 #define MX7D_PAD_SD1_DATA0__UART7_DCE_RX 0x019C 0x040C 0x0724 0x2 0x4
795 #define MX7D_PAD_SD1_DATA0__UART7_DTE_TX 0x019C 0x040C 0x0000 0x2 0x0
802 #define MX7D_PAD_SD1_DATA1__UART7_DCE_TX 0x01A0 0x0410 0x0000 0x2 0x0
803 #define MX7D_PAD_SD1_DATA1__UART7_DTE_RX 0x01A0 0x0410 0x0724 0x2 0x5
810 #define MX7D_PAD_SD1_DATA2__UART7_DCE_CTS 0x01A4 0x0414 0x0000 0x2 0x0
811 #define MX7D_PAD_SD1_DATA2__UART7_DTE_RTS 0x01A4 0x0414 0x0720 0x2 0x4
818 #define MX7D_PAD_SD1_DATA3__UART7_DCE_RTS 0x01A8 0x0418 0x0720 0x2 0x5
819 #define MX7D_PAD_SD1_DATA3__UART7_DTE_CTS 0x01A8 0x0418 0x0000 0x2 0x0
825 #define MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x01AC 0x041C 0x0568 0x1 0x2
826 #define MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x01AC 0x041C 0x0574 0x2 0x2
830 #define MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 0x01AC 0x041C 0x06D8 0x6 0x2
833 #define MX7D_PAD_SD2_WP__ENET2_MDC 0x01B0 0x0420 0x0000 0x2 0x0
835 #define MX7D_PAD_SD2_WP__USB_OTG1_ID 0x01B0 0x0420 0x0734 0x4 0x2
837 #define MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 0x01B0 0x0420 0x06DC 0x6 0x2
840 #define MX7D_PAD_SD2_RESET_B__SD2_RESET 0x01B4 0x0424 0x0000 0x2 0x0
842 #define MX7D_PAD_SD2_RESET_B__USB_OTG2_ID 0x01B4 0x0424 0x0730 0x4 0x2
846 #define MX7D_PAD_SD2_CLK__MQS_RIGHT 0x01B8 0x0428 0x0000 0x2 0x0
851 #define MX7D_PAD_SD2_CMD__MQS_LEFT 0x01BC 0x042C 0x0000 0x2 0x0
857 #define MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x01C0 0x0430 0x070C 0x2 0x2
858 #define MX7D_PAD_SD2_DATA0__UART4_DTE_TX 0x01C0 0x0430 0x0000 0x2 0x0
864 #define MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x01C4 0x0434 0x0000 0x2 0x0
865 #define MX7D_PAD_SD2_DATA1__UART4_DTE_RX 0x01C4 0x0434 0x070C 0x2 0x3
871 #define MX7D_PAD_SD2_DATA2__UART4_DCE_CTS 0x01C8 0x0438 0x0000 0x2 0x0
872 #define MX7D_PAD_SD2_DATA2__UART4_DTE_RTS 0x01C8 0x0438 0x0708 0x2 0x2
878 #define MX7D_PAD_SD2_DATA3__UART4_DCE_RTS 0x01CC 0x043C 0x0708 0x2 0x3
879 #define MX7D_PAD_SD2_DATA3__UART4_DTE_CTS 0x01CC 0x043C 0x0000 0x2 0x0
885 #define MX7D_PAD_SD3_CLK__ECSPI4_MISO 0x01D0 0x0440 0x0558 0x2 0x2
886 #define MX7D_PAD_SD3_CLK__SAI3_RX_SYNC 0x01D0 0x0440 0x06CC 0x3 0x2
891 #define MX7D_PAD_SD3_CMD__ECSPI4_MOSI 0x01D4 0x0444 0x055C 0x2 0x2
892 #define MX7D_PAD_SD3_CMD__SAI3_RX_BCLK 0x01D4 0x0444 0x06C4 0x3 0x2
897 #define MX7D_PAD_SD3_DATA0__ECSPI4_SS0 0x01D8 0x0448 0x0560 0x2 0x2
898 #define MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 0x01D8 0x0448 0x06C8 0x3 0x2
903 #define MX7D_PAD_SD3_DATA1__ECSPI4_SCLK 0x01DC 0x044C 0x0554 0x2 0x2
904 #define MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK 0x01DC 0x044C 0x06D0 0x3 0x2
909 #define MX7D_PAD_SD3_DATA2__I2C3_SDA 0x01E0 0x0450 0x05E8 0x2 0x3
910 #define MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC 0x01E0 0x0450 0x06D4 0x3 0x2
915 #define MX7D_PAD_SD3_DATA3__I2C3_SCL 0x01E4 0x0454 0x05E4 0x2 0x3
923 #define MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x01E8 0x0458 0x04E0 0x4 0x2
933 #define MX7D_PAD_SD3_DATA6__SD3_WP 0x01F0 0x0460 0x073C 0x2 0x2
940 #define MX7D_PAD_SD3_DATA7__SD3_CD_B 0x01F4 0x0464 0x0738 0x2 0x2
943 #define MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x01F4 0x0464 0x04DC 0x4 0x2
950 #define MX7D_PAD_SD3_RESET_B__SD3_RESET 0x01FC 0x046C 0x0000 0x2 0x0
955 #define MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x0200 0x0470 0x0714 0x2 0x2
956 #define MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x0200 0x0470 0x0000 0x2 0x0
963 #define MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x0204 0x0474 0x0000 0x2 0x0
964 #define MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x0204 0x0474 0x0714 0x2 0x3
971 #define MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x0208 0x0478 0x0000 0x2 0x0
972 #define MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x0208 0x0478 0x0710 0x2 0x2
979 #define MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x020C 0x047C 0x0710 0x2 0x3
980 #define MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x020C 0x047C 0x0000 0x2 0x0
987 #define MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x0210 0x0480 0x06B8 0x2 0x1
995 #define MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK 0x0214 0x0484 0x06B0 0x2 0x1
1003 #define MX7D_PAD_SAI1_MCLK__SAI2_MCLK 0x0218 0x0488 0x0000 0x2 0x0
1010 #define MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x021C 0x048C 0x070C 0x2 0x4
1011 #define MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX 0x021C 0x048C 0x0000 0x2 0x0
1018 #define MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x0220 0x0490 0x0000 0x2 0x0
1019 #define MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX 0x0220 0x0490 0x070C 0x2 0x5
1026 #define MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x0224 0x0494 0x0000 0x2 0x0
1027 #define MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS 0x0224 0x0494 0x0708 0x2 0x4
1029 #define MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x0224 0x0494 0x06F8 0x3 0x2
1035 #define MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x0228 0x0498 0x0708 0x2 0x5
1036 #define MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS 0x0228 0x0498 0x0000 0x2 0x0
1044 #define MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x022C 0x049C 0x05E4 0x2 0x4
1046 #define MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS 0x022C 0x049C 0x06F0 0x3 0x2
1052 #define MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x0230 0x04A0 0x05E8 0x2 0x4
1060 #define MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK 0x0234 0x04A4 0x0534 0x2 0x1
1061 #define MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX 0x0234 0x04A4 0x06F4 0x3 0x2
1068 #define MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI 0x0238 0x04A8 0x053C 0x2 0x1
1075 #define MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 0x023C 0x04AC 0x0000 0x2 0x0
1081 #define MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 0x0240 0x04B0 0x0000 0x2 0x0
1087 #define MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 0x0244 0x04B4 0x0000 0x2 0x0
1093 #define MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY 0x0248 0x04B8 0x0000 0x2 0x0
1099 #define MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO 0x024C 0x04BC 0x0538 0x2 0x1
1105 #define MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 0x0250 0x04C0 0x0540 0x2 0x1
1111 #define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x0000 0x2 0x0
1117 #define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x0000 0x2 0x0
1122 #define MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 0x025C 0x04CC 0x0564 0x1 0x2
1123 #define MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x025C 0x04CC 0x06A0 0x2 0x1
1127 #define MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 0x025C 0x04CC 0x04E4 0x6 0x2
1131 #define MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x0260 0x04D0 0x06A8 0x2 0x1
1135 #define MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 0x0260 0x04D0 0x04E8 0x6 0x2
1139 #define MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x0264 0x04D4 0x06AC 0x2 0x1
1143 #define MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 0x0264 0x04D4 0x04EC 0x6 0x2
1147 #define MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x0268 0x04D8 0x0000 0x2 0x0
1151 #define MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 0x0268 0x04D8 0x04F0 0x6 0x2
H A Dimx50-pinfunc.h19 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
24 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
29 #define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0 0x028 0x2d4 0x000 0x2 0x0
34 #define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0
39 #define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0
44 #define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0
49 #define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0
54 #define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS 0x03c 0x2e8 0x7b0 0x2 0x0
59 #define MX50_PAD_I2C1_SCL__UART2_TXD_MUX 0x040 0x2ec 0x7cc 0x2 0x0
62 #define MX50_PAD_I2C1_SDA__UART2_RXD_MUX 0x044 0x2f0 0x7cc 0x2 0x1
65 #define MX50_PAD_I2C2_SCL__UART2_CTS 0x048 0x2f4 0x000 0x2 0x0
68 #define MX50_PAD_I2C2_SDA__UART2_RTS 0x04c 0x2f8 0x7c8 0x2 0x1
71 #define MX50_PAD_I2C3_SCL__FEC_MDC 0x050 0x2fc 0x000 0x2 0x0
78 #define MX50_PAD_I2C3_SDA__FEC_MDIO 0x054 0x300 0x774 0x2 0x0
86 #define MX50_PAD_PWM1__USBOH1_USBOTG_OC 0x058 0x304 0x7e8 0x2 0x1
92 #define MX50_PAD_PWM2__USBOH1_USBOTG_PWR 0x05c 0x308 0x000 0x2 0x0
98 #define MX50_PAD_OWIRE__USBOH1_USBH1_OC 0x060 0x30c 0x000 0x2 0x0
106 #define MX50_PAD_EPITO__USBOH1_USBH1_PWR 0x064 0x310 0x000 0x2 0x0
114 #define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB 0x068 0x314 0x000 0x2 0x0
135 #define MX50_PAD_SSI_RXFS__UART5_TXD_MUX 0x07c 0x328 0x7e4 0x2 0x0
143 #define MX50_PAD_SSI_RXC__UART5_RXD_MUX 0x080 0x32c 0x7e4 0x2 0x1
157 #define MX50_PAD_UART1_CTS__UART5_TXD_MUX 0x08c 0x338 0x7e4 0x2 0x2
163 #define MX50_PAD_UART1_RTS__UART5_RXD_MUX 0x090 0x33c 0x7e4 0x2 0x3
167 #define MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x094 0x340 0x7cc 0x0 0x2
182 #define MX50_PAD_UART2_RTS__UART2_RTS 0x0a0 0x34c 0x7c8 0x0 0x2
203 #define MX50_PAD_UART4_TXD__UART3_CTS 0x0ac 0x358 0x7d0 0x2 0x0
210 #define MX50_PAD_UART4_RXD__UART3_RTS 0x0b0 0x35c 0x7d0 0x2 0x1
225 #define MX50_PAD_ECSPI1_SCLK__CSPI_RDY 0x0c4 0x370 0x6e8 0x2 0x1
227 #define MX50_PAD_ECSPI1_SCLK__UART3_RTS 0x0c4 0x370 0x7d0 0x4 0x2
232 #define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0x0c8 0x374 0x6ec 0x2 0x1
239 #define MX50_PAD_ECSPI1_MISO__CSPI_SS2 0x0cc 0x378 0x6f0 0x2 0x1
246 #define MX50_PAD_ECSPI1_SS0__CSPI_SS3 0x0d0 0x37c 0x6f4 0x2 0x1
253 #define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN 0x0d4 0x380 0x000 0x2 0x0
261 #define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E 0x0d8 0x384 0x000 0x2 0x0
269 #define MX50_PAD_ECSPI2_MISO__ELCDIF_RS 0x0dc 0x388 0x000 0x2 0x0
277 #define MX50_PAD_ECSPI2_SS0__ELCDIF_CS 0x0e0 0x38c 0x000 0x2 0x0
302 #define MX50_PAD_SD2_CLK__MSHC_SCLK 0x0fc 0x3a8 0x000 0x2 0x0
305 #define MX50_PAD_SD2_CMD__MSHC_BS 0x100 0x3ac 0x000 0x2 0x0
308 #define MX50_PAD_SD2_D0__MSHC_DATA_0 0x104 0x3b0 0x000 0x2 0x0
312 #define MX50_PAD_SD2_D1__MSHC_DATA_1 0x108 0x3b4 0x000 0x2 0x0
316 #define MX50_PAD_SD2_D2__MSHC_DATA_2 0x10c 0x3b8 0x000 0x2 0x0
320 #define MX50_PAD_SD2_D3__MSHC_DATA_3 0x110 0x3bc 0x000 0x2 0x0
324 #define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS 0x114 0x3c0 0x6d0 0x2 0x0
330 #define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC 0x118 0x3c4 0x6cc 0x2 0x0
336 #define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD 0x11c 0x3c8 0x6c4 0x2 0x0
342 #define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS 0x120 0x3cc 0x6d8 0x2 0x0
348 #define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD 0x124 0x3d0 0x6c8 0x2 0x0
353 #define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC 0x128 0x3d4 0x6d4 0x2 0x0
358 #define MX50_PAD_DISP_D0__FEC_TX_CLK 0x12c 0x40c 0x78c 0x2 0x0
364 #define MX50_PAD_DISP_D1__FEC_RX_ERR 0x130 0x410 0x788 0x2 0x0
370 #define MX50_PAD_DISP_D2__FEC_RX_DV 0x134 0x414 0x784 0x2 0x0
376 #define MX50_PAD_DISP_D3__FEC_RDATA_1 0x138 0x418 0x77c 0x2 0x0
383 #define MX50_PAD_DISP_D4__FEC_RDATA_0 0x13c 0x41c 0x778 0x2 0x0
389 #define MX50_PAD_DISP_D5__FEC_TX_EN 0x140 0x420 0x000 0x2 0x0
395 #define MX50_PAD_DISP_D6__FEC_TDATA_1 0x144 0x424 0x000 0x2 0x0
402 #define MX50_PAD_DISP_D7__FEC_TDATA_0 0x148 0x428 0x000 0x2 0x0
408 #define MX50_PAD_DISP_WR__ELCDIF_DOTCLK 0x14c 0x42c 0x000 0x2 0x0
414 #define MX50_PAD_DISP_RD__ELCDIF_ENABLE 0x150 0x430 0x000 0x2 0x0
420 #define MX50_PAD_DISP_RS__ELCDIF_VSYNC 0x154 0x434 0x73c 0x2 0x1
426 #define MX50_PAD_DISP_CS__ELCDIF_HSYNC 0x158 0x438 0x6f8 0x2 0x1
431 #define MX50_PAD_DISP_BUSY__ELCDIF_BUSY 0x15c 0x43c 0x6f8 0x0 0x2
443 #define MX50_PAD_SD3_CMD__EIM_NANDF_WRN 0x164 0x444 0x000 0x2 0x0
447 #define MX50_PAD_SD3_CLK__EIM_NANDF_RDN 0x168 0x448 0x000 0x2 0x0
451 #define MX50_PAD_SD3_D0__EIM_NANDF_D_4 0x16c 0x44c 0x000 0x2 0x0
456 #define MX50_PAD_SD3_D1__EIM_NANDF_D_5 0x170 0x450 0x000 0x2 0x0
461 #define MX50_PAD_SD3_D2__EIM_NANDF_D_6 0x174 0x454 0x000 0x2 0x0
466 #define MX50_PAD_SD3_D3__EIM_NANDF_D_7 0x178 0x458 0x000 0x2 0x0
470 #define MX50_PAD_SD3_D4__EIM_NANDF_D_0 0x17c 0x45c 0x000 0x2 0x0
474 #define MX50_PAD_SD3_D5__EIM_NANDF_D_1 0x180 0x460 0x000 0x2 0x0
478 #define MX50_PAD_SD3_D6__EIM_NANDF_D_2 0x184 0x464 0x000 0x2 0x0
482 #define MX50_PAD_SD3_D7__EIM_NANDF_D_3 0x188 0x468 0x000 0x2 0x0
486 #define MX50_PAD_SD3_WP__EIM_NANDF_RESETN 0x18c 0x46C 0x000 0x2 0x0
492 #define MX50_PAD_DISP_D8__EIM_NANDF_CLE 0x190 0x470 0x000 0x2 0x0
494 #define MX50_PAD_DISP_D8__ESDHC4_CMD 0x190 0x470 0x74c 0x4 0x2
500 #define MX50_PAD_DISP_D9__EIM_NANDF_ALE 0x194 0x474 0x000 0x2 0x0
502 #define MX50_PAD_DISP_D9__ESDHC4_CLK 0x194 0x474 0x748 0x4 0x2
508 #define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0 0x198 0x478 0x000 0x2 0x0
516 #define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1 0x19c 0x47c 0x000 0x2 0x0
523 #define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2 0x1a0 0x480 0x000 0x2 0x0
531 #define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3 0x1a4 0x484 0x000 0x2 0x0
539 #define MX50_PAD_DISP_D14__EIM_NANDF_READY0 0x1a8 0x488 0x7b4 0x2 0x1
547 #define MX50_PAD_DISP_D15__EIM_NANDF_DQS 0x1ac 0x48c 0x7b0 0x2 0x1
555 #define MX50_PAD_EPDC_D0__EIM_WEIM_D_0 0x1b0 0x54c 0x7ec 0x2 0x1
562 #define MX50_PAD_EPDC_D1__EIM_WEIM_D_1 0x1b4 0x550 0x7f0 0x2 0x1
569 #define MX50_PAD_EPDC_D2__EIM_WEIM_D_2 0x1b8 0x554 0x7f4 0x2 0x1
571 #define MX50_PAD_EPDC_D2__ELCDIF_VSYNC 0x1b8 0x554 0x73c 0x4 0x2
576 #define MX50_PAD_EPDC_D3__EIM_WEIM_D_3 0x1bc 0x558 0x7f8 0x2 0x1
583 #define MX50_PAD_EPDC_D4__EIM_WEIM_D_4 0x1c0 0x55c 0x7fc 0x2 0x1
588 #define MX50_PAD_EPDC_D5__EIM_WEIM_D_5 0x1c4 0x560 0x800 0x2 0x1
593 #define MX50_PAD_EPDC_D6__EIM_WEIM_D_6 0x1c8 0x564 0x804 0x2 0x1
598 #define MX50_PAD_EPDC_D7__EIM_WEIM_D_7 0x1cc 0x568 0x808 0x2 0x1
603 #define MX50_PAD_EPDC_D8__EIM_WEIM_D_8 0x1d0 0x56c 0x80c 0x2 0x2
609 #define MX50_PAD_EPDC_D9__EIM_WEIM_D_9 0x1d4 0x570 0x810 0x2 0x2
615 #define MX50_PAD_EPDC_D10__EIM_WEIM_D_10 0x1d8 0x574 0x814 0x2 0x2
621 #define MX50_PAD_EPDC_D11__EIM_WEIM_D_11 0x1dc 0x578 0x818 0x2 0x2
627 #define MX50_PAD_EPDC_D12__EIM_WEIM_D_12 0x1e0 0x57c 0x81c 0x2 0x1
633 #define MX50_PAD_EPDC_D13__EIM_WEIM_D_13 0x1e4 0x580 0x820 0x2 0x1
639 #define MX50_PAD_EPDC_D14__EIM_WEIM_D_14 0x1e8 0x584 0x824 0x2 0x1
646 #define MX50_PAD_EPDC_D15__EIM_WEIM_D_15 0x1ec 0x588 0x828 0x2 0x1
653 #define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16 0x1f0 0x58c 0x000 0x2 0x0
660 #define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17 0x1f4 0x590 0x000 0x2 0x0
667 #define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18 0x1f8 0x594 0x000 0x2 0x0
674 #define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19 0x1f8 0x598 0x000 0x2 0x0
681 #define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20 0x200 0x59c 0x000 0x2 0x0
688 #define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21 0x204 0x5a0 0x000 0x2 0x0
695 #define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22 0x208 0x5a4 0x000 0x2 0x0
702 #define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23 0x20c 0x5a8 0x000 0x2 0x0
709 #define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24 0x210 0x5ac 0x000 0x2 0x0
716 #define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25 0x214 0x5b0 0x000 0x2 0x0
723 #define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26 0x218 0x5b4 0x000 0x2 0x0
730 #define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27 0x21c 0x5b8 0x000 0x2 0x0
737 #define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28 0x220 0x5bc 0x000 0x2 0x0
744 #define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29 0x224 0x5c0 0x000 0x2 0x0
751 #define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30 0x228 0x5c4 0x000 0x2 0x0
758 #define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31 0x22c 0x5c8 0x000 0x2 0x0
765 #define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2 0x230 0x5cc 0x000 0x2 0x0
770 #define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3 0x234 0x5d0 0x000 0x2 0x0
774 #define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3 0x238 0x5d4 0x000 0x2 0x0
801 #define MX50_PAD_EIM_DA0__KPP_COL_4 0x25c 0x5f8 0x790 0x3 0x2
806 #define MX50_PAD_EIM_DA1__KPP_ROW_4 0x260 0x5fc 0x7a0 0x3 0x2
811 #define MX50_PAD_EIM_DA2__KPP_COL_5 0x264 0x600 0x794 0x3 0x2
816 #define MX50_PAD_EIM_DA3__KPP_ROW_5 0x268 0x604 0x7a4 0x3 0x2
821 #define MX50_PAD_EIM_DA4__KPP_COL_6 0x26c 0x608 0x798 0x3 0x2
826 #define MX50_PAD_EIM_DA5__KPP_ROW_6 0x270 0x60c 0x7a8 0x3 0x2
831 #define MX50_PAD_EIM_DA6__KPP_COL_7 0x274 0x610 0x79c 0x3 0x2
836 #define MX50_PAD_EIM_DA7__KPP_ROW_7 0x278 0x614 0x7ac 0x3 0x2
841 #define MX50_PAD_EIM_DA8__EIM_NANDF_CLE 0x27c 0x618 0x000 0x2 0x0
846 #define MX50_PAD_EIM_DA9__EIM_NANDF_ALE 0x280 0x61c 0x000 0x2 0x0
851 #define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0 0x284 0x620 0x000 0x2 0x0
856 #define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1 0x288 0x624 0x000 0x2 0x0
861 #define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2 0x28c 0x628 0x000 0x2 0x0
867 #define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3 0x290 0x62c 0x000 0x2 0x0
873 #define MX50_PAD_EIM_DA14__EIM_NANDF_READY0 0x294 0x630 0x7b4 0x2 0x2
879 #define MX50_PAD_EIM_DA15__EIM_NANDF_DQS 0x298 0x634 0x7b0 0x2 0x2
885 #define MX50_PAD_EIM_CS2__EIM_WEIM_A_27 0x29c 0x638 0x000 0x2 0x0
903 #define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B 0x2b0 0x64c 0x000 0x2 0x0
H A Dimx6dl-pinfunc.h19 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
26 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
80 #define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0
87 #define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0
94 #define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0
101 #define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0
108 #define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0
115 #define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0
141 #define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0
146 #define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0
151 #define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0
156 #define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0
162 #define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0
166 #define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0
187 #define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0
192 #define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1
198 #define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1
204 #define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1
211 #define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1
218 #define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0
222 #define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1
227 #define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1
232 #define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1
237 #define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1
242 #define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0
246 #define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0
250 #define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0
255 #define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0
260 #define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0
264 #define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0
269 #define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0
274 #define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0
280 #define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0
286 #define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0
292 #define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0
298 #define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0
304 #define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0
310 #define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0
316 #define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0
323 #define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0
330 #define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0
343 #define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2
348 #define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2
352 #define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2
353 #define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0
360 #define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2
361 #define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0
368 #define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2
369 #define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0
377 #define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0
386 #define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0
394 #define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0
402 #define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0
410 #define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0
411 #define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0
420 #define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0
421 #define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0
430 #define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1
431 #define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0
440 #define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0
450 #define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0
460 #define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0
472 #define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1
483 #define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0
492 #define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0
494 #define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2
502 #define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0
508 #define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0
514 #define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1
520 #define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0
526 #define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1
542 #define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0
548 #define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0
554 #define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0
560 #define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0
566 #define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0
572 #define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0
578 #define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0
584 #define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0
590 #define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0
596 #define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1
603 #define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1
608 #define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2
617 #define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3
618 #define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0
628 #define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1
634 #define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2
639 #define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2
648 #define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0
653 #define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0
657 #define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0
662 #define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0
667 #define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0
672 #define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0
677 #define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0
681 #define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0
685 #define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0
689 #define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0
694 #define MX6QDL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1
702 #define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1
709 #define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0
711 #define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2
717 #define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1
723 #define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0
728 #define MX6QDL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2
730 #define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0
736 #define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1
741 #define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1
748 #define MX6QDL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1
752 #define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1
755 #define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2
759 #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2
764 #define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0
767 #define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2
774 #define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0
784 #define MX6QDL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1
791 #define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1
794 #define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2
799 #define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1
802 #define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2
805 #define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2
807 #define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0
814 #define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1
821 #define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1
823 #define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2
828 #define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1
836 #define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1
844 #define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1
849 #define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2
850 #define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1
857 #define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0
871 #define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0
875 #define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1
881 #define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1
884 #define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2
913 #define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2
950 #define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1
954 #define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0
958 #define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0
965 #define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0
969 #define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0
975 #define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0
981 #define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3
985 #define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2
990 #define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2
994 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0
996 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2
999 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0
1001 #define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2
1004 #define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2
1008 #define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2
1010 #define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2
1015 #define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0
1019 #define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2
1020 #define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0
1025 #define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1
1042 #define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2
1055 #define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2
1056 #define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0
1060 #define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0
1061 #define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3
1064 #define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0
1067 #define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0
1070 #define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
1075 #define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6
1076 #define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0
1079 #define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4
1080 #define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0
1083 #define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0
1084 #define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5
1087 #define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0
1088 #define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7
H A Dimx35-pinfunc.h19 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
25 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
34 #define MX35_PAD_GPIO1_0__OWIRE_LINE 0x010 0x334 0x990 0x2 0x0
37 #define MX35_PAD_GPIO1_1__PWM_PWMO 0x014 0x338 0x000 0x2 0x0
135 #define MX35_PAD_CS5__CSPI1_SS2 0x0b4 0x48c 0x7d8 0x2 0x1
156 #define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC 0x0c8 0x4cc 0x924 0x2 0x0
161 #define MX35_PAD_NFRE_B__IPU_DISPB_BCLK 0x0cc 0x4d0 0x000 0x2 0x0
166 #define MX35_PAD_NFALE__IPU_DISPB_CS0 0x0d0 0x4d4 0x000 0x2 0x0
171 #define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS 0x0d4 0x4d8 0x000 0x2 0x0
176 #define MX35_PAD_NFWP_B__IPU_DISPB_WR 0x0d8 0x4dc 0x000 0x2 0x0
180 #define MX35_PAD_NFRB__IPU_DISPB_RD 0x0dc 0x4e0 0x000 0x2 0x0
241 #define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR 0x118 0x55c 0x000 0x2 0x0
246 #define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC 0x11c 0x560 0x9f4 0x2 0x0
263 #define MX35_PAD_STXD5__CSPI2_MOSI 0x130 0x574 0x7ec 0x2 0x0
268 #define MX35_PAD_SRXD5__CSPI2_MISO 0x134 0x578 0x7e8 0x2 0x0
273 #define MX35_PAD_SCK5__CSPI2_SCLK 0x138 0x57c 0x7e0 0x2 0x0
277 #define MX35_PAD_STXFS5__CSPI2_RDY 0x13c 0x580 0x7e4 0x2 0x0
288 #define MX35_PAD_HCKR__CSPI2_SS0 0x148 0x58c 0x7f0 0x2 0x0
307 #define MX35_PAD_TX5_RX0__CSPI2_SS2 0x158 0x59c 0x7f8 0x2 0x1
314 #define MX35_PAD_TX4_RX1__CSPI2_SS3 0x15c 0x5a0 0x7fc 0x2 0x0
334 #define MX35_PAD_TX1__CSPI1_SS2 0x168 0x5ac 0x7d8 0x2 0x2
342 #define MX35_PAD_TX0__CSPI1_SS3 0x16c 0x5b0 0x7dc 0x2 0x0
356 #define MX35_PAD_CSPI1_SS0__CSPI2_SS3 0x178 0x5bc 0x7fc 0x2 0x1
361 #define MX35_PAD_CSPI1_SS1__CCM_CLK32K 0x17c 0x5c0 0x7d0 0x2 0x1
385 #define MX35_PAD_RTS1__I2C3_SCL 0x190 0x5d4 0x91c 0x2 0x1
393 #define MX35_PAD_CTS1__I2C3_SDA 0x194 0x5d8 0x920 0x2 0x1
403 #define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK 0x19c 0x5e0 0x994 0x1 0x2
408 #define MX35_PAD_RTS2__CAN2_RXCAN 0x1a0 0x5e4 0x7cc 0x2 0x1
416 #define MX35_PAD_CTS2__CAN2_TXCAN 0x1a4 0x5e8 0x000 0x2 0x0
490 #define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC 0x1f0 0x654 0x928 0x2 0x0
495 #define MX35_PAD_LD17__IPU_DISPB_CS2 0x1f4 0x658 0x000 0x2 0x0
501 #define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC 0x1f8 0x65c 0x928 0x2 0x1
509 #define MX35_PAD_LD19__IPU_DISPB_CS1 0x1fc 0x660 0x000 0x2 0x0
517 #define MX35_PAD_LD20__IPU_DISPB_SD_CLK 0x200 0x664 0x000 0x2 0x0
524 #define MX35_PAD_LD21__IPU_DISPB_SER_RS 0x204 0x668 0x000 0x2 0x0
532 #define MX35_PAD_LD22__IPU_DISPB_SD_D_I 0x208 0x66c 0x92c 0x2 0x0
540 #define MX35_PAD_LD23__IPU_DISPB_SD_D_IO 0x20c 0x670 0x92c 0x2 0x1
547 #define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO 0x210 0x674 0x92c 0x2 0x2
552 #define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK 0x214 0x678 0x000 0x2 0x0
557 #define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O 0x218 0x67c 0x000 0x2 0x0
558 #define MX35_PAD_D3_DRDY__GPIO1_0 0x218 0x67c 0x82c 0x5 0x2
562 #define MX35_PAD_CONTRAST__GPIO1_1 0x21c 0x680 0x838 0x5 0x2
566 #define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 0x220 0x684 0x000 0x2 0x0
571 #define MX35_PAD_D3_REV__IPU_DISPB_SER_RS 0x224 0x688 0x000 0x2 0x0
576 #define MX35_PAD_D3_CLS__IPU_DISPB_CS2 0x228 0x68c 0x000 0x2 0x0
577 #define MX35_PAD_D3_CLS__GPIO1_4 0x228 0x68c 0x850 0x5 0x2
581 #define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC 0x22c 0x690 0x928 0x2 0x2
582 #define MX35_PAD_D3_SPL__GPIO1_5 0x22c 0x690 0x854 0x5 0x2
587 #define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC 0x230 0x694 0x924 0x3 0x2
589 #define MX35_PAD_SD1_CMD__GPIO1_6 0x230 0x694 0x858 0x5 0x2
595 #define MX35_PAD_SD1_CLK__GPIO1_7 0x234 0x698 0x85c 0x5 0x2
601 #define MX35_PAD_SD1_DATA0__GPIO1_8 0x238 0x69c 0x860 0x5 0x2
622 #define MX35_PAD_SD2_CMD__I2C3_SCL 0x248 0x6ac 0x91c 0x1 0x2
623 #define MX35_PAD_SD2_CMD__ESDHC1_DAT4 0x248 0x6ac 0x804 0x2 0x0
624 #define MX35_PAD_SD2_CMD__IPU_CSI_D_2 0x248 0x6ac 0x938 0x3 0x2
626 #define MX35_PAD_SD2_CMD__GPIO2_0 0x248 0x6ac 0x868 0x5 0x2
630 #define MX35_PAD_SD2_CLK__I2C3_SDA 0x24c 0x6b0 0x920 0x1 0x2
631 #define MX35_PAD_SD2_CLK__ESDHC1_DAT5 0x24c 0x6b0 0x808 0x2 0x0
632 #define MX35_PAD_SD2_CLK__IPU_CSI_D_3 0x24c 0x6b0 0x93c 0x3 0x2
635 #define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 0x24c 0x6b0 0x998 0x6 0x2
639 #define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 0x250 0x6b4 0x80c 0x2 0x0
646 #define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 0x254 0x6b8 0x810 0x2 0x0
652 #define MX35_PAD_SD2_DATA2__CAN1_RXCAN 0x258 0x6bc 0x7c8 0x2 0x1
658 #define MX35_PAD_SD2_DATA3__CAN1_TXCAN 0x25c 0x6c0 0x000 0x2 0x0
676 #define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR 0x268 0x6cc 0x9c4 0x2 0x1
684 #define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP 0x26c 0x6d0 0x000 0x2 0x0
686 #define MX35_PAD_ATA_DIOW__CSPI2_MOSI 0x26c 0x6d0 0x7ec 0x4 0x2
692 #define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT 0x270 0x6d4 0x9c8 0x2 0x1
693 #define MX35_PAD_ATA_DMACK__CSPI2_MISO 0x270 0x6d4 0x7e8 0x4 0x2
699 #define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 0x274 0x6d8 0x9a4 0x2 0x1
701 #define MX35_PAD_ATA_RESET_B__CSPI2_RDY 0x274 0x6d8 0x7e4 0x4 0x2
707 #define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 0x278 0x6dc 0x9a8 0x2 0x1
715 #define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 0x27c 0x6e0 0x9ac 0x2 0x1
723 #define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 0x280 0x6e4 0x9b0 0x2 0x1
731 #define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 0x284 0x6e8 0x9b4 0x2 0x1
739 #define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 0x288 0x6ec 0x9b8 0x2 0x1
740 #define MX35_PAD_ATA_DATA3__CSPI2_SCLK 0x288 0x6ec 0x7e0 0x4 0x2
746 #define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 0x28c 0x6f0 0x9bc 0x2 0x1
751 #define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 0x290 0x6f4 0x9c0 0x2 0x1
757 #define MX35_PAD_ATA_DATA6__UART1_DTR 0x294 0x6f8 0x000 0x2 0x0
762 #define MX35_PAD_ATA_DATA7__CAN1_RXCAN 0x298 0x6fc 0x7c8 0x1 0x2
763 #define MX35_PAD_ATA_DATA7__UART1_DSR 0x298 0x6fc 0x000 0x2 0x0
769 #define MX35_PAD_ATA_DATA8__UART1_RI 0x29c 0x700 0x000 0x2 0x0
775 #define MX35_PAD_ATA_DATA9__UART1_DCD 0x2a0 0x704 0x000 0x2 0x0
780 #define MX35_PAD_ATA_DATA10__UART3_RXD_MUX 0x2a4 0x708 0x9a0 0x1 0x2
798 #define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 0x2b4 0x718 0x930 0x1 0x2
799 #define MX35_PAD_ATA_DATA14__KPP_ROW_0 0x2b4 0x718 0x970 0x3 0x2
803 #define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 0x2b8 0x71c 0x934 0x1 0x2
804 #define MX35_PAD_ATA_DATA15__KPP_ROW_1 0x2b8 0x71c 0x974 0x3 0x2
809 #define MX35_PAD_ATA_INTRQ__KPP_ROW_2 0x2bc 0x720 0x978 0x3 0x2
814 #define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 0x2c0 0x724 0x97c 0x3 0x2
818 #define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 0x2c4 0x728 0x940 0x1 0x2
819 #define MX35_PAD_ATA_DMARQ__KPP_COL_0 0x2c4 0x728 0x950 0x3 0x2
824 #define MX35_PAD_ATA_DA0__IPU_CSI_D_5 0x2c8 0x72c 0x944 0x1 0x2
825 #define MX35_PAD_ATA_DA0__KPP_COL_1 0x2c8 0x72c 0x954 0x3 0x2
830 #define MX35_PAD_ATA_DA1__IPU_CSI_D_6 0x2cc 0x730 0x948 0x1 0x2
831 #define MX35_PAD_ATA_DA1__KPP_COL_2 0x2cc 0x730 0x958 0x3 0x2
836 #define MX35_PAD_ATA_DA2__IPU_CSI_D_7 0x2d0 0x734 0x94c 0x1 0x2
837 #define MX35_PAD_ATA_DA2__KPP_COL_3 0x2d0 0x734 0x95c 0x3 0x2
849 #define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX 0x2e0 0x744 0x9a0 0x2 0x3
857 #define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX 0x2e4 0x748 0x000 0x2 0x0
865 #define MX35_PAD_FEC_RX_DV__UART3_RTS 0x2e8 0x74c 0x99c 0x2 0x2
873 #define MX35_PAD_FEC_COL__UART3_CTS 0x2ec 0x750 0x000 0x2 0x0
881 #define MX35_PAD_FEC_RDATA0__UART3_DTR 0x2f0 0x754 0x000 0x2 0x0
883 #define MX35_PAD_FEC_RDATA0__CSPI2_SS0 0x2f0 0x754 0x7f0 0x4 0x2
889 #define MX35_PAD_FEC_TDATA0__UART3_DSR 0x2f4 0x758 0x000 0x2 0x0
891 #define MX35_PAD_FEC_TDATA0__CSPI2_SS1 0x2f4 0x758 0x7f4 0x4 0x2
897 #define MX35_PAD_FEC_TX_EN__UART3_RI 0x2f8 0x75c 0x000 0x2 0x0
904 #define MX35_PAD_FEC_MDC__UART3_DCD 0x2fc 0x760 0x000 0x2 0x0
910 #define MX35_PAD_FEC_MDIO__CAN2_RXCAN 0x300 0x764 0x7cc 0x1 0x2
916 #define MX35_PAD_FEC_TX_ERR__OWIRE_LINE 0x304 0x768 0x990 0x1 0x2
917 #define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK 0x304 0x768 0x994 0x2 0x4
936 #define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC 0x310 0x774 0x000 0x2 0x0
937 #define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC 0x310 0x774 0x9f4 0x3 0x2
943 #define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS 0x314 0x778 0x7bc 0x2 0x1
949 #define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD 0x318 0x77c 0x7b4 0x2 0x1
954 #define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD 0x31c 0x780 0x7b0 0x2 0x1
959 #define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC 0x320 0x784 0x7c0 0x2 0x1
964 #define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS 0x324 0x788 0x7c4 0x2 0x1
H A Dimx53-pinfunc.h19 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
27 #define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x024 0x34c 0x758 0x2 0x0
34 #define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x028 0x350 0x74c 0x2 0x0
40 #define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x02c 0x354 0x75c 0x2 0x0
47 #define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x030 0x358 0x748 0x2 0x0
54 #define MX53_PAD_KEY_COL2__CAN1_TXCAN 0x034 0x35c 0x000 0x2 0x0
61 #define MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x038 0x360 0x760 0x2 0x0
68 #define MX53_PAD_KEY_COL3__USBOH3_H2_DP 0x03c 0x364 0x000 0x2 0x0
76 #define MX53_PAD_KEY_ROW3__USBOH3_H2_DM 0x040 0x368 0x000 0x2 0x0
84 #define MX53_PAD_KEY_COL4__CAN2_TXCAN 0x044 0x36c 0x000 0x2 0x0
91 #define MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x048 0x370 0x764 0x2 0x0
98 #define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x04c 0x378 0x000 0x2 0x0
104 #define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x050 0x37c 0x000 0x2 0x0
110 #define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x054 0x380 0x000 0x2 0x0
116 #define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x058 0x384 0x000 0x2 0x0
122 #define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x05c 0x388 0x000 0x2 0x0
129 #define MX53_PAD_DISP0_DAT0__CSPI_SCLK 0x060 0x38c 0x780 0x2 0x0
136 #define MX53_PAD_DISP0_DAT1__CSPI_MOSI 0x064 0x390 0x788 0x2 0x0
143 #define MX53_PAD_DISP0_DAT2__CSPI_MISO 0x068 0x394 0x784 0x2 0x0
150 #define MX53_PAD_DISP0_DAT3__CSPI_SS0 0x06c 0x398 0x78c 0x2 0x0
157 #define MX53_PAD_DISP0_DAT4__CSPI_SS1 0x070 0x39c 0x790 0x2 0x0
164 #define MX53_PAD_DISP0_DAT5__CSPI_SS2 0x074 0x3a0 0x794 0x2 0x0
171 #define MX53_PAD_DISP0_DAT6__CSPI_SS3 0x078 0x3a4 0x798 0x2 0x0
178 #define MX53_PAD_DISP0_DAT7__CSPI_RDY 0x07c 0x3a8 0x000 0x2 0x0
185 #define MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x080 0x3ac 0x000 0x2 0x0
192 #define MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x084 0x3b0 0x000 0x2 0x0
199 #define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x088 0x3b4 0x000 0x2 0x0
205 #define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x08c 0x3b8 0x000 0x2 0x0
211 #define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x090 0x3bc 0x000 0x2 0x0
229 #define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 0x09c 0x3c8 0x7ac 0x2 0x1
236 #define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0a0 0x3cc 0x7c0 0x2 0x0
244 #define MX53_PAD_DISP0_DAT17__ECSPI2_MISO 0x0a4 0x3d0 0x7bc 0x2 0x0
251 #define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 0x0a8 0x3d4 0x7c4 0x2 0x0
259 #define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0ac 0x3d8 0x7b8 0x2 0x0
267 #define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0b0 0x3dc 0x79c 0x2 0x1
274 #define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0b4 0x3e0 0x7a4 0x2 0x1
281 #define MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x0b8 0x3e4 0x7a0 0x2 0x1
288 #define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 0x0bc 0x3e8 0x7a8 0x2 0x1
299 #define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x0c4 0x3f0 0x000 0x2 0x0
315 #define MX53_PAD_CSI0_DAT4__KPP_COL_5 0x0d0 0x3fc 0x840 0x2 0x1
316 #define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 0x0d0 0x3fc 0x79c 0x3 0x2
323 #define MX53_PAD_CSI0_DAT5__KPP_ROW_5 0x0d4 0x400 0x84c 0x2 0x0
324 #define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 0x0d4 0x400 0x7a4 0x3 0x2
331 #define MX53_PAD_CSI0_DAT6__KPP_COL_6 0x0d8 0x404 0x844 0x2 0x0
332 #define MX53_PAD_CSI0_DAT6__ECSPI1_MISO 0x0d8 0x404 0x7a0 0x3 0x2
339 #define MX53_PAD_CSI0_DAT7__KPP_ROW_6 0x0dc 0x408 0x850 0x2 0x0
340 #define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 0x0dc 0x408 0x7a8 0x3 0x2
347 #define MX53_PAD_CSI0_DAT8__KPP_COL_7 0x0e0 0x40c 0x848 0x2 0x0
355 #define MX53_PAD_CSI0_DAT9__KPP_ROW_7 0x0e4 0x410 0x854 0x2 0x0
363 #define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x0e8 0x414 0x000 0x2 0x0
371 #define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x0ec 0x418 0x878 0x2 0x1
379 #define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x0f0 0x41c 0x000 0x2 0x0
386 #define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x0f4 0x420 0x890 0x2 0x3
393 #define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 0x0f8 0x424 0x000 0x2 0x0
400 #define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 0x0fc 0x428 0x898 0x2 0x3
407 #define MX53_PAD_CSI0_DAT16__UART4_RTS 0x100 0x42c 0x88c 0x2 0x0
414 #define MX53_PAD_CSI0_DAT17__UART4_CTS 0x104 0x430 0x000 0x2 0x0
421 #define MX53_PAD_CSI0_DAT18__UART5_RTS 0x108 0x434 0x894 0x2 0x2
428 #define MX53_PAD_CSI0_DAT19__UART5_CTS 0x10c 0x438 0x000 0x2 0x0
435 #define MX53_PAD_EIM_A25__ECSPI2_RDY 0x110 0x458 0x000 0x2 0x0
442 #define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 0x114 0x45c 0x76c 0x2 0x0
448 #define MX53_PAD_EIM_D16__IPU_DI0_PIN5 0x118 0x460 0x000 0x2 0x0
454 #define MX53_PAD_EIM_D17__IPU_DI0_PIN6 0x11c 0x464 0x000 0x2 0x0
460 #define MX53_PAD_EIM_D18__IPU_DI0_PIN7 0x120 0x468 0x000 0x2 0x0
467 #define MX53_PAD_EIM_D19__IPU_DI0_PIN8 0x124 0x46c 0x000 0x2 0x0
469 #define MX53_PAD_EIM_D19__ECSPI1_SS1 0x124 0x46c 0x7ac 0x4 0x2
475 #define MX53_PAD_EIM_D20__IPU_DI0_PIN16 0x128 0x470 0x000 0x2 0x0
483 #define MX53_PAD_EIM_D21__IPU_DI0_PIN17 0x12c 0x474 0x000 0x2 0x0
490 #define MX53_PAD_EIM_D22__IPU_DI0_PIN1 0x130 0x478 0x000 0x2 0x0
496 #define MX53_PAD_EIM_D23__UART3_CTS 0x134 0x47c 0x000 0x2 0x0
504 #define MX53_PAD_EIM_EB3__UART3_RTS 0x138 0x480 0x884 0x2 0x1
511 #define MX53_PAD_EIM_D24__UART3_TXD_MUX 0x13c 0x484 0x000 0x2 0x0
519 #define MX53_PAD_EIM_D25__UART3_RXD_MUX 0x140 0x488 0x888 0x2 0x1
527 #define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0
535 #define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1
543 #define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0
551 #define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1
553 #define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2
559 #define MX53_PAD_EIM_D30__UART3_CTS 0x154 0x49c 0x000 0x2 0x0
567 #define MX53_PAD_EIM_D31__UART3_RTS 0x158 0x4a0 0x884 0x2 0x3
575 #define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x15c 0x4a8 0x000 0x2 0x0
581 #define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x160 0x4ac 0x000 0x2 0x0
587 #define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x164 0x4b0 0x000 0x2 0x0
592 #define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x168 0x4b4 0x000 0x2 0x0
597 #define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x16c 0x4b8 0x000 0x2 0x0
602 #define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x170 0x4bc 0x000 0x2 0x0
607 #define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x174 0x4c0 0x000 0x2 0x0
612 #define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x178 0x4c4 0x000 0x2 0x0
617 #define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x17c 0x4c8 0x000 0x2 0x0
622 #define MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x180 0x4cc 0x7b8 0x2 0x2
626 #define MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x184 0x4d0 0x7c0 0x2 0x2
630 #define MX53_PAD_EIM_OE__ECSPI2_MISO 0x188 0x4d4 0x7bc 0x2 0x2
635 #define MX53_PAD_EIM_RW__ECSPI2_SS0 0x18c 0x4d8 0x7c4 0x2 0x2
640 #define MX53_PAD_EIM_LBA__ECSPI2_SS1 0x190 0x4dc 0x7c8 0x2 0x1
735 #define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 0x1e4 0x534 0x000 0x2 0x0
783 #define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0
791 #define MX53_PAD_NANDF_CS3__IPU_SISG_1 0x244 0x5bc 0x000 0x2 0x0
798 #define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0
805 #define MX53_PAD_FEC_REF_CLK__ESAI1_FSR 0x24c 0x5c8 0x7cc 0x2 0x0
810 #define MX53_PAD_FEC_RX_ER__ESAI1_HCKR 0x250 0x5cc 0x7d4 0x2 0x0
815 #define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0
818 #define MX53_PAD_FEC_RXD1__ESAI1_FST 0x258 0x5d4 0x7d0 0x2 0x0
823 #define MX53_PAD_FEC_RXD0__ESAI1_HCKT 0x25c 0x5d8 0x7d8 0x2 0x0
827 #define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 0x260 0x5dc 0x7f0 0x2 0x0
830 #define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 0x264 0x5e0 0x7ec 0x2 0x0
835 #define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 0x268 0x5e4 0x7f4 0x2 0x0
839 #define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 0x26c 0x5e8 0x7f8 0x2 0x0
874 #define MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x288 0x608 0x000 0x2 0x0
880 #define MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x28c 0x60c 0x000 0x2 0x0
886 #define MX53_PAD_PATA_DA_0__ESDHC3_RST 0x290 0x610 0x000 0x2 0x0
891 #define MX53_PAD_PATA_DA_1__ESDHC4_CMD 0x294 0x614 0x000 0x2 0x0
896 #define MX53_PAD_PATA_DA_2__ESDHC4_CLK 0x298 0x618 0x000 0x2 0x0
958 #define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x2c4 0x648 0x000 0x2 0x0
965 #define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x2c8 0x64c 0x000 0x2 0x0
972 #define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x2cc 0x650 0x000 0x2 0x0
979 #define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x2d0 0x654 0x000 0x2 0x0
986 #define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 0x2d4 0x658 0x000 0x2 0x0
993 #define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 0x2d8 0x65c 0x000 0x2 0x0
1000 #define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 0x2dc 0x660 0x000 0x2 0x0
1007 #define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 0x2e0 0x664 0x000 0x2 0x0
1015 #define MX53_PAD_SD1_DATA0__CSPI_MISO 0x2e4 0x66c 0x784 0x5 0x2
1025 #define MX53_PAD_SD1_CMD__CSPI_MOSI 0x2ec 0x674 0x788 0x5 0x2
1029 #define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 0x2f0 0x678 0x000 0x2 0x0
1032 #define MX53_PAD_SD1_DATA2__CSPI_SS1 0x2f0 0x678 0x790 0x5 0x2
1037 #define MX53_PAD_SD1_CLK__OSC32k_32K_OUT 0x2f4 0x67c 0x000 0x2 0x0
1039 #define MX53_PAD_SD1_CLK__CSPI_SCLK 0x2f4 0x67c 0x780 0x5 0x2
1043 #define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 0x2f8 0x680 0x000 0x2 0x0
1046 #define MX53_PAD_SD1_DATA3__CSPI_SS2 0x2f8 0x680 0x794 0x5 0x2
1051 #define MX53_PAD_SD2_CLK__KPP_COL_5 0x2fc 0x688 0x840 0x2 0x2
1057 #define MX53_PAD_SD2_CMD__KPP_ROW_5 0x300 0x68c 0x84c 0x2 0x1
1063 #define MX53_PAD_SD2_DATA3__KPP_COL_6 0x304 0x690 0x844 0x2 0x1
1069 #define MX53_PAD_SD2_DATA2__KPP_ROW_6 0x308 0x694 0x850 0x2 0x1
1075 #define MX53_PAD_SD2_DATA1__KPP_COL_7 0x30c 0x698 0x848 0x2 0x1
1081 #define MX53_PAD_SD2_DATA0__KPP_ROW_7 0x310 0x69c 0x854 0x2 0x1
1087 #define MX53_PAD_GPIO_0__KPP_COL_5 0x314 0x6a4 0x840 0x2 0x3
1095 #define MX53_PAD_GPIO_1__KPP_ROW_5 0x318 0x6a8 0x84c 0x2 0x2
1103 #define MX53_PAD_GPIO_9__KPP_COL_6 0x31c 0x6ac 0x844 0x2 0x2
1111 #define MX53_PAD_GPIO_3__I2C3_SCL 0x320 0x6b0 0x824 0x2 0x1
1116 #define MX53_PAD_GPIO_3__MLB_MLBCLK 0x320 0x6b0 0x858 0x7 0x2
1119 #define MX53_PAD_GPIO_6__I2C3_SDA 0x324 0x6b4 0x828 0x2 0x1
1124 #define MX53_PAD_GPIO_6__MLB_MLBSIG 0x324 0x6b4 0x860 0x7 0x2
1127 #define MX53_PAD_GPIO_2__KPP_ROW_6 0x328 0x6b8 0x850 0x2 0x2
1132 #define MX53_PAD_GPIO_2__MLB_MLBDAT 0x328 0x6b8 0x85c 0x7 0x2
1135 #define MX53_PAD_GPIO_4__KPP_COL_7 0x32c 0x6bc 0x848 0x2 0x2
1143 #define MX53_PAD_GPIO_5__KPP_ROW_7 0x330 0x6c0 0x854 0x2 0x2
1147 #define MX53_PAD_GPIO_5__I2C3_SCL 0x330 0x6c0 0x824 0x6 0x2
1151 #define MX53_PAD_GPIO_7__EPIT1_EPITO 0x334 0x6c4 0x000 0x2 0x0
1159 #define MX53_PAD_GPIO_8__EPIT2_EPITO 0x338 0x6c8 0x000 0x2 0x0
1160 #define MX53_PAD_GPIO_8__CAN1_RXCAN 0x338 0x6c8 0x760 0x3 0x2
1167 #define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 0x33c 0x6cc 0x000 0x2 0x0
1170 #define MX53_PAD_GPIO_16__I2C3_SDA 0x33c 0x6cc 0x828 0x6 0x2
1174 #define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 0x340 0x6d0 0x868 0x2 0x1
1182 #define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 0x344 0x6d4 0x86c 0x2 0x1
H A Dimx6sx-pinfunc.h19 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
27 #define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0
35 #define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0
43 #define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0
52 #define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0
61 #define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0
70 #define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0
79 #define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0
88 #define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0
97 #define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0
106 #define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0
114 #define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2
115 #define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0
124 #define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0
133 #define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0
142 #define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1
152 #define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1
162 #define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1
172 #define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1
182 #define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0
193 #define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1
204 #define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2
214 #define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2
224 #define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1
225 #define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2
234 #define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0
235 #define MX6SX_PAD_CSI_MCLK__UART4_RX 0x0070 0x03B8 0x0848 0x3 0x2
245 #define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0
251 #define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2
256 #define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1
266 #define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1
276 #define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1
286 #define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1
293 #define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2
294 #define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0
302 #define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1
312 #define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1
322 #define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1
323 #define MX6SX_PAD_ENET2_COL__UART1_RX 0x0094 0x03DC 0x0830 0x3 0x2
332 #define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2
333 #define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1
344 #define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1
345 #define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2
354 #define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1
364 #define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2
373 #define MX6SX_PAD_KEY_COL1__UART6_RX 0x00A8 0x03F0 0x0858 0x2 0x2
374 #define MX6SX_PAD_KEY_COL1__UART6_TX 0x00A8 0x03F0 0x0000 0x2 0x0
382 #define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2
390 #define MX6SX_PAD_KEY_COL3__UART5_RX 0x00B0 0x03F8 0x0850 0x2 0x2
391 #define MX6SX_PAD_KEY_COL3__UART5_TX 0x00B0 0x03F8 0x0000 0x2 0x0
399 #define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2
407 #define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0
416 #define MX6SX_PAD_KEY_ROW1__UART6_RX 0x00BC 0x0404 0x0858 0x2 0x3
417 #define MX6SX_PAD_KEY_ROW1__UART6_TX 0x00BC 0x0404 0x0000 0x2 0x0
426 #define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0
434 #define MX6SX_PAD_KEY_ROW3__UART5_RX 0x00C4 0x040C 0x0850 0x2 0x3
435 #define MX6SX_PAD_KEY_ROW3__UART5_TX 0x00C4 0x040C 0x0000 0x2 0x0
443 #define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2
451 #define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1
461 #define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0
471 #define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0
481 #define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0
491 #define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0
609 #define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0
628 #define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0
638 #define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0
647 #define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0
657 #define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0
667 #define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0
677 #define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0
687 #define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1
697 #define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1
707 #define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1
717 #define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1
727 #define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0
737 #define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0
747 #define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0
757 #define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0
767 #define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0
777 #define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0
787 #define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0
797 #define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0
807 #define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0
817 #define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0
827 #define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0
838 #define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0
849 #define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0
859 #define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0
869 #define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0
879 #define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0
888 #define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2
889 #define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1
890 #define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2
897 #define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2
898 #define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1
899 #define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2
907 #define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0
908 #define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2
915 #define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2
916 #define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0
917 #define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2
925 #define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0
933 #define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2
934 #define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1
935 #define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2
943 #define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1
944 #define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2
951 #define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2
952 #define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2
961 #define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1
962 #define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2
969 #define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1
970 #define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2
976 #define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2
977 #define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0
978 #define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2
984 #define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2
985 #define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0
986 #define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2
993 #define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0
1002 #define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1
1003 #define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2
1011 #define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1
1018 #define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2
1019 #define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2
1063 #define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1
1070 #define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1
1077 #define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1
1084 #define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1
1091 #define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1
1099 #define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0
1106 #define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0
1113 #define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0
1120 #define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0
1127 #define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0
1147 #define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1
1155 #define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1
1163 #define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1
1171 #define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1
1179 #define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1
1187 #define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0
1195 #define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0
1205 #define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0
1215 #define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0
1217 #define MX6SX_PAD_SD1_DATA0__UART2_RX 0x0228 0x0570 0x0838 0x4 0x2
1226 #define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0
1237 #define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0
1246 #define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2
1251 #define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2
1254 #define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2
1255 #define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1
1257 #define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2
1264 #define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2
1265 #define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1
1267 #define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2
1274 #define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2
1275 #define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1
1285 #define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2
1286 #define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1
1296 #define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2
1297 #define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1
1299 #define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2
1307 #define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2
1308 #define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1
1310 #define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2
1319 #define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0
1329 #define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0
1338 #define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0
1348 #define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0
1358 #define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0
1369 #define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0
1379 #define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0
1380 #define MX6SX_PAD_SD3_DATA4__UART3_RX 0x0268 0x05B0 0x0840 0x3 0x2
1390 #define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0
1401 #define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0
1402 #define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2
1411 #define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0
1421 #define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1
1431 #define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1
1441 #define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1
1451 #define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1
1461 #define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0
1471 #define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0
1481 #define MX6SX_PAD_SD4_DATA4__UART5_RX 0x0290 0x05D8 0x0850 0x2 0x0
1482 #define MX6SX_PAD_SD4_DATA4__UART5_TX 0x0290 0x05D8 0x0000 0x2 0x0
1492 #define MX6SX_PAD_SD4_DATA5__UART5_RX 0x0294 0x05DC 0x0850 0x2 0x1
1493 #define MX6SX_PAD_SD4_DATA5__UART5_TX 0x0294 0x05DC 0x0000 0x2 0x0
1503 #define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0
1513 #define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0
1523 #define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0
1533 #define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0
1539 #define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0
/linux-4.4.14/include/uapi/linux/netfilter/
H A Dxt_devgroup.h8 XT_DEVGROUP_INVERT_SRC = 0x2,
H A Dxt_policy.h10 XT_POLICY_MATCH_OUT = 0x2,
/linux-4.4.14/include/linux/mfd/wm8350/
H A Dgpio.h41 #define WM8350_GPIO0_LDO_EN_IN 0x2
42 #define WM8350_GPIO0_VRTC_OUT 0x2
50 #define WM8350_GPIO1_LDO_EN_IN 0x2
51 #define WM8350_GPIO1_RESET_OUT 0x2
59 #define WM8350_GPIO2_WAKE_UP_IN 0x2
60 #define WM8350_GPIO2_VRTC_OUT 0x2
68 #define WM8350_GPIO3_LDO_EN_IN 0x2
69 #define WM8350_GPIO3_VRTC_OUT 0x2
77 #define WM8350_GPIO4_FLASH_IN 0x2
78 #define WM8350_GPIO4_ADA_OUT 0x2
88 #define WM8350_GPIO5_ADCLRCLK_IN 0x2
89 #define WM8350_GPIO5_ADCLRCLK_OUT 0x2
101 #define WM8350_GPIO6_FLASH_IN 0x2
102 #define WM8350_GPIO6_ADA_OUT 0x2
114 #define WM8350_GPIO7_MASK_IN 0x2
115 #define WM8350_GPIO7_VCC_FAULT_OUT 0x2
127 #define WM8350_GPIO8_ADCBCLK_IN 0x2
128 #define WM8350_GPIO8_ADCBCLK_OUT 0x2
137 #define WM8350_GPIO9_MASK_IN 0x2
138 #define WM8350_GPIO9_LINE_GT_BATT_OUT 0x2
146 #define WM8350_GPIO10_PWR_OFF_IN 0x2
147 #define WM8350_GPIO10_LINE_GT_BATT_OUT 0x2
153 #define WM8350_GPIO11_WAKEUP_IN 0x2
154 #define WM8350_GPIO11_LINE_GT_BATT_OUT 0x2
160 #define WM8350_GPIO12_LINE_GT_BATT_OUT 0x2
/linux-4.4.14/sound/soc/codecs/
H A Dtas2552.h53 #define TAS2552_PLL_SRC_IVCLKIN (0x2 << 4)
68 #define TAS2552_WCLK_FREQ_16KHZ (0x2 << 0)
77 #define TAS2552_DIN_SRC_SEL_RIGHT (0x2 << 3)
89 #define TAS2552_WORDLENGTH_24BIT (0x2 << 0)
94 #define TAS2552_DATAFORMAT_RIGHT_J (0x2 << 2)
99 #define TAS2552_CLKSPERFRAME_128 (0x2 << 4)
108 #define TAS2552_DATA_OUT_VBAT_DATA (0x2)
118 #define TAS2552_PDM_DATA_SEL_I_V (0x2 << 6)
125 #define TAS2552_PDM_CLK_SEL_BCLK (0x2 << 0)
133 #define TAS2552_APT_DELAY_125 (0x2 << 0)
137 #define TAS2552_APT_THRESH_14_11 (0x2 << 2)
H A Dad1836.h49 #define AD1836_WORD_LEN_16 0x2
H A Dak4535.h22 #define AK4535_SIG1 0x2
H A Drt5670-dsp.h34 #define RT5670_DSP_CLK_192K (0x2 << 6)
41 #define RT5670_DSP_DL_2 (0x2 << 2)
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_enum.h30 DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2,
50 DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2,
58 DCIO_UNIPHYC_FBDIV_CLK = 0x2,
66 DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2,
74 DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2,
82 DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2,
100 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2,
118 DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2,
124 DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2,
130 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2,
140 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2,
158 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
172 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
178 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2,
236 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2,
258 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
274 DCIO_GSL_SEL_GROUP_2 = 0x2,
279 DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2,
284 DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2,
289 DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2,
294 DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2,
299 DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2,
307 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
314 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
321 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
328 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
335 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
342 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
349 DCIO_GPU_TIMER_START_2_END_29 = 0x2,
359 DCIO_TEST_CLK_SEL_SCLK = 0x2,
372 DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2,
382 DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2,
396 DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2,
414 DCIO_DPHY_LANE_SEL_LANE2 = 0x2,
420 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2,
458 DCIO_IMPCAL_STEP_DELAY_3us = 0x2,
544 DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2,
566 INPUTCSC_MODE_B = 0x2,
572 INPUTCSC_TYPE_8_4 = 0x2,
581 PRESCALE_MODE_UNITY = 0x2,
586 COL_MAN_OUTPUT_CSC_YCrCb601 = 0x2,
594 DENORM_CLAMP_CONTROL_10 = 0x2,
600 GAMMA_CORR_CONTROL_B = 0x2,
605 ENDIAN_8IN32 = 0x2,
611 ARRAY_1D_TILED_THIN1 = 0x2,
629 CONFIG_4_PIPE = 0x2,
643 CONFIG_4KB_ROW = 0x2,
653 CONFIG_512B_SWAPS = 0x2,
659 CONFIG_4KB_SPLIT = 0x2,
665 ADDR_CONFIG_4_PIPE = 0x2,
675 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
689 ADDR_CONFIG_4_GPU = 0x2,
694 ADDR_CONFIG_GPU_TILE_64 = 0x2,
700 ADDR_CONFIG_4KB_ROW = 0x2,
709 DBG_CLIENT_BLKID_scf2 = 0x2,
869 DBG_BLOCK_ID_VMC = 0x2,
1103 DBG_BLOCK_ID_CG_BY2 = 0x2,
1221 DBG_BLOCK_ID_CSC_BY4 = 0x2,
1281 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
1312 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
1329 ABGR_TO_A_BG_G_RB = 0x2,
1335 REF_EQUAL = 0x2,
1349 DEPTH_X8_24 = 0x2,
1359 Z_24 = 0x2,
1369 CMASK_CLEAR_ALL = 0x2,
1387 EXPORT_32_GR = 0x2,
1397 EXPORT_4P_32BPC_GR = 0x2,
1405 COLOR_16 = 0x2,
1431 FMT_16 = 0x2,
1497 BUF_DATA_FORMAT_16 = 0x2,
1515 IMG_DATA_FORMAT_16 = 0x2,
1581 BUF_NUM_FORMAT_USCALED = 0x2,
1591 IMG_NUM_FORMAT_USCALED = 0x2,
1617 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1624 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1633 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1639 ADDR_SURF_P2_RESERVED1 = 0x2,
1659 ADDR_SURF_8_BANK = 0x2,
1665 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1671 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1677 ADDR_SURF_BANK_WH_4 = 0x2,
1683 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1689 GATCL1_TYPE_BYPASS = 0x2,
1698 MTYPE_CC = 0x2,
1704 PERFMON_COUNTER_MODE_MAX = 0x2,
1717 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1734 ARRAY_3D = 0x2,
1752 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1766 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
H A Ddce_11_0_enum.h38 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2,
80 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2,
113 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
136 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2,
153 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
176 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2,
194 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2,
212 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2,
239 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2,
261 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2,
287 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2,
313 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2,
419 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2,
433 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2,
451 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x2,
457 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2,
463 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2,
528 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x2,
534 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2,
544 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x2,
554 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x2,
584 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2,
602 CRTC_HORZ_REPETITION_COUNT_2 = 0x2,
620 PERFCOUNTER_CVALUE_SEL_31_16 = 0x2,
630 PERFCOUNTER_INC_MODE_LSB = 0x2,
672 PERFCOUNTER_CNTL_SEL_2 = 0x2,
682 PERFCOUNTER_CNT0_STATE_FREEZE = 0x2,
692 PERFCOUNTER_CNT1_STATE_FREEZE = 0x2,
702 PERFCOUNTER_CNT2_STATE_FREEZE = 0x2,
712 PERFCOUNTER_CNT3_STATE_FREEZE = 0x2,
722 PERFCOUNTER_CNT4_STATE_FREEZE = 0x2,
732 PERFCOUNTER_CNT5_STATE_FREEZE = 0x2,
742 PERFCOUNTER_CNT6_STATE_FREEZE = 0x2,
752 PERFCOUNTER_CNT7_STATE_FREEZE = 0x2,
762 PERFMON_STATE_FREEZE = 0x2,
780 LPT_NUM_BANKS_8BANK = 0x2,
787 DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2,
807 DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2,
818 DCIO_UNIPHYC_FBDIV_CLK = 0x2,
829 DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2,
840 DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2,
851 DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2,
869 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2,
887 DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2,
893 DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2,
899 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2,
909 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2,
927 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
941 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
947 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2,
1005 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2,
1027 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
1043 DCIO_GSL_SEL_GROUP_2 = 0x2,
1048 DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2,
1053 DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2,
1058 DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2,
1063 DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2,
1068 DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2,
1076 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
1083 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
1090 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
1097 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
1104 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
1111 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
1118 DCIO_GPU_TIMER_START_2_END_29 = 0x2,
1128 DCIO_TEST_CLK_SEL_SCLK = 0x2,
1137 DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2,
1147 DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2,
1161 DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2,
1179 DCIO_DPHY_LANE_SEL_LANE2 = 0x2,
1185 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2,
1207 DCIO_IMPCAL_STEP_DELAY_3us = 0x2,
1293 DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2,
1315 DCP_GRPH_DEPTH_32BPP = 0x2,
1321 DCP_GRPH_NUM_BANKS_8BANK = 0x2,
1327 DCP_GRPH_BANK_WIDTH_4 = 0x2,
1333 DCP_GRPH_FORMAT_32BPP = 0x2,
1339 DCP_GRPH_BANK_HEIGHT_4 = 0x2,
1345 DCP_GRPH_TILE_SPLIT_256B = 0x2,
1362 DCP_GRPH_MACRO_TILE_ASPECT_4 = 0x2,
1368 DCP_GRPH_ARRAY_MODE_2 = 0x2,
1378 DCP_GRPH_MICRO_TILE_MODE_2 = 0x2,
1396 DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x2,
1402 DCP_GRPH_RED_CROSSBAR_FROM_B = 0x2,
1408 DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x2,
1414 DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x2,
1420 DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x2,
1486 DCP_GRPH_DFQ_SIZE_DEEP3 = 0x2,
1496 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x2,
1542 DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x2,
1548 DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x2,
1558 DCP_DENORM_MODE_8BIT = 0x2,
1572 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x2,
1590 DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x2,
1596 DCP_GRPH_DEGAMMA_MODE_ROMB = 0x2,
1602 DCP_CURSOR2_DEGAMMA_MODE_ROMB = 0x2,
1608 DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x2,
1614 DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x2,
1624 DCP_SPATIAL_DITHER_MODE_ROMB = 0x2,
1630 DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x2,
1656 DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x2,
1670 DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x2,
1693 DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x2,
1707 DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI = 0x2,
1721 DCP_CURSOR2_URGENT_CONTROL_MODE_2 = 0x2,
1744 DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED = 0x2,
1786 DCP_DC_LUT_INC_B_4 = 0x2,
1806 DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x2,
1812 DCP_DC_LUT_INC_G_4 = 0x2,
1832 DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x2,
1838 DCP_DC_LUT_INC_R_4 = 0x2,
1858 DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x2,
1868 DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x2,
1874 DCP_CRC_LINE_SEL_ODD = 0x2,
1880 DCP_GRPH_FLIP_RATE_3FRAME = 0x2,
1910 DCP_GSL_XDMA_GROUP_HSYNC1 = 0x2,
1920 DCP_GSL_SYNC_SOURCE_RESET = 0x2,
1938 DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x2,
1948 DCP_GRPH_ROTATION_ANGLE_180 = 0x2,
1962 DCP_GRPH_REGAMMA_MODE_XVYCC = 0x2,
1997 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x2,
2039 HDMI_DEEP_COLOR_DEPTH_36BPP = 0x2,
2045 HDMI_AUDIO_DELAY_56CLK = 0x2,
2063 HDMI_ACR_SELECT_44K = 0x2,
2073 HDMI_ACR_2_MULTIPLE = 0x2,
2175 TMDS_COLOR_FORMAT_DUAL30BPP = 0x2,
2181 TMDS_STEREOSYNC_CTL2 = 0x2,
2187 TMDS_CTL0_DATA_SEL2_VSYNC = 0x2,
2197 TMDS_CTL0_DATA_DELAY_2PIX = 0x2,
2211 TMDS_CTL0_DATA_MODULATION_BIT1 = 0x2,
2221 TMDS_CTL1_DATA_SEL2_VSYNC = 0x2,
2231 TMDS_CTL1_DATA_DELAY_2PIX = 0x2,
2245 TMDS_CTL1_DATA_MODULATION_BIT1 = 0x2,
2255 TMDS_CTL2_DATA_SEL2_VSYNC = 0x2,
2265 TMDS_CTL2_DATA_DELAY_2PIX = 0x2,
2279 TMDS_CTL2_DATA_MODULATION_BIT1 = 0x2,
2289 TMDS_CTL3_DATA_DELAY_2PIX = 0x2,
2303 TMDS_CTL3_DATA_MODULATION_BIT1 = 0x2,
2313 TMDS_CTL3_DATA_SEL2_VSYNC = 0x2,
2323 DIG_FE_SOURCE_FROM_FMT2 = 0x2,
2329 DIG_FE_STEREOSYNC_FROM_FMT2 = 0x2,
2343 DIG_OUTPUT_CRC_FOR_VBI = 0x2,
2429 AFMT_AUDIO_CRC_CH2_SIG = 0x2,
2457 AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x2,
2466 DIG_BE_TMDS_DVI_MODE = 0x2,
2476 DIG_BE_CNTL_HPD3 = 0x2,
2508 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x2,
2550 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x2,
2556 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x2,
2570 DP_PIXEL_ENCODING_YCBCR444 = 0x2,
2586 DP_COMPONENT_DEPTH_10BPC = 0x2,
2598 DP_UDI_LANES_RESERVED = 0x2,
2604 DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x2,
2677 DPHY_TRAINING_PATTERN_3 = 0x2,
2698 DPHY_PRBS11_SELECTED = 0x2,
2719 DPHY_CRC_LANE2_SELECTED = 0x2,
2749 DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x2,
2754 DP_MSE_LINK_LINE_128_MTP_LONG = 0x2,
2776 DP_DPHY_HBR2_PATTERN_2_NEG = 0x2,
2815 DP_AUX_CONTROL_HPD3_SELECTED = 0x2,
2835 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x2,
2861 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x2,
2867 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x2,
2877 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US= 0x2,
2885 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x2,
2895 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD= 0x2,
2905 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES= 0x2,
2923 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS= 0x2,
2929 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x2,
2939 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x2,
2953 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US= 0x2,
2959 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS= 0x2,
2965 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128= 0x2,
3007 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x2,
3012 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x2,
3017 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP= 0x2,
3026 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x2,
3032 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x2,
3038 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x2,
3052 FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x2,
3078 FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x2,
3092 FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x2,
3098 FMT_SPATIAL_DITHER_MODE_2 = 0x2,
3112 LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x2,
3186 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET= 0x2,
3196 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x2,
3216 LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x2,
3230 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE= 0x2,
3238 ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE= 0x2,
3259 PIXEL_DEPTH_18BPP = 0x2,
3289 MEMORY_CONFIG_2 = 0x2,
3299 SYNC_DURATION_64 = 0x2,
3305 SCL_C_RAM_TAP_PAIR_ID2 = 0x2,
3312 SCL_C_RAM_PHASE_2 = 0x2,
3323 SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 0x2,
3331 SCL_MODE_YCBCR_SCALING = 0x2,
3340 SCL_V_NUM_OF_TAPS_3 = 0x2,
3364 SCL_BYPASS_MODE_AC_AR = 0x2,
3370 SCL_V_MANUAL_REPLICATE_FACTOR_3 = 0x2,
3388 SCL_H_MANUAL_REPLICATE_FACTOR_3 = 0x2,
3442 SCL_HF_SHARP_SCALE_FACTOR_2 = 0x2,
3456 SCL_VF_SHARP_SCALE_FACTOR_2 = 0x2,
3482 INTERLACE_SOURCE_STACK = 0x2,
3503 INPUTCSC_MODE_B = 0x2,
3509 INPUTCSC_TYPE_8_4 = 0x2,
3518 PRESCALE_MODE_UNITY = 0x2,
3523 INGAMMA_MODE_FLOAT = 0x2,
3528 COL_MAN_OUTPUT_CSC_YCrCb601 = 0x2,
3537 DENORM_CLAMP_MODE_10 = 0x2,
3543 GAMMA_CORR_MODE_B = 0x2,
3556 UNP_GRPH_32BPP = 0x2,
3561 UNP_GRPH_ADDR_SURF_8_BANK = 0x2,
3567 UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 0x2,
3573 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 0x2,
3579 UNP_ADDR_SURF_TILE_SPLIT_256B = 0x2,
3596 UNP_ADDR_SURF_MACRO_ASPECT_4 = 0x2,
3606 UNP_VIDEO_FORMAT_YUV420_YCbCr = 0x2,
3616 UNP_GRPH_ENDIAN_SWAP_8IN32 = 0x2,
3622 UNP_GRPH_RED_CROSSBAR_B_Cb = 0x2,
3628 UNP_UNP_GRPH_GREEN_CROSSBAR_A = 0x2,
3634 UNP_GRPH_BLUE_CROSSBAR_R_Cr = 0x2,
3660 UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 0x2,
3670 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 0x2,
3680 UNP_CRC_SOURCE_SEL_RESERVED = 0x2,
3687 UNP_CRC_LINE_SEL_ODD_ONLY = 0x2,
3693 UNP_ROTATION_ANGLE_180 = 0x2,
3715 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5= 0x2,
3725 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5= 0x2,
3843 AZ_CORB_SIZE_256ENTRIES = 0x2,
3861 AZ_RIRB_SIZE_256ENTRIES = 0x2,
3919 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
3926 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
3936 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20= 0x2,
3944 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
3970 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
3977 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
3987 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
3995 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
4094 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4154 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4246 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4306 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4410 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
4417 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
4427 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
4435 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
4490 BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2,
4496 BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
4510 BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2,
4519 BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2,
4534 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
4540 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x2,
4602 DBG_BLOCK_ID_VMC = 0x2,
4859 DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
4981 DBG_BLOCK_ID_CSC_BY4 = 0x2,
5043 DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
5075 DBG_BLOCK_ID_SXM_BY16 = 0x2,
5092 ENDIAN_8IN32 = 0x2,
5098 ARRAY_1D_TILED_THIN1 = 0x2,
5116 CONFIG_4_PIPE = 0x2,
5130 CONFIG_4KB_ROW = 0x2,
5140 CONFIG_512B_SWAPS = 0x2,
5146 CONFIG_4KB_SPLIT = 0x2,
5152 ADDR_CONFIG_4_PIPE = 0x2,
5162 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
5176 ADDR_CONFIG_4_GPU = 0x2,
5181 ADDR_CONFIG_GPU_TILE_64 = 0x2,
5187 ADDR_CONFIG_4KB_ROW = 0x2,
5196 ABGR_TO_A_BG_G_RB = 0x2,
5202 REF_EQUAL = 0x2,
5216 DEPTH_X8_24 = 0x2,
5226 Z_24 = 0x2,
5236 CMASK_CLEAR_ALL = 0x2,
5254 EXPORT_32_GR = 0x2,
5264 EXPORT_4P_32BPC_GR = 0x2,
5272 COLOR_16 = 0x2,
5298 FMT_16 = 0x2,
5364 BUF_DATA_FORMAT_16 = 0x2,
5382 IMG_DATA_FORMAT_16 = 0x2,
5448 BUF_NUM_FORMAT_USCALED = 0x2,
5458 IMG_NUM_FORMAT_USCALED = 0x2,
5484 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
5491 ADDR_SURF_TILE_SPLIT_256B = 0x2,
5500 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
5506 ADDR_SURF_P2_RESERVED1 = 0x2,
5526 ADDR_SURF_8_BANK = 0x2,
5532 ADDR_SURF_BANK_WIDTH_4 = 0x2,
5538 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
5544 ADDR_SURF_BANK_WH_4 = 0x2,
5550 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
5556 GATCL1_TYPE_BYPASS = 0x2,
5565 MTYPE_CC = 0x2,
5571 PERFMON_COUNTER_MODE_MAX = 0x2,
5584 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
5601 ARRAY_3D = 0x2,
5619 FORCE_DEEP_SLEEP_REQUEST = 0x2,
5633 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
5686 TMDS_DVO_MUX_SELECT_R = 0x2,
5824 GENERICA_STEREOSYNC_SEL_D3 = 0x2,
5833 GENERICB_STEREOSYNC_SEL_D3 = 0x2,
5842 DCO_DBG_BLOCK_SEL_DVO = 0x2,
5899 DCO_DBG_CLOCK_SEL_MVPCLK = 0x2,
5936 DOUT_I2C_CONTROL_SELECT_DDC3 = 0x2,
5945 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x2,
5955 DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x2,
5981 DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE= 0x2,
6019 BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2,
6025 BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
6039 BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2,
6048 BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2,
6063 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
6069 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW= 0x2,
H A Ddce_8_0_sh_mask.h119 #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2
122 #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2
145 #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2
148 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2
155 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
249 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2
252 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2
313 #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
323 #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
421 #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_LIGHT_SLEEP_DIS_MASK 0x2
424 #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT 0x2
643 #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2
647 #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2
657 #define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2
660 #define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
717 #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2
720 #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
741 #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2
1093 #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2
1096 #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2
1201 #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2
1204 #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2
1213 #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
1216 #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
1254 #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
1299 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2
1302 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
1469 #define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2
1472 #define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2
1495 #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2
1498 #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2
1583 #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2
1635 #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2
1638 #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2
1763 #define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK 0x2
1766 #define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT 0x2
1773 #define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK 0x2
1776 #define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT 0x2
1783 #define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK 0x2
1786 #define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT 0x2
1793 #define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK 0x2
1796 #define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT 0x2
1803 #define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK 0x2
1806 #define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT 0x2
1813 #define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK 0x2
1816 #define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT 0x2
1823 #define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2
1826 #define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2
1901 #define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x2
1904 #define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x2
1915 #define DCO_SOFT_RESET__DACB_SOFT_RESET_MASK 0x2
1918 #define DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2
2067 #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2
2070 #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2
2089 #define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2
2092 #define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2
2151 #define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2
2157 #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2
2160 #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2
2278 #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2
2347 #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2
2350 #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2
2502 #define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT 0x2
2534 #define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT 0x2
2583 #define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK 0x2
2586 #define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT 0x2
2637 #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK 0x2
2640 #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x2
2725 #define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_SW_INT_STATUS_MASK 0x2
2773 #define MCIF_BUF_1_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2
2793 #define MCIF_BUF_2_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2
2813 #define MCIF_BUF_3_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2
2833 #define MCIF_BUF_4_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2
2902 #define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT 0x2
2932 #define DCO_MEM_POWER_STATE_2__HDMI6_MEM_PWR_STATE__SHIFT 0x2
2935 #define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK 0x2
2938 #define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT 0x2
3179 #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2
3203 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2
3206 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2
3452 #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2
3537 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2
3540 #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2
3917 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2
3920 #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2
4085 #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2
4135 #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2
4139 #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2
4143 #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2
4169 #define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2
4348 #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2
4383 #define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2
4386 #define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2
4394 #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2
4399 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2
4402 #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2
4422 #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2
4495 #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2
4540 #define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
4611 #define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2
4614 #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
4668 #define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x2
4727 #define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x2
4761 #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2
4764 #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
4783 #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x2
4786 #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x2
5047 #define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2
5097 #define CUR2_UPDATE__CURSOR2_UPDATE_TAKEN_MASK 0x2
5109 #define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2
5117 #define CUR2_STEREO_CONTROL__CURSOR2_STEREO_OFFSET_YNX_MASK 0x2
5145 #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2
5186 #define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
5203 #define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2
5206 #define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
5261 #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2
5429 #define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2
5477 #define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2
5480 #define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x2
5497 #define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
5500 #define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
5553 #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2
5579 #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2
5597 #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2
5610 #define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
5619 #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2
5833 #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2
5879 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2
5882 #define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
5972 #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
6011 #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2
6014 #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
6141 #define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2
6144 #define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
6171 #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK 0x2
6199 #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK 0x2
6227 #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK 0x2
6255 #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK 0x2
6283 #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK 0x2
6311 #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK 0x2
6411 #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2
6414 #define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2
6426 #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2
6443 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2
6446 #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2
6492 #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2
6605 #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2
6629 #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2
6653 #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2
6677 #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2
6701 #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2
6725 #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2
6791 #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2
6794 #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2
6801 #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2
6804 #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2
6825 #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2
6859 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2
6862 #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2
6871 #define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
6874 #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2
6927 #define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
6930 #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2
6983 #define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
6986 #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2
7037 #define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
7040 #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2
7091 #define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
7094 #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2
7145 #define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
7148 #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2
7229 #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
7232 #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
7293 #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
7296 #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
7357 #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
7360 #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
7451 #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2
7689 #define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2
7692 #define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2
7701 #define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2
7704 #define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2
7727 #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2
7730 #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2
7771 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2
7774 #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2
7803 #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x2
7806 #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x2
7865 #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2
7867 #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2
7870 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2
7872 #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2
7963 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2
7966 #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2
7999 #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2
8002 #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2
8045 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2
8048 #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2
8100 #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2
8187 #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
8189 #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
8192 #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
8194 #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
8295 #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
8297 #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
8300 #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
8302 #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
8403 #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
8405 #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
8408 #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
8410 #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
8511 #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
8513 #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
8516 #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
8518 #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
8545 #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
8548 #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
8599 #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
8602 #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
8653 #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
8656 #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
8707 #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
8710 #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
8725 #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
8728 #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
8779 #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
8782 #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
8833 #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
8836 #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
8887 #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
8890 #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
8905 #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK_MASK 0x2
8908 #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
8959 #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK_MASK 0x2
8962 #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
9013 #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK_MASK 0x2
9016 #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
9067 #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_MASK_MASK 0x2
9070 #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
9159 #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2
9162 #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
9165 #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2
9168 #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
9237 #define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2
9240 #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
9398 #define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
9406 #define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
9425 #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2
9428 #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
9449 #define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2
9485 #define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2
9635 #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2
9697 #define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2
9727 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
9730 #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
9876 #define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2
9951 #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2
10009 #define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2
10058 #define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
10361 #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2
10364 #define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2
10437 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2
10440 #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2
10455 #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2
10458 #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2
10591 #define GENMO_WT__VGA_RAM_EN_MASK 0x2
10594 #define GENMO_WT__VGA_CKSEL__SHIFT 0x2
10603 #define GENMO_RD__VGA_RAM_EN_MASK 0x2
10606 #define GENMO_RD__VGA_CKSEL__SHIFT 0x2
10643 #define SEQ00__SEQ_RST1B_MASK 0x2
10648 #define SEQ01__SEQ_SHIFT2__SHIFT 0x2
10657 #define SEQ02__SEQ_MAP1_EN_MASK 0x2
10660 #define SEQ02__SEQ_MAP2_EN__SHIFT 0x2
10665 #define SEQ03__SEQ_FONT_B2_MASK 0x2
10668 #define SEQ03__SEQ_FONT_A1__SHIFT 0x2
10675 #define SEQ04__SEQ_256K_MASK 0x2
10678 #define SEQ04__SEQ_ODDEVEN__SHIFT 0x2
10709 #define CRT07__V_DISP_END_B8_MASK 0x2
10712 #define CRT07__V_SYNC_START_B8__SHIFT 0x2
10779 #define CRT17__RA1_AS_A14B_MASK 0x2
10782 #define CRT17__VCOUNT_BY2__SHIFT 0x2
10793 #define CRT1E__GRPH_DEC_RD1_MASK 0x2
10805 #define GRA00__GRPH_SET_RESET1_MASK 0x2
10808 #define GRA00__GRPH_SET_RESET2__SHIFT 0x2
10813 #define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2
10816 #define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2
10839 #define GRA06__GRPH_ODDEVEN_MASK 0x2
10842 #define GRA06__GRPH_ADRSEL__SHIFT 0x2
10845 #define GRA07__GRPH_XCARE1_MASK 0x2
10848 #define GRA07__GRPH_XCARE2__SHIFT 0x2
10895 #define ATTR10__ATTR_MONO_EN_MASK 0x2
10898 #define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2
10918 #define ATTR14__ATTR_CSEL2__SHIFT 0x2
10939 #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2
10942 #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2
11071 #define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2
11074 #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2
11095 #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2
11098 #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2
11163 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2
11166 #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2
11401 #define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2
11409 #define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2
11415 #define INTERRUPT_CONTROL__OUTPUT_STREAM_1_INTERRUPT_ENABLE_MASK 0x2
11418 #define INTERRUPT_CONTROL__OUTPUT_STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2
11431 #define INTERRUPT_STATUS__OUTPUT_STREAM_1_INTERRUPT_STATUS_MASK 0x2
11434 #define INTERRUPT_STATUS__OUTPUT_STREAM_2_INTERRUPT_STATUS__SHIFT 0x2
11449 #define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2
11452 #define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2
11473 #define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2
11495 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2
11498 #define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2
11502 #define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2
11519 #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2
11533 #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2
11536 #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
11587 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
11590 #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
11639 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
11642 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
11669 #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
11675 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
11678 #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
11701 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
11704 #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
11903 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
11909 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2
11915 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2
11921 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2
11985 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2
11991 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2
11997 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2
12003 #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2
12012 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
12016 #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
12214 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
12217 #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
12258 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
12261 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
12290 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
12293 #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
12306 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
12309 #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
12332 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
12335 #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
12462 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
12486 #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2
12593 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
12597 #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
12680 #define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2
12692 #define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_UPDATE_PENDING_MASK 0x2
12695 #define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
12724 #define SI_EC_CONFIG__DISPCLK_G_SCANIN_GATE_DIS_MASK 0x2
12727 #define SI_EC_CONFIG__DISPCLK_G_SISCL_GATE_DIS__SHIFT 0x2
12751 #define CNV_MODE__CNV_INPUT_PIPE_SELECT__SHIFT 0x2
12848 #define SI_DBG_MODE__SI_DBG_DIN_FMT_MASK 0x2
12851 #define SI_DBG_MODE__SI_DBG_36MODE__SHIFT 0x2
/linux-4.4.14/arch/arm/mach-s3c64xx/include/mach/
H A Dregs-gpio.h44 #define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30)
51 #define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28)
58 #define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26)
65 #define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24)
72 #define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22)
81 #define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18)
88 #define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16)
94 #define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14)
100 #define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12)
106 #define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8)
118 #define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0)
173 #define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12)
178 #define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0)
/linux-4.4.14/arch/mips/mti-sead3/
H A Dsead3-time.c32 orig = readl(status_reg) & 0x2; /* get original sample */ estimate_cpu_frequency()
34 while ((readl(status_reg) & 0x2) == orig) estimate_cpu_frequency()
36 orig = orig ^ 0x2; /* flip the bit */ estimate_cpu_frequency()
43 while ((readl(status_reg) & 0x2) == orig) estimate_cpu_frequency()
45 orig = orig ^ 0x2; /* flip the bit */ estimate_cpu_frequency()
/linux-4.4.14/include/linux/mfd/syscon/
H A Dimx6q-iomuxc-gpr.h32 #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK (0x2 << 30)
37 #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR (0x2 << 28)
41 #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK (0x2 << 26)
51 #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK (0x2 << 22)
56 #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK (0x2 << 20)
61 #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK (0x2 << 18)
66 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (0x2 << 16)
71 #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3 (0x2 << 14)
129 #define IMX6Q_GPR1_ADDRS3_128MB (0x2 << 10)
141 #define IMX6Q_GPR2_COUNTER_RESET_VAL_4 (0x2 << 20)
146 #define IMX6Q_GPR2_LVDS_CLK_SHIFT_2 (0x2 << 16)
186 #define IMX6Q_GPR3_GPU_DBG_OPENVG (0x2 << 29)
203 #define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0 (0x2 << 8)
208 #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6)
214 #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0 (0x2 << 4)
220 #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0 (0x2 << 2)
290 #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2)
295 #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0)
313 #define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB (0x2 << 24)
329 #define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F (0x2 << 16)
338 #define IMX6Q_GPR13_SATA_TX_ATTEN_12_16 (0x2 << 11)
345 #define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB (0x2 << 7)
420 #define IMX6SX_GPR5_CSI2_MUX_CTRL_VDAC_TO_CSI (0x2 << 27)
428 #define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI (0x2 << 4)
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_enum.h30 UVDFC_DECODED_ADDR = 0x2,
43 ENDIAN_8IN32 = 0x2,
49 ARRAY_1D_TILED_THIN1 = 0x2,
67 CONFIG_4_PIPE = 0x2,
81 CONFIG_4KB_ROW = 0x2,
91 CONFIG_512B_SWAPS = 0x2,
97 CONFIG_4KB_SPLIT = 0x2,
103 ADDR_CONFIG_4_PIPE = 0x2,
113 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
127 ADDR_CONFIG_4_GPU = 0x2,
132 ADDR_CONFIG_GPU_TILE_64 = 0x2,
138 ADDR_CONFIG_4KB_ROW = 0x2,
147 DBG_CLIENT_BLKID_scf2 = 0x2,
307 DBG_BLOCK_ID_VMC = 0x2,
541 DBG_BLOCK_ID_CG_BY2 = 0x2,
659 DBG_BLOCK_ID_CSC_BY4 = 0x2,
719 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
750 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
767 ABGR_TO_A_BG_G_RB = 0x2,
773 REF_EQUAL = 0x2,
787 DEPTH_X8_24 = 0x2,
797 Z_24 = 0x2,
807 CMASK_CLEAR_ALL = 0x2,
825 EXPORT_32_GR = 0x2,
835 EXPORT_4P_32BPC_GR = 0x2,
843 COLOR_16 = 0x2,
869 FMT_16 = 0x2,
935 BUF_DATA_FORMAT_16 = 0x2,
953 IMG_DATA_FORMAT_16 = 0x2,
1019 BUF_NUM_FORMAT_USCALED = 0x2,
1029 IMG_NUM_FORMAT_USCALED = 0x2,
1055 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1062 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1071 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1077 ADDR_SURF_P2_RESERVED1 = 0x2,
1097 ADDR_SURF_8_BANK = 0x2,
1103 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1109 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1115 ADDR_SURF_BANK_WH_4 = 0x2,
1121 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1127 GATCL1_TYPE_BYPASS = 0x2,
1136 MTYPE_CC = 0x2,
1142 PERFMON_COUNTER_MODE_MAX = 0x2,
1155 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1172 ARRAY_3D = 0x2,
1190 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1204 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
H A Duvd_6_0_enum.h30 UVDFC_DECODED_ADDR = 0x2,
43 DBG_BLOCK_ID_VMC = 0x2,
300 DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
422 DBG_BLOCK_ID_CSC_BY4 = 0x2,
484 DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
516 DBG_BLOCK_ID_SXM_BY16 = 0x2,
533 ENDIAN_8IN32 = 0x2,
539 ARRAY_1D_TILED_THIN1 = 0x2,
557 CONFIG_4_PIPE = 0x2,
571 CONFIG_4KB_ROW = 0x2,
581 CONFIG_512B_SWAPS = 0x2,
587 CONFIG_4KB_SPLIT = 0x2,
593 ADDR_CONFIG_4_PIPE = 0x2,
603 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
617 ADDR_CONFIG_4_GPU = 0x2,
622 ADDR_CONFIG_GPU_TILE_64 = 0x2,
628 ADDR_CONFIG_4KB_ROW = 0x2,
637 ABGR_TO_A_BG_G_RB = 0x2,
643 REF_EQUAL = 0x2,
657 DEPTH_X8_24 = 0x2,
667 Z_24 = 0x2,
677 CMASK_CLEAR_ALL = 0x2,
695 EXPORT_32_GR = 0x2,
705 EXPORT_4P_32BPC_GR = 0x2,
713 COLOR_16 = 0x2,
739 FMT_16 = 0x2,
805 BUF_DATA_FORMAT_16 = 0x2,
823 IMG_DATA_FORMAT_16 = 0x2,
889 BUF_NUM_FORMAT_USCALED = 0x2,
899 IMG_NUM_FORMAT_USCALED = 0x2,
925 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
932 ADDR_SURF_TILE_SPLIT_256B = 0x2,
941 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
947 ADDR_SURF_P2_RESERVED1 = 0x2,
967 ADDR_SURF_8_BANK = 0x2,
973 ADDR_SURF_BANK_WIDTH_4 = 0x2,
979 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
985 ADDR_SURF_BANK_WH_4 = 0x2,
991 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
997 GATCL1_TYPE_BYPASS = 0x2,
1006 MTYPE_CC = 0x2,
1012 PERFMON_COUNTER_MODE_MAX = 0x2,
1025 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1042 ARRAY_3D = 0x2,
1060 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1074 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
H A Duvd_4_2_sh_mask.h53 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
111 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2
125 #define UVD_CGC_GATE__UDEC_MASK 0x2
128 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2
165 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
168 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
224 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
269 #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2
272 #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
299 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2
302 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
327 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x2
330 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
383 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2
386 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
412 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
442 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
573 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2
576 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
635 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2
638 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
663 #define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2
666 #define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2
676 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2
687 #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2
690 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2
719 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2
722 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2
H A Duvd_5_0_sh_mask.h53 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
123 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2
137 #define UVD_CGC_GATE__UDEC_MASK 0x2
140 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2
181 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
184 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
243 #define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2
246 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
293 #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2
296 #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
331 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2
334 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
359 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x2
362 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
415 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2
418 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
444 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
474 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
605 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2
608 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
697 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2
700 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
725 #define UVD_SUVD_CGC_GATE__SIT_MASK 0x2
728 #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2
755 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2
758 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2
787 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2
790 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2
833 #define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2
836 #define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2
846 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2
857 #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2
860 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2
893 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2
896 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2
930 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
H A Duvd_6_0_sh_mask.h53 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
125 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2
139 #define UVD_CGC_GATE__UDEC_MASK 0x2
142 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2
183 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
186 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
245 #define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2
248 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
295 #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2
298 #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
333 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2
336 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
361 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x2
364 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
417 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2
420 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
446 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
476 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
607 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2
610 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
699 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2
702 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
727 #define UVD_SUVD_CGC_GATE__SIT_MASK 0x2
730 #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2
753 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2
756 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2
781 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2
784 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2
823 #define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2
826 #define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2
836 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2
847 #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2
850 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2
883 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2
886 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2
918 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
/linux-4.4.14/arch/powerpc/include/asm/
H A Dehv_pic.h22 #define EHV_PIC_VECPRI_SENSE_LEVEL 0x2
24 #define EHV_PIC_VECPRI_SENSE_MASK 0x2
H A Dimmap_qe.h64 u8 res1[0x2];
73 u8 res3[0x2];
76 u8 res5[0x2];
78 u8 res6[0x2];
80 u8 res7[0x2];
82 u8 res8[0x2];
84 u8 res9[0x2];
86 u8 res10[0x2];
88 u8 res11[0x2];
146 u8 res1[0x2];
149 u8 res3[0x2];
154 u8 res6[0x2];
247 u8 res0[0x2];
251 u8 res1[0x2];
266 u8 res0[0x2];
268 u8 res1[0x2];
275 u8 res3[0x2];
281 u8 res4[0x2];
283 u8 res5[0x2];
285 u8 res6[0x2];
287 u8 res7[0x2];
435 struct spi spi[0x2]; /* spi */
457 struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF
/linux-4.4.14/arch/arm/mach-mv78xx0/
H A Dmpp.h28 #define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1)
33 #define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1)
38 #define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1)
43 #define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1)
48 #define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1)
53 #define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1)
58 #define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1)
63 #define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1)
68 #define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1)
73 #define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1)
78 #define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1)
83 #define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1)
244 #define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1)
251 #define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1)
261 #define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1)
271 #define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1)
327 #define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1)
334 #define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1)
/linux-4.4.14/arch/arm/mach-orion5x/
H A Dmpp.h22 #define MPP0_PCI_ARB MPP(0, 0x2, 0, 0, 1, 1, 1)
26 #define MPP1_PCI_ARB MPP(1, 0x2, 0, 0, 1, 1, 1)
30 #define MPP2_PCI_ARB MPP(2, 0x2, 0, 0, 1, 1, 1)
35 #define MPP3_PCI_ARB MPP(3, 0x2, 0, 0, 1, 1, 1)
39 #define MPP4_PCI_ARB MPP(4, 0x2, 0, 0, 1, 1, 1)
45 #define MPP5_PCI_ARB MPP(5, 0x2, 0, 0, 1, 1, 1)
51 #define MPP6_PCI_ARB MPP(6, 0x2, 0, 0, 1, 1, 1)
58 #define MPP7_PCI_ARB MPP(7, 0x2, 0, 0, 1, 1, 1)
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_1_enum.h30 ENDIAN_8IN32 = 0x2,
36 ARRAY_1D_TILED_THIN1 = 0x2,
54 CONFIG_4_PIPE = 0x2,
68 CONFIG_4KB_ROW = 0x2,
78 CONFIG_512B_SWAPS = 0x2,
84 CONFIG_4KB_SPLIT = 0x2,
90 ADDR_CONFIG_4_PIPE = 0x2,
100 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
114 ADDR_CONFIG_4_GPU = 0x2,
119 ADDR_CONFIG_GPU_TILE_64 = 0x2,
125 ADDR_CONFIG_4KB_ROW = 0x2,
134 DBG_CLIENT_BLKID_scf2 = 0x2,
294 DBG_BLOCK_ID_VMC = 0x2,
528 DBG_BLOCK_ID_CG_BY2 = 0x2,
646 DBG_BLOCK_ID_CSC_BY4 = 0x2,
706 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
737 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
754 ABGR_TO_A_BG_G_RB = 0x2,
760 REF_EQUAL = 0x2,
774 DEPTH_X8_24 = 0x2,
784 Z_24 = 0x2,
794 CMASK_CLEAR_ALL = 0x2,
812 EXPORT_32_GR = 0x2,
822 EXPORT_4P_32BPC_GR = 0x2,
830 COLOR_16 = 0x2,
856 FMT_16 = 0x2,
922 BUF_DATA_FORMAT_16 = 0x2,
940 IMG_DATA_FORMAT_16 = 0x2,
1006 BUF_NUM_FORMAT_USCALED = 0x2,
1016 IMG_NUM_FORMAT_USCALED = 0x2,
1042 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1049 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1058 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1064 ADDR_SURF_P2_RESERVED1 = 0x2,
1084 ADDR_SURF_8_BANK = 0x2,
1090 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1096 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1102 ADDR_SURF_BANK_WH_4 = 0x2,
1108 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1114 GATCL1_TYPE_BYPASS = 0x2,
1123 MTYPE_CC = 0x2,
1129 PERFMON_COUNTER_MODE_MAX = 0x2,
1142 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1159 ARRAY_3D = 0x2,
1177 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1191 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
H A Dgmc_8_2_enum.h30 DBG_BLOCK_ID_VMC = 0x2,
287 DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
409 DBG_BLOCK_ID_CSC_BY4 = 0x2,
471 DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
503 DBG_BLOCK_ID_SXM_BY16 = 0x2,
520 ENDIAN_8IN32 = 0x2,
526 ARRAY_1D_TILED_THIN1 = 0x2,
544 CONFIG_4_PIPE = 0x2,
558 CONFIG_4KB_ROW = 0x2,
568 CONFIG_512B_SWAPS = 0x2,
574 CONFIG_4KB_SPLIT = 0x2,
580 ADDR_CONFIG_4_PIPE = 0x2,
590 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
604 ADDR_CONFIG_4_GPU = 0x2,
609 ADDR_CONFIG_GPU_TILE_64 = 0x2,
615 ADDR_CONFIG_4KB_ROW = 0x2,
624 ABGR_TO_A_BG_G_RB = 0x2,
630 REF_EQUAL = 0x2,
644 DEPTH_X8_24 = 0x2,
654 Z_24 = 0x2,
664 CMASK_CLEAR_ALL = 0x2,
682 EXPORT_32_GR = 0x2,
692 EXPORT_4P_32BPC_GR = 0x2,
700 COLOR_16 = 0x2,
726 FMT_16 = 0x2,
792 BUF_DATA_FORMAT_16 = 0x2,
810 IMG_DATA_FORMAT_16 = 0x2,
876 BUF_NUM_FORMAT_USCALED = 0x2,
886 IMG_NUM_FORMAT_USCALED = 0x2,
912 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
919 ADDR_SURF_TILE_SPLIT_256B = 0x2,
928 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
934 ADDR_SURF_P2_RESERVED1 = 0x2,
954 ADDR_SURF_8_BANK = 0x2,
960 ADDR_SURF_BANK_WIDTH_4 = 0x2,
966 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
972 ADDR_SURF_BANK_WH_4 = 0x2,
978 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
984 GATCL1_TYPE_BYPASS = 0x2,
993 MTYPE_CC = 0x2,
999 PERFMON_COUNTER_MODE_MAX = 0x2,
1012 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1029 ARRAY_3D = 0x2,
1047 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1061 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_enum.h30 ENDIAN_8IN32 = 0x2,
36 ARRAY_1D_TILED_THIN1 = 0x2,
54 CONFIG_4_PIPE = 0x2,
68 CONFIG_4KB_ROW = 0x2,
78 CONFIG_512B_SWAPS = 0x2,
84 CONFIG_4KB_SPLIT = 0x2,
90 ADDR_CONFIG_4_PIPE = 0x2,
100 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
114 ADDR_CONFIG_4_GPU = 0x2,
119 ADDR_CONFIG_GPU_TILE_64 = 0x2,
125 ADDR_CONFIG_4KB_ROW = 0x2,
134 DBG_CLIENT_BLKID_scf2 = 0x2,
294 DBG_BLOCK_ID_VMC = 0x2,
528 DBG_BLOCK_ID_CG_BY2 = 0x2,
646 DBG_BLOCK_ID_CSC_BY4 = 0x2,
706 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
737 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
754 ABGR_TO_A_BG_G_RB = 0x2,
760 REF_EQUAL = 0x2,
774 DEPTH_X8_24 = 0x2,
784 Z_24 = 0x2,
794 CMASK_CLEAR_ALL = 0x2,
812 EXPORT_32_GR = 0x2,
822 EXPORT_4P_32BPC_GR = 0x2,
830 COLOR_16 = 0x2,
856 FMT_16 = 0x2,
922 BUF_DATA_FORMAT_16 = 0x2,
940 IMG_DATA_FORMAT_16 = 0x2,
1006 BUF_NUM_FORMAT_USCALED = 0x2,
1016 IMG_NUM_FORMAT_USCALED = 0x2,
1042 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1049 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1058 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1064 ADDR_SURF_P2_RESERVED1 = 0x2,
1084 ADDR_SURF_8_BANK = 0x2,
1090 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1096 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1102 ADDR_SURF_BANK_WH_4 = 0x2,
1108 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1114 GATCL1_TYPE_BYPASS = 0x2,
1123 MTYPE_CC = 0x2,
1129 PERFMON_COUNTER_MODE_MAX = 0x2,
1142 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1159 ARRAY_3D = 0x2,
1177 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1191 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
H A Dbif_5_1_enum.h30 DBG_BLOCK_ID_VMC = 0x2,
287 DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
409 DBG_BLOCK_ID_CSC_BY4 = 0x2,
471 DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
503 DBG_BLOCK_ID_SXM_BY16 = 0x2,
520 ENDIAN_8IN32 = 0x2,
526 ARRAY_1D_TILED_THIN1 = 0x2,
544 CONFIG_4_PIPE = 0x2,
558 CONFIG_4KB_ROW = 0x2,
568 CONFIG_512B_SWAPS = 0x2,
574 CONFIG_4KB_SPLIT = 0x2,
580 ADDR_CONFIG_4_PIPE = 0x2,
590 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
604 ADDR_CONFIG_4_GPU = 0x2,
609 ADDR_CONFIG_GPU_TILE_64 = 0x2,
615 ADDR_CONFIG_4KB_ROW = 0x2,
624 ABGR_TO_A_BG_G_RB = 0x2,
630 REF_EQUAL = 0x2,
644 DEPTH_X8_24 = 0x2,
654 Z_24 = 0x2,
664 CMASK_CLEAR_ALL = 0x2,
682 EXPORT_32_GR = 0x2,
692 EXPORT_4P_32BPC_GR = 0x2,
700 COLOR_16 = 0x2,
726 FMT_16 = 0x2,
792 BUF_DATA_FORMAT_16 = 0x2,
810 IMG_DATA_FORMAT_16 = 0x2,
876 BUF_NUM_FORMAT_USCALED = 0x2,
886 IMG_NUM_FORMAT_USCALED = 0x2,
912 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
919 ADDR_SURF_TILE_SPLIT_256B = 0x2,
928 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
934 ADDR_SURF_P2_RESERVED1 = 0x2,
954 ADDR_SURF_8_BANK = 0x2,
960 ADDR_SURF_BANK_WIDTH_4 = 0x2,
966 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
972 ADDR_SURF_BANK_WH_4 = 0x2,
978 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
984 GATCL1_TYPE_BYPASS = 0x2,
993 MTYPE_CC = 0x2,
999 PERFMON_COUNTER_MODE_MAX = 0x2,
1012 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1029 ARRAY_3D = 0x2,
1047 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1061 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
H A Dbif_5_0_sh_mask.h35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
41 #define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
44 #define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
69 #define CONFIG_CNTL__VGA_DIS_MASK 0x2
72 #define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
103 #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x2
111 #define BX_RESET_EN__REG_RESET_EN_MASK 0x2
114 #define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
131 #define HW_DEBUG__HW_01_DEBUG_MASK 0x2
134 #define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
213 #define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2
231 #define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2
234 #define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2
265 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2
268 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
301 #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2
304 #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
349 #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2
352 #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
373 #define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS_MASK 0x2
377 #define BIF_FB_EN__FB_WRITE_EN_MASK 0x2
409 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2
412 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2
425 #define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2
428 #define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
449 #define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2
452 #define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
473 #define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2
476 #define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2
549 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2
552 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2
583 #define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2
593 #define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2
596 #define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
602 #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
608 #define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
610 #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
616 #define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
618 #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
624 #define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
626 #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
632 #define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
634 #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
640 #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
642 #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
648 #define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
650 #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
656 #define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
658 #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
664 #define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
666 #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
672 #define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
674 #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
680 #define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
683 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x2
686 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
694 #define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT 0x2
696 #define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT 0x2
698 #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
702 #define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
704 #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
708 #define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
713 #define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2
716 #define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2
755 #define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2
758 #define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2
761 #define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2
764 #define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2
767 #define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2
770 #define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2
773 #define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2
776 #define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2
779 #define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2
782 #define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2
785 #define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2
788 #define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2
791 #define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2
794 #define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2
797 #define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2
800 #define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2
802 #define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2
804 #define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2
806 #define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2
808 #define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2
810 #define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2
812 #define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2
814 #define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2
816 #define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2
821 #define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2
824 #define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2
849 #define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2
852 #define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2
876 #define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
878 #define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
926 #define BIF_RB_RPTR__OFFSET__SHIFT 0x2
930 #define BIF_RB_WPTR__OFFSET__SHIFT 0x2
934 #define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
955 #define MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x2
963 #define MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x2
1037 #define COMMAND__MEM_ACCESS_EN_MASK 0x2
1040 #define COMMAND__BUS_MASTER_EN__SHIFT 0x2
1209 #define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
1212 #define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
1233 #define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2
1236 #define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
1373 #define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2
1376 #define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
1398 #define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
1493 #define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
1517 #define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
1819 #define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
1822 #define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
1995 #define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
1998 #define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
2011 #define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2
2014 #define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
2047 #define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2
2051 #define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2
2067 #define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2
2070 #define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
2075 #define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2
2078 #define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
2087 #define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2
2090 #define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
2157 #define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x2
2163 #define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x2
2175 #define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x2
2181 #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x2
2184 #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
2381 #define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2
2384 #define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2
2405 #define PCIE_EFUSE__PCIE_EFUSE_VALID_MASK 0x2
2408 #define PCIE_EFUSE__PPHY_EFUSE_VALID__SHIFT 0x2
2461 #define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2
2463 #define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY_MASK 0x2
2466 #define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2
2493 #define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
2496 #define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
2585 #define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2
2588 #define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
2601 #define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2
2604 #define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
2655 #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
2658 #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
2682 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
2696 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2
2722 #define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
2799 #define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
2802 #define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
2811 #define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
2814 #define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
2845 #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
2848 #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
2853 #define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
2856 #define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
2893 #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2
2896 #define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2
2935 #define PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS_MASK 0x2
2938 #define PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS__SHIFT 0x2
2953 #define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
2956 #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
3071 #define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
3074 #define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
3123 #define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2
3126 #define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2
3165 #define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2
3168 #define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2
3245 #define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
3248 #define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
3363 #define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2
3371 #define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2
3374 #define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
3413 #define SWRST_COMMAND_1__RESETPCFG_MASK 0x2
3416 #define SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2
3469 #define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2
3472 #define SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2
3525 #define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2
3528 #define SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2
3581 #define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2
3584 #define SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2
3625 #define SWRST_EP_COMMAND_0__EP_SOFT_RESET_MASK 0x2
3628 #define SWRST_EP_COMMAND_0__EP_DRV_RESET__SHIFT 0x2
3643 #define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN_MASK 0x2
3646 #define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN__SHIFT 0x2
3665 #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2
3668 #define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
3711 #define GSKT_CONTROL__GSKT_TxFifoDelay_MASK 0x2
3714 #define GSKT_CONTROL__GSKT_TxFifoDelay2__SHIFT 0x2
3827 #define LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2
3830 #define LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2
3873 #define LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2
3876 #define LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2
4027 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK 0x2
4030 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT 0x2
4045 #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK 0x2
4048 #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT 0x2
4075 #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK 0x2
4078 #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT 0x2
4105 #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK 0x2
4108 #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT 0x2
4135 #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK 0x2
4138 #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT 0x2
4169 #define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2
4172 #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2
4181 #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2
4184 #define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT 0x2
4193 #define PB0_HW_DEBUG__HW_01_DEBUG_MASK 0x2
4196 #define PB0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
4255 #define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2
4258 #define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2
4325 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2
4328 #define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2
4357 #define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2
4360 #define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2
4376 #define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT 0x2
4431 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2
4434 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2
4470 #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2
4523 #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
4531 #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
4539 #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
4547 #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
4556 #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2
4669 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2
4672 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2
4790 #define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2
4797 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK 0x2
4800 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT 0x2
4845 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2
4848 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2
4893 #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2
5305 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2
5308 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2
5367 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK 0x2
5370 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT 0x2
5391 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2
5394 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2
5455 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2
5458 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2
5519 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2
5522 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2
5583 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2
5586 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2
5675 #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2
5678 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2
5731 #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2
5734 #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2
5739 #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2
5742 #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2
5765 #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2
5768 #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2
5773 #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2
5776 #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2
5799 #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2
5802 #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2
5807 #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2
5810 #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2
5833 #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2
5836 #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2
5841 #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2
5844 #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2
5867 #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2
5870 #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2
5875 #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2
5878 #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2
5901 #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2
5904 #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2
5909 #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2
5912 #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2
5935 #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2
5938 #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2
5943 #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2
5946 #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2
5969 #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2
5972 #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2
5977 #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2
5980 #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2
6003 #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2
6006 #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2
6011 #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2
6014 #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2
6037 #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2
6040 #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2
6045 #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2
6048 #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2
6071 #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2
6074 #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2
6079 #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2
6082 #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2
6105 #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2
6108 #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2
6113 #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2
6116 #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2
6139 #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2
6142 #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2
6147 #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2
6150 #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2
6173 #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2
6176 #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2
6181 #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2
6184 #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2
6207 #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2
6210 #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2
6215 #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2
6218 #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2
6241 #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2
6244 #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2
6249 #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2
6252 #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2
6371 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK 0x2
6374 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT 0x2
6389 #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK 0x2
6392 #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT 0x2
6419 #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK 0x2
6422 #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT 0x2
6449 #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK 0x2
6452 #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT 0x2
6479 #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK 0x2
6482 #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT 0x2
6513 #define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2
6516 #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2
6525 #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2
6528 #define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT 0x2
6537 #define PB1_HW_DEBUG__HW_01_DEBUG_MASK 0x2
6540 #define PB1_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
6599 #define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2
6602 #define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2
6669 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2
6672 #define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2
6701 #define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2
6704 #define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2
6720 #define PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT 0x2
6775 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2
6778 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2
6814 #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2
6867 #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
6875 #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
6883 #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
6891 #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
6900 #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2
7013 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2
7016 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2
7134 #define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2
7141 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK 0x2
7144 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT 0x2
7189 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2
7192 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2
7237 #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2
7649 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2
7652 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2
7711 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK 0x2
7714 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT 0x2
7735 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2
7738 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2
7799 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2
7802 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2
7863 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2
7866 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2
7927 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2
7930 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2
8019 #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2
8022 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2
8075 #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2
8078 #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2
8083 #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2
8086 #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2
8109 #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2
8112 #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2
8117 #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2
8120 #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2
8143 #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2
8146 #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2
8151 #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2
8154 #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2
8177 #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2
8180 #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2
8185 #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2
8188 #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2
8211 #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2
8214 #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2
8219 #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2
8222 #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2
8245 #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2
8248 #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2
8253 #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2
8256 #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2
8279 #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2
8282 #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2
8287 #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2
8290 #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2
8313 #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2
8316 #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2
8321 #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2
8324 #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2
8347 #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2
8350 #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2
8355 #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2
8358 #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2
8381 #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2
8384 #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2
8389 #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2
8392 #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2
8415 #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2
8418 #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2
8423 #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2
8426 #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2
8449 #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2
8452 #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2
8457 #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2
8460 #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2
8483 #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2
8486 #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2
8491 #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2
8494 #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2
8517 #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2
8520 #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2
8525 #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2
8528 #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2
8551 #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2
8554 #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2
8559 #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2
8562 #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2
8585 #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2
8588 #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2
8593 #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2
8596 #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2
8621 #define PB0_PIF_HW_DEBUG__HW_01_DEBUG_MASK 0x2
8624 #define PB0_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
8651 #define PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
8654 #define PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
8681 #define PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
8684 #define PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
8805 #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
8808 #define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
8823 #define PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
8826 #define PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
8853 #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
8856 #define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
8918 #define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
8931 #define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
8934 #define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
8961 #define PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
8964 #define PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
9029 #define PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
9032 #define PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
9097 #define PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
9100 #define PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
9165 #define PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
9168 #define PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
9233 #define PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
9236 #define PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
9301 #define PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
9304 #define PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
9369 #define PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
9372 #define PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
9437 #define PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
9440 #define PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
9507 #define PB1_PIF_HW_DEBUG__HW_01_DEBUG_MASK 0x2
9510 #define PB1_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
9537 #define PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
9540 #define PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
9567 #define PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
9570 #define PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
9691 #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
9694 #define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
9709 #define PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
9712 #define PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
9739 #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
9742 #define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
9804 #define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
9817 #define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
9820 #define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
9847 #define PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
9850 #define PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
9915 #define PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
9918 #define PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
9983 #define PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
9986 #define PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
10051 #define PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
10054 #define PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
10119 #define PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
10122 #define PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
10187 #define PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
10190 #define PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
10255 #define PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
10258 #define PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
10323 #define PB1_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
10326 #define PB1_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
10395 #define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
10398 #define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
10427 #define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
10430 #define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
10521 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
10524 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
10573 #define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
10576 #define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
10605 #define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
10608 #define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
10663 #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
10666 #define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
10686 #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
10710 #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
10730 #define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x2
10731 #define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
10734 #define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
10868 #define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
10922 #define PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
10927 #define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
10930 #define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
11057 #define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
11060 #define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
11206 #define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
11227 #define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
11230 #define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
11247 #define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
11250 #define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
11268 #define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
11276 #define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
11284 #define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
11292 #define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
11303 #define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2
11307 #define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2
11319 #define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst_MASK 0x2
11323 #define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst_MASK 0x2
11326 #define BIF_RFE_MASTER_SOFTRST_TRIGGER__SMBUS_rst__SHIFT 0x2
11331 #define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd_MASK 0x2
11334 #define BIF_PWDN_COMMAND__REG_SMBUS_pw_cmd__SHIFT 0x2
11339 #define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status_MASK 0x2
11342 #define BIF_PWDN_STATUS__SMBUS_REG_pw_status__SHIFT 0x2
11405 #define BIF_IMPCTL_SMPLCNTL__RxPDNB_MASK 0x2
11408 #define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd__SHIFT 0x2
H A Dbif_4_1_sh_mask.h37 #define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
40 #define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
65 #define CONFIG_CNTL__VGA_DIS_MASK 0x2
68 #define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
85 #define BX_RESET_EN__REG_RESET_EN_MASK 0x2
88 #define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
95 #define HW_DEBUG__HW_01_DEBUG_MASK 0x2
98 #define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
177 #define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2
193 #define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2
196 #define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2
227 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2
230 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
263 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x2
266 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x2
287 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x2
290 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x2
317 #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2
320 #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
341 #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2
344 #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
351 #define BIF_FB_EN__FB_WRITE_EN_MASK 0x2
383 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2
386 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2
399 #define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2
402 #define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
423 #define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2
426 #define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
447 #define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2
450 #define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2
523 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2
526 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2
555 #define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2
565 #define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2
568 #define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
571 #define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS_MASK 0x2
574 #define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS__SHIFT 0x2
576 #define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER__SHIFT 0x2
582 #define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER__SHIFT 0x2
584 #define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER__SHIFT 0x2
590 #define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER__SHIFT 0x2
592 #define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER__SHIFT 0x2
598 #define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER__SHIFT 0x2
600 #define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER__SHIFT 0x2
606 #define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER__SHIFT 0x2
608 #define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER__SHIFT 0x2
614 #define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER__SHIFT 0x2
616 #define BIF_SSA_MC_LOWER__SSA_MC_LOWER__SHIFT 0x2
624 #define BIF_SSA_MC_UPPER__SSA_MC_UPPER__SHIFT 0x2
629 #define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2
632 #define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2
665 #define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2
668 #define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2
671 #define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2
674 #define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2
677 #define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2
680 #define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2
683 #define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2
686 #define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2
689 #define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2
692 #define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2
695 #define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2
698 #define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2
701 #define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2
704 #define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2
707 #define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2
710 #define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2
712 #define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2
714 #define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2
716 #define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2
718 #define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2
720 #define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2
722 #define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2
724 #define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2
726 #define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2
731 #define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2
734 #define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2
755 #define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2
758 #define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2
778 #define GARLIC_COHE_CP_RB0_WPTR__ADDRESS__SHIFT 0x2
780 #define GARLIC_COHE_CP_RB1_WPTR__ADDRESS__SHIFT 0x2
782 #define GARLIC_COHE_CP_RB2_WPTR__ADDRESS__SHIFT 0x2
784 #define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS__SHIFT 0x2
786 #define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
788 #define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
790 #define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS__SHIFT 0x2
792 #define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS__SHIFT 0x2
794 #define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS__SHIFT 0x2
796 #define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS__SHIFT 0x2
798 #define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS__SHIFT 0x2
800 #define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS__SHIFT 0x2
802 #define GARLIC_COHE_VCE_RB_WPTR__ADDRESS__SHIFT 0x2
841 #define COMMAND__MEM_ACCESS_EN_MASK 0x2
844 #define COMMAND__BUS_MASTER_EN__SHIFT 0x2
1013 #define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
1016 #define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
1037 #define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2
1040 #define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
1165 #define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2
1168 #define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
1188 #define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
1257 #define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
1281 #define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
1583 #define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
1586 #define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
1759 #define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
1762 #define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
1775 #define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2
1778 #define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
1811 #define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2
1815 #define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2
1831 #define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2
1834 #define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
1839 #define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2
1842 #define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
1851 #define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2
1854 #define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
1927 #define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
1930 #define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
2019 #define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2
2022 #define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
2035 #define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2
2038 #define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
2077 #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
2080 #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
2096 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
2110 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2
2136 #define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
2211 #define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
2214 #define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
2223 #define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
2226 #define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
2257 #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
2260 #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
2263 #define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
2266 #define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
2303 #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2
2306 #define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2
2341 #define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
2344 #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
2459 #define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
2462 #define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
2495 #define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2
2498 #define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2
2529 #define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2
2532 #define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2
2597 #define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
2600 #define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
2715 #define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
2718 #define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
2747 #define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
2750 #define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
2841 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
2844 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
2893 #define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
2896 #define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
2925 #define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
2928 #define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
2979 #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
2982 #define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
2999 #define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
3002 #define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
3183 #define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
3186 #define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
3297 #define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
3300 #define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
3444 #define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
3465 #define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
3468 #define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
3577 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x2
3580 #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x2
3595 #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x2
3598 #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x2
3625 #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x2
3628 #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x2
3655 #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x2
3658 #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x2
3685 #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x2
3688 #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x2
3719 #define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2
3722 #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2
3731 #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2
3735 #define PB0_HW_DEBUG__PB0_HW_01_DEBUG_MASK 0x2
3738 #define PB0_HW_DEBUG__PB0_HW_02_DEBUG__SHIFT 0x2
3797 #define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2
3800 #define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2
3865 #define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2
3868 #define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2
3897 #define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2
3900 #define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2
3941 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2
3944 #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2
3988 #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2
4041 #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
4049 #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
4057 #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
4065 #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
4074 #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2
4125 #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
4133 #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
4141 #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
4149 #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
4205 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2
4208 #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2
4308 #define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2
4311 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x2
4314 #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x2
4359 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2
4362 #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2
4411 #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2
4759 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2
4762 #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2
4821 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x2
4824 #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x2
4853 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2
4856 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2
4917 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2
4920 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2
4981 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2
4984 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2
5045 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2
5048 #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2
5137 #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2
5140 #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2
5193 #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2
5196 #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2
5201 #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2
5204 #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2
5229 #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2
5232 #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2
5237 #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2
5240 #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2
5265 #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2
5268 #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2
5273 #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2
5276 #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2
5301 #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2
5304 #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2
5309 #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2
5312 #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2
5337 #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2
5340 #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2
5345 #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2
5348 #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2
5373 #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2
5376 #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2
5381 #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2
5384 #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2
5409 #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2
5412 #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2
5417 #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2
5420 #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2
5445 #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2
5448 #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2
5453 #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2
5456 #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2
5481 #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2
5484 #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2
5489 #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2
5492 #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2
5517 #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2
5520 #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2
5525 #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2
5528 #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2
5553 #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2
5556 #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2
5561 #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2
5564 #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2
5589 #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2
5592 #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2
5597 #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2
5600 #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2
5625 #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2
5628 #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2
5633 #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2
5636 #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2
5661 #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2
5664 #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2
5669 #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2
5672 #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2
5697 #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2
5700 #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2
5705 #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2
5708 #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2
5733 #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2
5736 #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2
5741 #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2
5744 #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2
5865 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x2
5868 #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x2
5883 #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x2
5886 #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x2
5913 #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x2
5916 #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x2
5943 #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x2
5946 #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x2
5973 #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x2
5976 #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x2
6007 #define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2
6010 #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2
6019 #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2
6023 #define PB1_HW_DEBUG__PB1_HW_01_DEBUG_MASK 0x2
6026 #define PB1_HW_DEBUG__PB1_HW_02_DEBUG__SHIFT 0x2
6085 #define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2
6088 #define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2
6153 #define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2
6156 #define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2
6185 #define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2
6188 #define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2
6229 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2
6232 #define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2
6276 #define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2
6329 #define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
6337 #define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
6345 #define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
6353 #define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
6362 #define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2
6413 #define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
6421 #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
6429 #define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
6437 #define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
6493 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2
6496 #define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2
6596 #define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2
6599 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x2
6602 #define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x2
6647 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2
6650 #define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2
6699 #define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2
7047 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2
7050 #define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2
7109 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x2
7112 #define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x2
7141 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2
7144 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2
7205 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2
7208 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2
7269 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2
7272 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2
7333 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2
7336 #define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2
7425 #define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2
7428 #define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2
7481 #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2
7484 #define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2
7489 #define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2
7492 #define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2
7517 #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2
7520 #define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2
7525 #define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2
7528 #define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2
7553 #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2
7556 #define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2
7561 #define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2
7564 #define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2
7589 #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2
7592 #define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2
7597 #define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2
7600 #define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2
7625 #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2
7628 #define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2
7633 #define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2
7636 #define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2
7661 #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2
7664 #define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2
7669 #define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2
7672 #define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2
7697 #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2
7700 #define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2
7705 #define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2
7708 #define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2
7733 #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2
7736 #define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2
7741 #define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2
7744 #define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2
7769 #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2
7772 #define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2
7777 #define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2
7780 #define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2
7805 #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2
7808 #define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2
7813 #define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2
7816 #define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2
7841 #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2
7844 #define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2
7849 #define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2
7852 #define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2
7877 #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2
7880 #define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2
7885 #define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2
7888 #define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2
7913 #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2
7916 #define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2
7921 #define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2
7924 #define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2
7949 #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2
7952 #define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2
7957 #define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2
7960 #define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2
7985 #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2
7988 #define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2
7993 #define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2
7996 #define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2
8021 #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2
8024 #define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2
8029 #define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2
8032 #define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2
8059 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG_MASK 0x2
8062 #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG__SHIFT 0x2
8095 #define PB0_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x2
8098 #define PB0_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x2
8143 #define PB0_PIF_PAIRING__X2_LANE_3_2_MASK 0x2
8146 #define PB0_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x2
8269 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x2
8272 #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x2
8301 #define PB0_PIF_SC_CTL__SC_RXDETECT_MASK 0x2
8304 #define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x2
8399 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1_MASK 0x2
8402 #define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2__SHIFT 0x2
8603 #define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x2
8606 #define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x2
8619 #define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x2
8622 #define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x2
8635 #define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x2
8638 #define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x2
8651 #define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x2
8654 #define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x2
8667 #define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x2
8670 #define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x2
8683 #define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x2
8686 #define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x2
8699 #define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x2
8702 #define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x2
8715 #define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x2
8718 #define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x2
8891 #define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x2
8894 #define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x2
8907 #define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x2
8910 #define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x2
8923 #define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x2
8926 #define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x2
8939 #define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x2
8942 #define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x2
8955 #define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x2
8958 #define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x2
8971 #define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x2
8974 #define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x2
8987 #define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x2
8990 #define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x2
9003 #define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x2
9006 #define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x2
9021 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG_MASK 0x2
9024 #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG__SHIFT 0x2
9057 #define PB1_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x2
9060 #define PB1_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x2
9105 #define PB1_PIF_PAIRING__X2_LANE_3_2_MASK 0x2
9108 #define PB1_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x2
9231 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x2
9234 #define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x2
9263 #define PB1_PIF_SC_CTL__SC_RXDETECT_MASK 0x2
9266 #define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x2
9361 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1_MASK 0x2
9364 #define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2__SHIFT 0x2
9565 #define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x2
9568 #define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x2
9581 #define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x2
9584 #define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x2
9597 #define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x2
9600 #define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x2
9613 #define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x2
9616 #define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x2
9629 #define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x2
9632 #define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x2
9645 #define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x2
9648 #define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x2
9661 #define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x2
9664 #define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x2
9677 #define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x2
9680 #define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x2
9853 #define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x2
9856 #define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x2
9869 #define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x2
9872 #define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x2
9885 #define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x2
9888 #define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x2
9901 #define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x2
9904 #define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x2
9917 #define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x2
9920 #define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x2
9933 #define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x2
9936 #define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x2
9949 #define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x2
9952 #define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x2
9965 #define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x2
9968 #define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x2
9981 #define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2
9985 #define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2
9997 #define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst_MASK 0x2
10001 #define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst_MASK 0x2
10004 #define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x2
10007 #define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd_MASK 0x2
10010 #define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x2
10013 #define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status_MASK 0x2
10016 #define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x2
10067 #define BIF_IMPCTL_SMPLCNTL__RxPDNB_MASK 0x2
10070 #define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd__SHIFT 0x2
10175 #define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x2
10178 #define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x2
10231 #define BIF_RESET_CNTL__RST_DONE_MASK 0x2
10234 #define BIF_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x2
10243 #define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode_MASK 0x2
10246 #define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2
H A Dbif_5_1_sh_mask.h35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
39 #define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
42 #define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
67 #define CONFIG_CNTL__VGA_DIS_MASK 0x2
70 #define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
87 #define BX_RESET_EN__REG_RESET_EN_MASK 0x2
90 #define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
97 #define HW_DEBUG__HW_01_DEBUG_MASK 0x2
100 #define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
179 #define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2
197 #define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2
200 #define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2
231 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2
234 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
255 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x2
258 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x2
279 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x2
282 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x2
309 #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2
312 #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
335 #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2
338 #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
351 #define BIF_FB_EN__FB_WRITE_EN_MASK 0x2
383 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2
386 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2
399 #define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2
402 #define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
423 #define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2
426 #define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
447 #define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2
450 #define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2
523 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2
526 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2
555 #define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2
565 #define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2
568 #define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
572 #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
578 #define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
580 #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
586 #define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
588 #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
594 #define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
596 #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
602 #define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
604 #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
610 #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
612 #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
618 #define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
620 #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
626 #define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
628 #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
634 #define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
636 #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
642 #define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
644 #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
650 #define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
653 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x2
656 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
664 #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
668 #define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
670 #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
674 #define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
676 #define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT 0x2
678 #define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT 0x2
683 #define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2
686 #define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2
725 #define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2
728 #define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2
731 #define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2
734 #define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2
737 #define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2
740 #define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2
743 #define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2
746 #define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2
749 #define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2
752 #define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2
755 #define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2
758 #define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2
761 #define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2
764 #define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2
767 #define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2
770 #define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2
772 #define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2
774 #define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2
776 #define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2
778 #define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2
780 #define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2
782 #define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2
784 #define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2
786 #define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2
791 #define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2
794 #define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2
819 #define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2
822 #define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2
846 #define GARLIC_COHE_CP_RB0_WPTR__ADDRESS__SHIFT 0x2
848 #define GARLIC_COHE_CP_RB1_WPTR__ADDRESS__SHIFT 0x2
850 #define GARLIC_COHE_CP_RB2_WPTR__ADDRESS__SHIFT 0x2
852 #define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS__SHIFT 0x2
854 #define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
856 #define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
858 #define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS__SHIFT 0x2
860 #define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS__SHIFT 0x2
862 #define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS__SHIFT 0x2
864 #define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS__SHIFT 0x2
866 #define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS__SHIFT 0x2
868 #define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS__SHIFT 0x2
870 #define GARLIC_COHE_VCE_RB_WPTR__ADDRESS__SHIFT 0x2
872 #define GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
874 #define GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
876 #define GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS__SHIFT 0x2
878 #define GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS__SHIFT 0x2
880 #define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
882 #define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
930 #define BIF_RB_RPTR__OFFSET__SHIFT 0x2
934 #define BIF_RB_WPTR__OFFSET__SHIFT 0x2
938 #define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
945 #define COMMAND__MEM_ACCESS_EN_MASK 0x2
948 #define COMMAND__BUS_MASTER_EN__SHIFT 0x2
1117 #define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
1120 #define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
1141 #define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2
1144 #define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
1269 #define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2
1272 #define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
1292 #define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
1361 #define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
1385 #define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
1687 #define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
1690 #define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
1863 #define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
1866 #define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
1879 #define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2
1882 #define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
1915 #define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2
1919 #define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2
1935 #define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2
1938 #define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
1943 #define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2
1946 #define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
1955 #define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2
1958 #define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
2025 #define BIF_MM_INDACCESS_CNTL_IND__MM_INDACCESS_DIS_MASK 0x2
2029 #define BUS_CNTL_IND__BIOS_ROM_DIS_MASK 0x2
2032 #define BUS_CNTL_IND__PMI_IO_DIS__SHIFT 0x2
2057 #define CONFIG_CNTL_IND__VGA_DIS_MASK 0x2
2060 #define CONFIG_CNTL_IND__GENMO_MONO_ADDRESS_B__SHIFT 0x2
2077 #define BX_RESET_EN_IND__REG_RESET_EN_MASK 0x2
2080 #define BX_RESET_EN_IND__STY_RESET_EN__SHIFT 0x2
2087 #define HW_DEBUG_IND__HW_01_DEBUG_MASK 0x2
2090 #define HW_DEBUG_IND__HW_02_DEBUG__SHIFT 0x2
2169 #define INTERRUPT_CNTL_IND__IH_DUMMY_RD_EN_MASK 0x2
2187 #define BIF_DEBUG_CNTL_IND__DEBUG_MULTIBLOCKEN_MASK 0x2
2190 #define BIF_DEBUG_CNTL_IND__DEBUG_OUT_EN__SHIFT 0x2
2221 #define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SEL_MASK 0x2
2224 #define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_MODE__SHIFT 0x2
2245 #define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SEL_MASK 0x2
2248 #define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_MODE__SHIFT 0x2
2269 #define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SEL_MASK 0x2
2272 #define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_MODE__SHIFT 0x2
2299 #define BIF_FEATURES_CONTROL_MISC_IND__SLV_BIF_CPL_EP_DIS_MASK 0x2
2302 #define BIF_FEATURES_CONTROL_MISC_IND__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
2325 #define BIF_DOORBELL_CNTL_IND__TRANS_CHECK_DIS_MASK 0x2
2328 #define BIF_DOORBELL_CNTL_IND__UNTRANS_LBACK_EN__SHIFT 0x2
2341 #define BIF_FB_EN_IND__FB_WRITE_EN_MASK 0x2
2373 #define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET0_MASK 0x2
2376 #define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET1__SHIFT 0x2
2389 #define GPU_HDP_FLUSH_REQ_IND__CP1_MASK 0x2
2392 #define GPU_HDP_FLUSH_REQ_IND__CP2__SHIFT 0x2
2413 #define GPU_HDP_FLUSH_DONE_IND__CP1_MASK 0x2
2416 #define GPU_HDP_FLUSH_DONE_IND__CP2__SHIFT 0x2
2437 #define SLAVE_HANG_ERROR_IND__HDP_HANG_ERROR_MASK 0x2
2440 #define SLAVE_HANG_ERROR_IND__VGA_HANG_ERROR__SHIFT 0x2
2513 #define BACO_CNTL_IND__BACO_BCLK_OFF_MASK 0x2
2516 #define BACO_CNTL_IND__BACO_ISO_DIS__SHIFT 0x2
2545 #define BF_ANA_ISO_CNTL_IND__BF_VDDC_ISO_DIS_MASK_MASK 0x2
2555 #define BACO_CNTL_MISC_IND__BIF_AZ_REQ_DIS_MASK 0x2
2558 #define BACO_CNTL_MISC_IND__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
2562 #define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
2568 #define BIF_VDDGFX_GFX0_UPPER_IND__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
2570 #define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
2576 #define BIF_VDDGFX_GFX1_UPPER_IND__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
2578 #define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
2584 #define BIF_VDDGFX_GFX2_UPPER_IND__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
2586 #define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
2592 #define BIF_VDDGFX_GFX3_UPPER_IND__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
2594 #define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
2600 #define BIF_VDDGFX_GFX4_UPPER_IND__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
2602 #define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
2608 #define BIF_VDDGFX_GFX5_UPPER_IND__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
2610 #define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
2616 #define BIF_VDDGFX_RSV1_UPPER_IND__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
2618 #define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
2624 #define BIF_VDDGFX_RSV2_UPPER_IND__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
2626 #define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
2632 #define BIF_VDDGFX_RSV3_UPPER_IND__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
2634 #define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
2640 #define BIF_VDDGFX_RSV4_UPPER_IND__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
2643 #define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_STALL_EN_MASK 0x2
2646 #define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
2654 #define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
2658 #define BIF_DOORBELL_GBLAPER1_UPPER_IND__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
2660 #define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
2664 #define BIF_DOORBELL_GBLAPER2_UPPER_IND__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
2666 #define BIF_SMU_INDEX_IND__BIF_SMU_INDEX__SHIFT 0x2
2668 #define BIF_SMU_DATA_IND__BIF_SMU_DATA__SHIFT 0x2
2673 #define GARLIC_FLUSH_CNTL_IND__CP_RB1_WPTR_MASK 0x2
2676 #define GARLIC_FLUSH_CNTL_IND__CP_RB2_WPTR__SHIFT 0x2
2717 #define GPU_GARLIC_FLUSH_REQ_IND__CP1_MASK 0x2
2720 #define GPU_GARLIC_FLUSH_REQ_IND__CP2__SHIFT 0x2
2745 #define GPU_GARLIC_FLUSH_DONE_IND__CP1_MASK 0x2
2748 #define GPU_GARLIC_FLUSH_DONE_IND__CP2__SHIFT 0x2
2772 #define GARLIC_COHE_CP_RB0_WPTR_IND__ADDRESS__SHIFT 0x2
2774 #define GARLIC_COHE_CP_RB1_WPTR_IND__ADDRESS__SHIFT 0x2
2776 #define GARLIC_COHE_CP_RB2_WPTR_IND__ADDRESS__SHIFT 0x2
2778 #define GARLIC_COHE_UVD_RBC_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2780 #define GARLIC_COHE_SDMA0_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2782 #define GARLIC_COHE_SDMA1_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2784 #define GARLIC_COHE_CP_DMA_ME_COMMAND_IND__ADDRESS__SHIFT 0x2
2786 #define GARLIC_COHE_CP_DMA_PFP_COMMAND_IND__ADDRESS__SHIFT 0x2
2788 #define GARLIC_COHE_SAM_SAB_RBI_WPTR_IND__ADDRESS__SHIFT 0x2
2790 #define GARLIC_COHE_SAM_SAB_RBO_WPTR_IND__ADDRESS__SHIFT 0x2
2792 #define GARLIC_COHE_VCE_OUT_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2794 #define GARLIC_COHE_VCE_RB_WPTR2_IND__ADDRESS__SHIFT 0x2
2796 #define GARLIC_COHE_VCE_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2798 #define GARLIC_COHE_SDMA2_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2800 #define GARLIC_COHE_SDMA3_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2802 #define GARLIC_COHE_CP_DMA_PIO_COMMAND_IND__ADDRESS__SHIFT 0x2
2804 #define GARLIC_COHE_GARLIC_FLUSH_REQ_IND__ADDRESS__SHIFT 0x2
2806 #define REMAP_HDP_MEM_FLUSH_CNTL_IND__ADDRESS__SHIFT 0x2
2808 #define REMAP_HDP_REG_FLUSH_CNTL_IND__ADDRESS__SHIFT 0x2
2856 #define BIF_RB_RPTR_IND__OFFSET__SHIFT 0x2
2860 #define BIF_RB_WPTR_IND__OFFSET__SHIFT 0x2
2864 #define BIF_RB_WPTR_ADDR_LO_IND__ADDR__SHIFT 0x2
2883 #define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
2886 #define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
2975 #define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2
2978 #define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
2991 #define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2
2994 #define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
3033 #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
3036 #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
3052 #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
3066 #define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2
3092 #define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
3167 #define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
3170 #define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
3179 #define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
3182 #define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
3213 #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
3216 #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
3219 #define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
3222 #define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
3259 #define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2
3262 #define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2
3297 #define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
3300 #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
3415 #define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
3418 #define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
3451 #define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2
3454 #define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2
3485 #define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2
3488 #define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2
3553 #define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
3556 #define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
3671 #define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
3674 #define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
3703 #define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
3706 #define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
3797 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
3800 #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
3849 #define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
3852 #define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
3881 #define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
3884 #define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
3935 #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
3938 #define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
3955 #define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
3958 #define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
4139 #define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
4142 #define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
4253 #define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
4256 #define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
4400 #define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
4421 #define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
4424 #define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
4437 #define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2
4449 #define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWGBIF_rst_MASK 0x2
4452 #define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWGBIF_rst__SHIFT 0x2
4455 #define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWGBIF_rst_MASK 0x2
4458 #define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x2
4461 #define BIF_PWDN_COMMAND__REG_RWREG_RFEWGBIF_pw_cmd_MASK 0x2
4464 #define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x2
4467 #define BIF_PWDN_STATUS__RWREG_RFEWGBIF_REG_pw_status_MASK 0x2
4470 #define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x2
4525 #define BIF_RESET_EN_IND__SOFT_RST_MODE_MASK 0x2
4528 #define BIF_RESET_EN_IND__PHY_RESET_EN__SHIFT 0x2
4583 #define BIF_RESET_CNTL_IND__RST_DONE_MASK 0x2
4586 #define BIF_RESET_CNTL_IND__LINK_TRAIN_EN__SHIFT 0x2
4595 #define BIF_RFE_CNTL_MISC_IND__ADAPT_pif1_bu_reg_accessMode_MASK 0x2
4598 #define BIF_RFE_CNTL_MISC_IND__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2
4629 #define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x2
4632 #define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x2
4687 #define BIF_RESET_CNTL__RST_DONE_MASK 0x2
4690 #define BIF_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x2
4699 #define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode_MASK 0x2
4702 #define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2
4723 #define D2F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
4726 #define D2F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
4755 #define D2F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
4758 #define D2F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
4843 #define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
4846 #define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
4895 #define D2F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
4898 #define D2F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
4923 #define D2F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
4926 #define D2F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
4981 #define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
4984 #define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
5004 #define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
5028 #define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
5045 #define D2F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
5048 #define D2F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
5182 #define D2F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
5236 #define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
5241 #define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
5244 #define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
5371 #define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
5374 #define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
5520 #define D2F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
5541 #define D2F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
5544 #define D2F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
5561 #define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
5564 #define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
5587 #define D2F1_COMMAND__MEM_ACCESS_EN_MASK 0x2
5590 #define D2F1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
5805 #define D2F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
5808 #define D2F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
5897 #define D2F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
5900 #define D2F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
5921 #define D2F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
5924 #define D2F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
5961 #define D2F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
5964 #define D2F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
6082 #define D2F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
6369 #define D2F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
6372 #define D2F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
6375 #define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
6378 #define D2F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
6409 #define D2F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
6412 #define D2F1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
6585 #define D2F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
6588 #define D2F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
6661 #define D2F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
6664 #define D2F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
6693 #define D2F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
6696 #define D2F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
6781 #define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
6784 #define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
6833 #define D2F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
6836 #define D2F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
6861 #define D2F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
6864 #define D2F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
6919 #define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
6922 #define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
6942 #define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
6966 #define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
6983 #define D2F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
6986 #define D2F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
7120 #define D2F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
7174 #define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
7179 #define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
7182 #define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
7309 #define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
7312 #define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
7458 #define D2F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
7479 #define D2F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
7482 #define D2F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
7499 #define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
7502 #define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
7525 #define D2F2_COMMAND__MEM_ACCESS_EN_MASK 0x2
7528 #define D2F2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
7743 #define D2F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
7746 #define D2F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
7835 #define D2F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
7838 #define D2F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
7859 #define D2F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
7862 #define D2F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
7899 #define D2F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
7902 #define D2F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
8020 #define D2F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
8307 #define D2F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
8310 #define D2F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
8313 #define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
8316 #define D2F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
8347 #define D2F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
8350 #define D2F2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
8523 #define D2F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
8526 #define D2F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
8599 #define D2F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
8602 #define D2F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
8631 #define D2F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
8634 #define D2F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
8719 #define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
8722 #define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
8771 #define D2F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
8774 #define D2F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
8799 #define D2F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
8802 #define D2F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
8857 #define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
8860 #define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
8880 #define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
8904 #define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
8921 #define D2F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
8924 #define D2F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
9058 #define D2F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
9112 #define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
9117 #define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
9120 #define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
9247 #define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
9250 #define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
9396 #define D2F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
9417 #define D2F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
9420 #define D2F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
9437 #define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
9440 #define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
9463 #define D2F3_COMMAND__MEM_ACCESS_EN_MASK 0x2
9466 #define D2F3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
9681 #define D2F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
9684 #define D2F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
9773 #define D2F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
9776 #define D2F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
9797 #define D2F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
9800 #define D2F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
9837 #define D2F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
9840 #define D2F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
9958 #define D2F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
10245 #define D2F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
10248 #define D2F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
10251 #define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
10254 #define D2F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
10285 #define D2F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
10288 #define D2F3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
10461 #define D2F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
10464 #define D2F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
10537 #define D2F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
10540 #define D2F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
10569 #define D2F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
10572 #define D2F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
10657 #define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
10660 #define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
10709 #define D2F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
10712 #define D2F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
10737 #define D2F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
10740 #define D2F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
10795 #define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
10798 #define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
10818 #define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
10842 #define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
10859 #define D2F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
10862 #define D2F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
10996 #define D2F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
11050 #define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
11055 #define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
11058 #define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
11185 #define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
11188 #define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
11334 #define D2F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
11355 #define D2F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
11358 #define D2F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
11375 #define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
11378 #define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
11401 #define D2F4_COMMAND__MEM_ACCESS_EN_MASK 0x2
11404 #define D2F4_COMMAND__BUS_MASTER_EN__SHIFT 0x2
11619 #define D2F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
11622 #define D2F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
11711 #define D2F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
11714 #define D2F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
11735 #define D2F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
11738 #define D2F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
11775 #define D2F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
11778 #define D2F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
11896 #define D2F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
12183 #define D2F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
12186 #define D2F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
12189 #define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
12192 #define D2F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
12223 #define D2F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
12226 #define D2F4_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
12399 #define D2F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
12402 #define D2F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
12475 #define D2F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
12478 #define D2F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
12507 #define D2F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
12510 #define D2F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
12595 #define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
12598 #define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
12647 #define D2F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
12650 #define D2F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
12675 #define D2F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
12678 #define D2F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
12733 #define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
12736 #define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
12756 #define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
12780 #define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
12797 #define D2F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
12800 #define D2F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
12934 #define D2F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
12988 #define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
12993 #define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
12996 #define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
13123 #define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
13126 #define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
13272 #define D2F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
13293 #define D2F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
13296 #define D2F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
13313 #define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
13316 #define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
13339 #define D2F5_COMMAND__MEM_ACCESS_EN_MASK 0x2
13342 #define D2F5_COMMAND__BUS_MASTER_EN__SHIFT 0x2
13557 #define D2F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
13560 #define D2F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
13649 #define D2F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
13652 #define D2F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
13673 #define D2F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
13676 #define D2F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
13713 #define D2F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
13716 #define D2F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
13834 #define D2F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
14121 #define D2F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
14124 #define D2F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
14127 #define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
14130 #define D2F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
14161 #define D2F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
14164 #define D2F5_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
14337 #define D2F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
14340 #define D2F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
14413 #define D3F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
14416 #define D3F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
14445 #define D3F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
14448 #define D3F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
14533 #define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
14536 #define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
14585 #define D3F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
14588 #define D3F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
14613 #define D3F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
14616 #define D3F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
14671 #define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
14674 #define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
14694 #define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
14718 #define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
14735 #define D3F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
14738 #define D3F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
14872 #define D3F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
14926 #define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
14931 #define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
14934 #define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
15061 #define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
15064 #define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
15210 #define D3F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
15231 #define D3F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
15234 #define D3F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
15251 #define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
15254 #define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
15277 #define D3F1_COMMAND__MEM_ACCESS_EN_MASK 0x2
15280 #define D3F1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
15495 #define D3F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
15498 #define D3F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
15587 #define D3F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
15590 #define D3F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
15611 #define D3F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
15614 #define D3F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
15651 #define D3F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
15654 #define D3F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
15772 #define D3F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
16059 #define D3F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
16062 #define D3F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
16065 #define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
16068 #define D3F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
16099 #define D3F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
16102 #define D3F1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
16275 #define D3F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
16278 #define D3F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
16351 #define D3F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
16354 #define D3F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
16383 #define D3F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
16386 #define D3F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
16471 #define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
16474 #define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
16523 #define D3F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
16526 #define D3F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
16551 #define D3F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
16554 #define D3F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
16609 #define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
16612 #define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
16632 #define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
16656 #define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
16673 #define D3F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
16676 #define D3F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
16810 #define D3F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
16864 #define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
16869 #define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
16872 #define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
16999 #define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
17002 #define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
17148 #define D3F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
17169 #define D3F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
17172 #define D3F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
17189 #define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
17192 #define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
17215 #define D3F2_COMMAND__MEM_ACCESS_EN_MASK 0x2
17218 #define D3F2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
17433 #define D3F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
17436 #define D3F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
17525 #define D3F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
17528 #define D3F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
17549 #define D3F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
17552 #define D3F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
17589 #define D3F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
17592 #define D3F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
17710 #define D3F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
17997 #define D3F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
18000 #define D3F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
18003 #define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
18006 #define D3F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
18037 #define D3F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
18040 #define D3F2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
18213 #define D3F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
18216 #define D3F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
18289 #define D3F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
18292 #define D3F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
18321 #define D3F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
18324 #define D3F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
18409 #define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
18412 #define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
18461 #define D3F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
18464 #define D3F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
18489 #define D3F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
18492 #define D3F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
18547 #define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
18550 #define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
18570 #define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
18594 #define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
18611 #define D3F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
18614 #define D3F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
18748 #define D3F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
18802 #define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
18807 #define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
18810 #define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
18937 #define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
18940 #define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
19086 #define D3F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
19107 #define D3F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
19110 #define D3F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
19127 #define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
19130 #define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
19153 #define D3F3_COMMAND__MEM_ACCESS_EN_MASK 0x2
19156 #define D3F3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
19371 #define D3F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
19374 #define D3F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
19463 #define D3F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
19466 #define D3F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
19487 #define D3F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
19490 #define D3F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
19527 #define D3F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
19530 #define D3F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
19648 #define D3F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
19935 #define D3F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
19938 #define D3F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
19941 #define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
19944 #define D3F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
19975 #define D3F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
19978 #define D3F3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
20151 #define D3F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
20154 #define D3F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
20227 #define D3F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
20230 #define D3F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
20259 #define D3F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
20262 #define D3F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
20347 #define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
20350 #define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
20399 #define D3F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
20402 #define D3F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
20427 #define D3F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
20430 #define D3F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
20485 #define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
20488 #define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
20508 #define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
20532 #define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
20549 #define D3F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
20552 #define D3F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
20686 #define D3F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
20740 #define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
20745 #define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
20748 #define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
20875 #define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
20878 #define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
21024 #define D3F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
21045 #define D3F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
21048 #define D3F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
21065 #define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
21068 #define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
21091 #define D3F4_COMMAND__MEM_ACCESS_EN_MASK 0x2
21094 #define D3F4_COMMAND__BUS_MASTER_EN__SHIFT 0x2
21309 #define D3F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
21312 #define D3F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
21401 #define D3F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
21404 #define D3F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
21425 #define D3F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
21428 #define D3F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
21465 #define D3F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
21468 #define D3F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
21586 #define D3F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
21873 #define D3F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
21876 #define D3F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
21879 #define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
21882 #define D3F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
21913 #define D3F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
21916 #define D3F4_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
22089 #define D3F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
22092 #define D3F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
22165 #define D3F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
22168 #define D3F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
22197 #define D3F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
22200 #define D3F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
22285 #define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
22288 #define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
22337 #define D3F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
22340 #define D3F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
22365 #define D3F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
22368 #define D3F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
22423 #define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
22426 #define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
22446 #define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
22470 #define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
22487 #define D3F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
22490 #define D3F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
22624 #define D3F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
22678 #define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
22683 #define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
22686 #define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
22813 #define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
22816 #define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
22962 #define D3F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
22983 #define D3F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
22986 #define D3F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
23003 #define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
23006 #define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
23029 #define D3F5_COMMAND__MEM_ACCESS_EN_MASK 0x2
23032 #define D3F5_COMMAND__BUS_MASTER_EN__SHIFT 0x2
23247 #define D3F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
23250 #define D3F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
23339 #define D3F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
23342 #define D3F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
23363 #define D3F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
23366 #define D3F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
23403 #define D3F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
23406 #define D3F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
23524 #define D3F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
23811 #define D3F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
23814 #define D3F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
23817 #define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
23820 #define D3F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
23851 #define D3F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
23854 #define D3F5_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
24027 #define D3F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
24030 #define D3F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
24097 #define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK 0x2
24100 #define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT 0x2
24129 #define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK 0x2
24132 #define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT 0x2
24147 #define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK 0x2
24150 #define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT 0x2
24179 #define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK 0x2
24182 #define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT 0x2
24186 #define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT 0x2
24212 #define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24268 #define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24324 #define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24380 #define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24436 #define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24491 #define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2
24494 #define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2
24539 #define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2
24541 #define PSX80_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK 0x2
24544 #define PSX80_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2
24585 #define PSX80_WRP_DTM_CNTL__Dtm_Dummy1_MASK 0x2
24588 #define PSX80_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT 0x2
24637 #define PSX80_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK 0x2
24640 #define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT 0x2
24687 #define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK 0x2
24690 #define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT 0x2
24709 #define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK 0x2
24712 #define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT 0x2
24723 #define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK 0x2
24726 #define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT 0x2
24755 #define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK 0x2
24758 #define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT 0x2
24773 #define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK 0x2
24776 #define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT 0x2
24805 #define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK 0x2
24808 #define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT 0x2
24812 #define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT 0x2
24838 #define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24894 #define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24950 #define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
25006 #define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
25062 #define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
25117 #define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2
25120 #define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2
25165 #define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2
25167 #define PSX81_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK 0x2
25170 #define PSX81_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2
25211 #define PSX81_WRP_DTM_CNTL__Dtm_Dummy1_MASK 0x2
25214 #define PSX81_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT 0x2
25263 #define PSX81_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK 0x2
25266 #define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT 0x2
25313 #define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK 0x2
25316 #define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT 0x2
25335 #define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK 0x2
25338 #define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT 0x2
25351 #define RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2
25363 #define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWRC_rst_MASK 0x2
25366 #define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWRC_rst__SHIFT 0x2
25369 #define RFE_MASTER_SOFTRST_TRIGGER__PCIEW1_rst_MASK 0x2
25372 #define RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWRC_rst__SHIFT 0x2
25375 #define RFE_PWDN_COMMAND__REG_PCIEW1_pw_cmd_MASK 0x2
25378 #define RFE_PWDN_COMMAND__REG_RWREG_RFEWRC_pw_cmd__SHIFT 0x2
25381 #define RFE_PWDN_STATUS__PCIEW1_REG_pw_status_MASK 0x2
25384 #define RFE_PWDN_STATUS__RWREG_RFEWRC_REG_pw_status__SHIFT 0x2
25421 #define PSX80_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
25424 #define PSX80_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
25551 #define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
25554 #define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
25578 #define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
25590 #define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
25663 #define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
25666 #define PSX80_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
25675 #define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
25678 #define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
25709 #define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
25712 #define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
25717 #define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
25720 #define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
25757 #define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
25760 #define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
25875 #define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
25878 #define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
25945 #define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
25948 #define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
26033 #define PSX80_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2
26041 #define PSX80_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2
26044 #define PSX80_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
26079 #define PSX80_BIF_SWRST_COMMAND_1__RESETPCFG_MASK 0x2
26082 #define PSX80_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2
26135 #define PSX80_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2
26138 #define PSX80_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2
26191 #define PSX80_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2
26194 #define PSX80_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2
26247 #define PSX80_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2
26250 #define PSX80_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2
26291 #define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2
26294 #define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
26445 #define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2
26448 #define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2
26491 #define PSX80_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2
26494 #define PSX80_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2
26553 #define PSX81_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
26556 #define PSX81_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
26683 #define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
26686 #define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
26710 #define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
26722 #define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
26795 #define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
26798 #define PSX81_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
26807 #define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
26810 #define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
26841 #define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
26844 #define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
26849 #define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
26852 #define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
26889 #define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
26892 #define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
27007 #define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
27010 #define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
27077 #define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
27080 #define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
27165 #define PSX81_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2
27173 #define PSX81_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2
27176 #define PSX81_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
27211 #define PSX81_BIF_SWRST_COMMAND_1__RESETPCFG_MASK 0x2
27214 #define PSX81_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2
27267 #define PSX81_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2
27270 #define PSX81_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2
27323 #define PSX81_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2
27326 #define PSX81_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2
27379 #define PSX81_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2
27382 #define PSX81_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2
27423 #define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2
27426 #define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
27577 #define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2
27580 #define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2
27623 #define PSX81_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2
27626 #define PSX81_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2
27721 #define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK 0x2
27724 #define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT 0x2
27852 #define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT 0x2
28149 #define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK 0x2
28165 #define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK 0x2
28181 #define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK 0x2
28197 #define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK 0x2
28213 #define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK 0x2
28229 #define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK 0x2
28245 #define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK 0x2
28261 #define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK 0x2
28277 #define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK 0x2
28293 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK 0x2
28296 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT 0x2
28303 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK 0x2
28306 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT 0x2
28313 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK 0x2
28316 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT 0x2
28323 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK 0x2
28326 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT 0x2
28333 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK 0x2
28336 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT 0x2
28343 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK 0x2
28346 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT 0x2
28353 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK 0x2
28356 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT 0x2
28363 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK 0x2
28366 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT 0x2
28373 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK 0x2
28376 #define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT 0x2
28581 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28584 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28597 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28600 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28613 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28616 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28629 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28632 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28645 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28648 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28661 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28664 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28677 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28680 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28693 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28696 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28709 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28712 #define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28725 #define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK 0x2
28728 #define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT 0x2
28741 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK 0x2
28744 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT 0x2
28757 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK 0x2
28760 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT 0x2
28773 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK 0x2
28776 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT 0x2
28789 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK 0x2
28792 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT 0x2
28805 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK 0x2
28808 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT 0x2
28821 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK 0x2
28824 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT 0x2
28837 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK 0x2
28840 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT 0x2
28853 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK 0x2
28856 #define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT 0x2
28978 #define PSX80_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT 0x2
28986 #define PSX80_PHY0_TX_DFX_LANE0__obs_sel__SHIFT 0x2
28994 #define PSX80_PHY0_TX_DFX_LANE1__obs_sel__SHIFT 0x2
29002 #define PSX80_PHY0_TX_DFX_LANE2__obs_sel__SHIFT 0x2
29010 #define PSX80_PHY0_TX_DFX_LANE3__obs_sel__SHIFT 0x2
29018 #define PSX80_PHY0_TX_DFX_LANE4__obs_sel__SHIFT 0x2
29026 #define PSX80_PHY0_TX_DFX_LANE5__obs_sel__SHIFT 0x2
29034 #define PSX80_PHY0_TX_DFX_LANE6__obs_sel__SHIFT 0x2
29042 #define PSX80_PHY0_TX_DFX_LANE7__obs_sel__SHIFT 0x2
29393 #define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK 0x2
29396 #define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x2
29535 #define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK 0x2
29538 #define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT 0x2
29666 #define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT 0x2
29963 #define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK 0x2
29979 #define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK 0x2
29995 #define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK 0x2
30011 #define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK 0x2
30027 #define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK 0x2
30043 #define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK 0x2
30059 #define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK 0x2
30075 #define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK 0x2
30091 #define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK 0x2
30107 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK 0x2
30110 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT 0x2
30117 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK 0x2
30120 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT 0x2
30127 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK 0x2
30130 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT 0x2
30137 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK 0x2
30140 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT 0x2
30147 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK 0x2
30150 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT 0x2
30157 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK 0x2
30160 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT 0x2
30167 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK 0x2
30170 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT 0x2
30177 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK 0x2
30180 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT 0x2
30187 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK 0x2
30190 #define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT 0x2
30395 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30398 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30411 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30414 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30427 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30430 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30443 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30446 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30459 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30462 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30475 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30478 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30491 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30494 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30507 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30510 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30523 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30526 #define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30539 #define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK 0x2
30542 #define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT 0x2
30555 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK 0x2
30558 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT 0x2
30571 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK 0x2
30574 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT 0x2
30587 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK 0x2
30590 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT 0x2
30603 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK 0x2
30606 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT 0x2
30619 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK 0x2
30622 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT 0x2
30635 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK 0x2
30638 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT 0x2
30651 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK 0x2
30654 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT 0x2
30667 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK 0x2
30670 #define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT 0x2
30792 #define PSX81_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT 0x2
30800 #define PSX81_PHY0_TX_DFX_LANE0__obs_sel__SHIFT 0x2
30808 #define PSX81_PHY0_TX_DFX_LANE1__obs_sel__SHIFT 0x2
30816 #define PSX81_PHY0_TX_DFX_LANE2__obs_sel__SHIFT 0x2
30824 #define PSX81_PHY0_TX_DFX_LANE3__obs_sel__SHIFT 0x2
30832 #define PSX81_PHY0_TX_DFX_LANE4__obs_sel__SHIFT 0x2
30840 #define PSX81_PHY0_TX_DFX_LANE5__obs_sel__SHIFT 0x2
30848 #define PSX81_PHY0_TX_DFX_LANE6__obs_sel__SHIFT 0x2
30856 #define PSX81_PHY0_TX_DFX_LANE7__obs_sel__SHIFT 0x2
31207 #define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK 0x2
31210 #define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x2
31311 #define PSX80_PIF0_HW_DEBUG__HW_01_DEBUG_MASK 0x2
31314 #define PSX80_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
31341 #define PSX80_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
31344 #define PSX80_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
31371 #define PSX80_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
31374 #define PSX80_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
31495 #define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
31498 #define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
31513 #define PSX80_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
31516 #define PSX80_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
31543 #define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
31546 #define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
31608 #define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
31621 #define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
31624 #define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
31651 #define PSX80_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
31654 #define PSX80_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
31719 #define PSX80_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
31722 #define PSX80_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
31787 #define PSX80_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
31790 #define PSX80_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
31855 #define PSX80_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
31858 #define PSX80_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
31923 #define PSX80_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
31926 #define PSX80_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
31991 #define PSX80_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
31994 #define PSX80_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
32059 #define PSX80_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
32062 #define PSX80_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
32127 #define PSX80_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
32130 #define PSX80_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
32197 #define PSX81_PIF0_HW_DEBUG__HW_01_DEBUG_MASK 0x2
32200 #define PSX81_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
32227 #define PSX81_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
32230 #define PSX81_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
32257 #define PSX81_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
32260 #define PSX81_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
32381 #define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
32384 #define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
32399 #define PSX81_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
32402 #define PSX81_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
32429 #define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
32432 #define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
32494 #define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
32507 #define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
32510 #define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
32537 #define PSX81_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
32540 #define PSX81_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
32605 #define PSX81_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
32608 #define PSX81_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
32673 #define PSX81_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
32676 #define PSX81_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
32741 #define PSX81_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
32744 #define PSX81_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
32809 #define PSX81_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
32812 #define PSX81_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
32877 #define PSX81_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
32880 #define PSX81_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
32945 #define PSX81_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
32948 #define PSX81_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
33013 #define PSX81_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
33016 #define PSX81_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
/linux-4.4.14/drivers/gpu/drm/
H A Ddrm_rect.c46 r1->x2 = min(r1->x2, r2->x2); drm_rect_intersect()
84 diff = dst->x2 - clip->x2; drm_rect_clip_scaled()
86 int64_t tmp = src->x2 - (int64_t) diff * hscale; drm_rect_clip_scaled()
87 src->x2 = clamp_t(int64_t, tmp, INT_MIN, INT_MAX); drm_rect_clip_scaled()
323 r->x1 = width - tmp.x2; drm_rect_rotate()
324 r->x2 = width - tmp.x1; drm_rect_rotate()
339 r->x2 = tmp.y2; drm_rect_rotate()
340 r->y1 = width - tmp.x2; drm_rect_rotate()
345 r->x1 = width - tmp.x2; drm_rect_rotate()
346 r->x2 = width - tmp.x1; drm_rect_rotate()
353 r->x2 = height - tmp.y1; drm_rect_rotate()
355 r->y2 = tmp.x2; drm_rect_rotate()
399 r->x2 = width - tmp.y1; drm_rect_rotate_inv()
401 r->y2 = tmp.x2; drm_rect_rotate_inv()
405 r->x1 = width - tmp.x2; drm_rect_rotate_inv()
406 r->x2 = width - tmp.x1; drm_rect_rotate_inv()
413 r->x2 = tmp.y2; drm_rect_rotate_inv()
414 r->y1 = height - tmp.x2; drm_rect_rotate_inv()
425 r->x1 = width - tmp.x2; drm_rect_rotate_inv()
426 r->x2 = width - tmp.x1; drm_rect_rotate_inv()
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_enum.h48 #define SMC_MSG_PHY_LN_OFF 0x2
80 ENDIAN_8IN32 = 0x2,
86 ARRAY_1D_TILED_THIN1 = 0x2,
104 CONFIG_4_PIPE = 0x2,
118 CONFIG_4KB_ROW = 0x2,
128 CONFIG_512B_SWAPS = 0x2,
134 CONFIG_4KB_SPLIT = 0x2,
140 ADDR_CONFIG_4_PIPE = 0x2,
150 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
164 ADDR_CONFIG_4_GPU = 0x2,
169 ADDR_CONFIG_GPU_TILE_64 = 0x2,
175 ADDR_CONFIG_4KB_ROW = 0x2,
184 DBG_CLIENT_BLKID_uvdu_0 = 0x2,
324 DBG_BLOCK_ID_VMC = 0x2,
558 DBG_BLOCK_ID_CG_BY2 = 0x2,
676 DBG_BLOCK_ID_CSC_BY4 = 0x2,
736 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
767 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
784 ABGR_TO_A_BG_G_RB = 0x2,
790 REF_EQUAL = 0x2,
804 DEPTH_X8_24 = 0x2,
814 Z_24 = 0x2,
824 CMASK_CLEAR_ALL = 0x2,
842 EXPORT_32_GR = 0x2,
852 EXPORT_4P_32BPC_GR = 0x2,
860 COLOR_16 = 0x2,
886 FMT_16 = 0x2,
952 BUF_DATA_FORMAT_16 = 0x2,
970 IMG_DATA_FORMAT_16 = 0x2,
1036 BUF_NUM_FORMAT_USCALED = 0x2,
1046 IMG_NUM_FORMAT_USCALED = 0x2,
1072 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1079 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1088 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1094 ADDR_SURF_P2_RESERVED1 = 0x2,
1114 ADDR_SURF_8_BANK = 0x2,
1120 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1126 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1132 ADDR_SURF_BANK_WH_4 = 0x2,
1138 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1144 GATCL1_TYPE_BYPASS = 0x2,
1153 MTYPE_CC = 0x2,
1159 PERFMON_COUNTER_MODE_MAX = 0x2,
1172 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1189 ARRAY_3D = 0x2,
H A Dsmu_8_0_enum.h30 DBG_BLOCK_ID_VMC = 0x2,
287 DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
409 DBG_BLOCK_ID_CSC_BY4 = 0x2,
471 DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
503 DBG_BLOCK_ID_SXM_BY16 = 0x2,
520 ENDIAN_8IN32 = 0x2,
526 ARRAY_1D_TILED_THIN1 = 0x2,
544 CONFIG_4_PIPE = 0x2,
558 CONFIG_4KB_ROW = 0x2,
568 CONFIG_512B_SWAPS = 0x2,
574 CONFIG_4KB_SPLIT = 0x2,
580 ADDR_CONFIG_4_PIPE = 0x2,
590 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
604 ADDR_CONFIG_4_GPU = 0x2,
609 ADDR_CONFIG_GPU_TILE_64 = 0x2,
615 ADDR_CONFIG_4KB_ROW = 0x2,
624 ABGR_TO_A_BG_G_RB = 0x2,
630 REF_EQUAL = 0x2,
644 DEPTH_X8_24 = 0x2,
654 Z_24 = 0x2,
664 CMASK_CLEAR_ALL = 0x2,
682 EXPORT_32_GR = 0x2,
692 EXPORT_4P_32BPC_GR = 0x2,
700 COLOR_16 = 0x2,
726 FMT_16 = 0x2,
792 BUF_DATA_FORMAT_16 = 0x2,
810 IMG_DATA_FORMAT_16 = 0x2,
876 BUF_NUM_FORMAT_USCALED = 0x2,
886 IMG_NUM_FORMAT_USCALED = 0x2,
912 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
919 ADDR_SURF_TILE_SPLIT_256B = 0x2,
928 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
934 ADDR_SURF_P2_RESERVED1 = 0x2,
954 ADDR_SURF_8_BANK = 0x2,
960 ADDR_SURF_BANK_WIDTH_4 = 0x2,
966 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
972 ADDR_SURF_BANK_WH_4 = 0x2,
978 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
984 GATCL1_TYPE_BYPASS = 0x2,
993 MTYPE_CC = 0x2,
999 PERFMON_COUNTER_MODE_MAX = 0x2,
1012 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1029 ARRAY_3D = 0x2,
1047 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1061 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
H A Dsmu_7_1_0_enum.h41 #define SMC_MSG_PHY_LN_OFF 0x2
73 ENDIAN_8IN32 = 0x2,
79 ARRAY_1D_TILED_THIN1 = 0x2,
97 CONFIG_4_PIPE = 0x2,
111 CONFIG_4KB_ROW = 0x2,
121 CONFIG_512B_SWAPS = 0x2,
127 CONFIG_4KB_SPLIT = 0x2,
133 ADDR_CONFIG_4_PIPE = 0x2,
144 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
158 ADDR_CONFIG_4_GPU = 0x2,
163 ADDR_CONFIG_GPU_TILE_64 = 0x2,
169 ADDR_CONFIG_4KB_ROW = 0x2,
178 DBG_CLIENT_BLKID_dco0 = 0x2,
329 DBG_BLOCK_ID_VMC = 0x2,
563 DBG_BLOCK_ID_CG_BY2 = 0x2,
681 DBG_BLOCK_ID_CSC_BY4 = 0x2,
741 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
772 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
789 REF_EQUAL = 0x2,
803 DEPTH_X8_24 = 0x2,
813 Z_24 = 0x2,
823 CMASK_CLEAR_ALL = 0x2,
841 EXPORT_32_GR = 0x2,
851 EXPORT_4P_32BPC_GR = 0x2,
859 COLOR_16 = 0x2,
885 FMT_16 = 0x2,
951 BUF_DATA_FORMAT_16 = 0x2,
969 IMG_DATA_FORMAT_16 = 0x2,
1035 BUF_NUM_FORMAT_USCALED = 0x2,
1045 IMG_NUM_FORMAT_USCALED = 0x2,
1071 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1078 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1087 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1093 ADDR_SURF_P2_RESERVED1 = 0x2,
1113 ADDR_SURF_8_BANK = 0x2,
1119 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1125 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1131 ADDR_SURF_BANK_WH_4 = 0x2,
1137 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1143 TCC_CACHE_POLICY_BYPASS = 0x2,
1148 PERFMON_COUNTER_MODE_MAX = 0x2,
1161 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1178 ARRAY_3D = 0x2,
H A Dsmu_7_1_2_enum.h48 #define SMC_MSG_PHY_LN_OFF 0x2
80 ENDIAN_8IN32 = 0x2,
86 ARRAY_1D_TILED_THIN1 = 0x2,
104 CONFIG_4_PIPE = 0x2,
118 CONFIG_4KB_ROW = 0x2,
128 CONFIG_512B_SWAPS = 0x2,
134 CONFIG_4KB_SPLIT = 0x2,
140 ADDR_CONFIG_4_PIPE = 0x2,
150 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
164 ADDR_CONFIG_4_GPU = 0x2,
169 ADDR_CONFIG_GPU_TILE_64 = 0x2,
175 ADDR_CONFIG_4KB_ROW = 0x2,
184 DBG_CLIENT_BLKID_scf2 = 0x2,
342 DBG_BLOCK_ID_VMC = 0x2,
576 DBG_BLOCK_ID_CG_BY2 = 0x2,
694 DBG_BLOCK_ID_CSC_BY4 = 0x2,
754 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
785 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
802 ABGR_TO_A_BG_G_RB = 0x2,
808 REF_EQUAL = 0x2,
822 DEPTH_X8_24 = 0x2,
832 Z_24 = 0x2,
842 CMASK_CLEAR_ALL = 0x2,
860 EXPORT_32_GR = 0x2,
870 EXPORT_4P_32BPC_GR = 0x2,
878 COLOR_16 = 0x2,
904 FMT_16 = 0x2,
970 BUF_DATA_FORMAT_16 = 0x2,
988 IMG_DATA_FORMAT_16 = 0x2,
1054 BUF_NUM_FORMAT_USCALED = 0x2,
1064 IMG_NUM_FORMAT_USCALED = 0x2,
1090 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1097 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1106 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1112 ADDR_SURF_P2_RESERVED1 = 0x2,
1132 ADDR_SURF_8_BANK = 0x2,
1138 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1144 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1150 ADDR_SURF_BANK_WH_4 = 0x2,
1156 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1162 GATCL1_TYPE_BYPASS = 0x2,
1171 MTYPE_CC = 0x2,
1177 PERFMON_COUNTER_MODE_MAX = 0x2,
1190 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1207 ARRAY_3D = 0x2,
1225 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1239 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
H A Dsmu_7_1_3_enum.h45 #define SMC_MSG_PHY_LN_OFF 0x2
77 ENDIAN_8IN32 = 0x2,
83 ARRAY_1D_TILED_THIN1 = 0x2,
101 CONFIG_4_PIPE = 0x2,
115 CONFIG_4KB_ROW = 0x2,
125 CONFIG_512B_SWAPS = 0x2,
131 CONFIG_4KB_SPLIT = 0x2,
137 ADDR_CONFIG_4_PIPE = 0x2,
147 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
161 ADDR_CONFIG_4_GPU = 0x2,
166 ADDR_CONFIG_GPU_TILE_64 = 0x2,
172 ADDR_CONFIG_4KB_ROW = 0x2,
181 DBG_CLIENT_BLKID_scf2 = 0x2,
378 DBG_BLOCK_ID_VMC = 0x2,
612 DBG_BLOCK_ID_CG_BY2 = 0x2,
730 DBG_BLOCK_ID_CSC_BY4 = 0x2,
790 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
821 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
838 ABGR_TO_A_BG_G_RB = 0x2,
844 REF_EQUAL = 0x2,
858 DEPTH_X8_24 = 0x2,
868 Z_24 = 0x2,
878 CMASK_CLEAR_ALL = 0x2,
896 EXPORT_32_GR = 0x2,
906 EXPORT_4P_32BPC_GR = 0x2,
914 COLOR_16 = 0x2,
940 FMT_16 = 0x2,
1006 BUF_DATA_FORMAT_16 = 0x2,
1024 IMG_DATA_FORMAT_16 = 0x2,
1090 BUF_NUM_FORMAT_USCALED = 0x2,
1100 IMG_NUM_FORMAT_USCALED = 0x2,
1126 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1133 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1142 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1148 ADDR_SURF_P2_RESERVED1 = 0x2,
1168 ADDR_SURF_8_BANK = 0x2,
1174 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1180 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1186 ADDR_SURF_BANK_WH_4 = 0x2,
1192 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1198 GATCL1_TYPE_BYPASS = 0x2,
1207 MTYPE_CC = 0x2,
1213 PERFMON_COUNTER_MODE_MAX = 0x2,
1226 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1243 ARRAY_3D = 0x2,
1261 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1275 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
H A Dsmu_8_0_sh_mask.h37 #define THM_TCON_HTC__RSVD0_MASK 0x2
40 #define THM_TCON_HTC__HTC_P_STATE_EN__SHIFT 0x2
87 #define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x2
90 #define THM_TCON_THERM_TRIP__RSVD1__SHIFT 0x2
103 #define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x2
106 #define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2
123 #define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x2
126 #define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2
143 #define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
146 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
171 #define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
174 #define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
383 #define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x2
386 #define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2
396 #define THM_TCON_LOCAL2__PwrDn_NumSensors__SHIFT 0x2
431 #define THM_TCON_LOCAL13__PowerDownTmon1_MASK 0x2
452 #define THM_FUSE1__FUSE_TconUseSecondary__SHIFT 0x2
651 #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
654 #define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
699 #define SAM_IH_EXT_ERR_INTR__VCE_MASK 0x2
702 #define SAM_IH_EXT_ERR_INTR__ISP__SHIFT 0x2
707 #define SAM_IH_EXT_ERR_INTR_STATUS__VCE_MASK 0x2
710 #define SAM_IH_EXT_ERR_INTR_STATUS__ISP__SHIFT 0x2
883 #define SMU_DISP0_TIMER_INT_CONTROL__INT_UNMASK_MASK 0x2
886 #define SMU_DISP0_TIMER_INT_CONTROL__INT_TYPE__SHIFT 0x2
893 #define SMU_DISP1_TIMER_INT_CONTROL__INT_UNMASK_MASK 0x2
896 #define SMU_DISP1_TIMER_INT_CONTROL__INT_TYPE__SHIFT 0x2
909 #define MP_SRBM_CONTROL__ALLOW_NS_ACC_MASK 0x2
912 #define MP_SRBM_CONTROL__SOFT_RST_MASK__SHIFT 0x2
925 #define MP_CRBBM_CONTROL__MP0_ACCESS_MASK 0x2
928 #define MP_CRBBM_CONTROL__ALLOW_NS_ACC__SHIFT 0x2
931 #define MP_CRBBM_ACCVIO_LOG__ACC_VIO_INTF_MASK 0x2
1047 #define MP_DRAM_CNTL_RDRET_VALID__vld_1_MASK 0x2
1050 #define MP_DRAM_CNTL_RDRET_VALID__vld_2__SHIFT 0x2
1068 #define MP_DRAM_CNTL_RDRET_NACK__nack_1__SHIFT 0x2
1213 #define MP_IOC_CTRL__IOC_mst_stop_MASK 0x2
1216 #define MP_IOC_CTRL__IOC_mst_force_active__SHIFT 0x2
1231 #define MP_IOC_PHASE1__BiuCqfC_AwqReqCommit_MASK 0x2
1234 #define MP_IOC_PHASE1__BiuCqfC_AltReqRdCmd__SHIFT 0x2
1407 #define UNBPM_NBPWRMGT_FSM_CFG__DIS_AUTO_PWRGATE_ON_EXIT_MASK 0x2
1421 #define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER1_MASK 0x2
1424 #define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER0__SHIFT 0x2
1447 #define MISC_GNB_PWRMGT_DATA__GN_ALLOW_NB_PSTATES_MASK 0x2
1450 #define MISC_GNB_PWRMGT_DATA__GN_FLUSH_REQ_TOGGLE__SHIFT 0x2
1465 #define MISC_SMU_PWRMGT_DATA__NB_MEMPS_MASK 0x2
1559 #define UNBPM_WARM_RESET_HS_STATUS__WARM_RESET_HS_DONE_MASK 0x2
1577 #define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_0_MASK 0x2
1580 #define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_1__SHIFT 0x2
1584 #define SPR_PROGRAMMABLE_CTRL__PllVddOutUpTime__SHIFT 0x2
1691 #define RCC3ON_CPU_0__RCC3_PSM_EN_MASK 0x2
1694 #define RCC3ON_CPU_0__RCC3_PSM_CLK_DIV__SHIFT 0x2
1742 #define SPMI_CONFIG0_0__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT 0x2
1765 #define SPMI_PATH_0__PATH_ENABLE_ACK_MASK 0x2
1771 #define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK 0x2
1774 #define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT 0x2
1805 #define RCC3ON_CPU_1__RCC3_PSM_EN_MASK 0x2
1808 #define RCC3ON_CPU_1__RCC3_PSM_CLK_DIV__SHIFT 0x2
1856 #define SPMI_CONFIG0_1__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT 0x2
1879 #define SPMI_PATH_1__PATH_ENABLE_ACK_MASK 0x2
1885 #define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK 0x2
1888 #define SPMI_C6_STATE_1__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT 0x2
1913 #define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
1916 #define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
1950 #define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
2015 #define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
2018 #define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
2077 #define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
2080 #define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
2139 #define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
2142 #define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
2201 #define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
2204 #define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
2263 #define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
2266 #define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
2325 #define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
2328 #define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
2387 #define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
2390 #define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
2449 #define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
2452 #define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
2557 #define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
2560 #define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
2587 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
2590 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
2643 #define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
2646 #define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
2779 #define PWR_ACPI_INTERRUPT__AZ_CG_req_MASK 0x2
2782 #define PWR_ACPI_INTERRUPT__AZ_CG_resp__SHIFT 0x2
2789 #define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2
2792 #define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2
2887 #define GNBPM_SMU_PWRMGT_DATA__UNBPM_HtcActive_MASK 0x2
2890 #define GNBPM_SMU_PWRMGT_DATA__UNBPM_SmuInt__SHIFT 0x2
2903 #define GNBPM_SMU_PWRMGT_STATUS__PM_HtcActive_MASK 0x2
2906 #define GNBPM_SMU_PWRMGT_STATUS__PM_SmuInt__SHIFT 0x2
/linux-4.4.14/arch/tile/kernel/
H A Dtile-desc_64.c34 { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
55 { "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1,
58 { "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1,
61 { "prefetch_add_l2", TILEGX_OPC_PREFETCH_ADD_L2, 0x2, 2, TREG_ZERO, 1,
64 { "prefetch_add_l2_fault", TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 0x2, 2, TREG_ZERO, 1,
67 { "prefetch_add_l3", TILEGX_OPC_PREFETCH_ADD_L3, 0x2, 2, TREG_ZERO, 1,
70 { "prefetch_add_l3_fault", TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 0x2, 2, TREG_ZERO, 1,
91 { "raise", TILEGX_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
121 { "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1,
124 { "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1,
136 { "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
139 { "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
142 { "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1,
145 { "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1,
148 { "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1,
151 { "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1,
154 { "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1,
157 { "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1,
160 { "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
163 { "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
166 { "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1,
169 { "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1,
172 { "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1,
175 { "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1,
193 { "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1,
196 { "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1,
262 { "drain", TILEGX_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0,
265 { "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
268 { "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1,
271 { "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1,
298 { "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1,
301 { "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1,
304 { "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1,
307 { "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1,
310 { "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1,
313 { "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1,
316 { "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1,
319 { "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1,
322 { "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
325 { "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
328 { "flushwb", TILEGX_OPC_FLUSHWB, 0x2, 0, TREG_ZERO, 1,
355 { "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
361 { "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1,
364 { "iret", TILEGX_OPC_IRET, 0x2, 0, TREG_ZERO, 1,
367 { "j", TILEGX_OPC_J, 0x2, 1, TREG_ZERO, 1,
370 { "jal", TILEGX_OPC_JAL, 0x2, 1, TREG_LR, 1,
391 { "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1,
397 { "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1,
403 { "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1,
409 { "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1,
415 { "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1,
421 { "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1,
424 { "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1,
427 { "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1,
430 { "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1,
433 { "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1,
436 { "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1,
439 { "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1,
442 { "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1,
445 { "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1,
448 { "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1,
451 { "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1,
454 { "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1,
457 { "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1,
460 { "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1,
463 { "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1,
466 { "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1,
469 { "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1,
472 { "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1,
478 { "mf", TILEGX_OPC_MF, 0x2, 0, TREG_ZERO, 1,
481 { "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
490 { "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
562 { "nap", TILEGX_OPC_NAP, 0x2, 0, TREG_ZERO, 0,
652 { "st1_add", TILEGX_OPC_ST1_ADD, 0x2, 3, TREG_ZERO, 1,
658 { "st2_add", TILEGX_OPC_ST2_ADD, 0x2, 3, TREG_ZERO, 1,
664 { "st4_add", TILEGX_OPC_ST4_ADD, 0x2, 3, TREG_ZERO, 1,
667 { "st_add", TILEGX_OPC_ST_ADD, 0x2, 3, TREG_ZERO, 1,
670 { "stnt", TILEGX_OPC_STNT, 0x2, 2, TREG_ZERO, 1,
673 { "stnt1", TILEGX_OPC_STNT1, 0x2, 2, TREG_ZERO, 1,
676 { "stnt1_add", TILEGX_OPC_STNT1_ADD, 0x2, 3, TREG_ZERO, 1,
679 { "stnt2", TILEGX_OPC_STNT2, 0x2, 2, TREG_ZERO, 1,
682 { "stnt2_add", TILEGX_OPC_STNT2_ADD, 0x2, 3, TREG_ZERO, 1,
685 { "stnt4", TILEGX_OPC_STNT4, 0x2, 2, TREG_ZERO, 1,
688 { "stnt4_add", TILEGX_OPC_STNT4_ADD, 0x2, 3, TREG_ZERO, 1,
691 { "stnt_add", TILEGX_OPC_STNT_ADD, 0x2, 3, TREG_ZERO, 1,
703 { "swint0", TILEGX_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0,
706 { "swint1", TILEGX_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0,
709 { "swint2", TILEGX_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0,
712 { "swint3", TILEGX_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0,
1024 { "wh64", TILEGX_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
H A Dtile-desc_32.c34 { "bpt", TILEPRO_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
43 { "j", TILEPRO_OPC_J, 0x2, 1, TREG_ZERO, 1,
46 { "jal", TILEPRO_OPC_JAL, 0x2, 1, TREG_LR, 1,
73 { "raise", TILEPRO_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
178 { "bbns", TILEPRO_OPC_BBNS, 0x2, 2, TREG_ZERO, 1,
181 { "bbns.sn", TILEPRO_OPC_BBNS_SN, 0x2, 2, TREG_SN, 1,
184 { "bbnst", TILEPRO_OPC_BBNST, 0x2, 2, TREG_ZERO, 1,
187 { "bbnst.sn", TILEPRO_OPC_BBNST_SN, 0x2, 2, TREG_SN, 1,
190 { "bbs", TILEPRO_OPC_BBS, 0x2, 2, TREG_ZERO, 1,
193 { "bbs.sn", TILEPRO_OPC_BBS_SN, 0x2, 2, TREG_SN, 1,
196 { "bbst", TILEPRO_OPC_BBST, 0x2, 2, TREG_ZERO, 1,
199 { "bbst.sn", TILEPRO_OPC_BBST_SN, 0x2, 2, TREG_SN, 1,
202 { "bgez", TILEPRO_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
205 { "bgez.sn", TILEPRO_OPC_BGEZ_SN, 0x2, 2, TREG_SN, 1,
208 { "bgezt", TILEPRO_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
211 { "bgezt.sn", TILEPRO_OPC_BGEZT_SN, 0x2, 2, TREG_SN, 1,
214 { "bgz", TILEPRO_OPC_BGZ, 0x2, 2, TREG_ZERO, 1,
217 { "bgz.sn", TILEPRO_OPC_BGZ_SN, 0x2, 2, TREG_SN, 1,
220 { "bgzt", TILEPRO_OPC_BGZT, 0x2, 2, TREG_ZERO, 1,
223 { "bgzt.sn", TILEPRO_OPC_BGZT_SN, 0x2, 2, TREG_SN, 1,
232 { "blez", TILEPRO_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
235 { "blez.sn", TILEPRO_OPC_BLEZ_SN, 0x2, 2, TREG_SN, 1,
238 { "blezt", TILEPRO_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
241 { "blezt.sn", TILEPRO_OPC_BLEZT_SN, 0x2, 2, TREG_SN, 1,
244 { "blz", TILEPRO_OPC_BLZ, 0x2, 2, TREG_ZERO, 1,
247 { "blz.sn", TILEPRO_OPC_BLZ_SN, 0x2, 2, TREG_SN, 1,
250 { "blzt", TILEPRO_OPC_BLZT, 0x2, 2, TREG_ZERO, 1,
253 { "blzt.sn", TILEPRO_OPC_BLZT_SN, 0x2, 2, TREG_SN, 1,
256 { "bnz", TILEPRO_OPC_BNZ, 0x2, 2, TREG_ZERO, 1,
259 { "bnz.sn", TILEPRO_OPC_BNZ_SN, 0x2, 2, TREG_SN, 1,
262 { "bnzt", TILEPRO_OPC_BNZT, 0x2, 2, TREG_ZERO, 1,
265 { "bnzt.sn", TILEPRO_OPC_BNZT_SN, 0x2, 2, TREG_SN, 1,
274 { "bz", TILEPRO_OPC_BZ, 0x2, 2, TREG_ZERO, 1,
277 { "bz.sn", TILEPRO_OPC_BZ_SN, 0x2, 2, TREG_SN, 1,
280 { "bzt", TILEPRO_OPC_BZT, 0x2, 2, TREG_ZERO, 1,
283 { "bzt.sn", TILEPRO_OPC_BZT_SN, 0x2, 2, TREG_SN, 1,
310 { "drain", TILEPRO_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0,
313 { "dtlbpr", TILEPRO_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
322 { "finv", TILEPRO_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
325 { "flush", TILEPRO_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
331 { "icoh", TILEPRO_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
361 { "inv", TILEPRO_OPC_INV, 0x2, 1, TREG_ZERO, 1,
364 { "iret", TILEPRO_OPC_IRET, 0x2, 0, TREG_ZERO, 1,
367 { "jalb", TILEPRO_OPC_JALB, 0x2, 1, TREG_LR, 1,
370 { "jalf", TILEPRO_OPC_JALF, 0x2, 1, TREG_LR, 1,
373 { "jalr", TILEPRO_OPC_JALR, 0x2, 1, TREG_LR, 1,
376 { "jalrp", TILEPRO_OPC_JALRP, 0x2, 1, TREG_LR, 1,
379 { "jb", TILEPRO_OPC_JB, 0x2, 1, TREG_ZERO, 1,
382 { "jf", TILEPRO_OPC_JF, 0x2, 1, TREG_ZERO, 1,
385 { "jr", TILEPRO_OPC_JR, 0x2, 1, TREG_ZERO, 1,
388 { "jrp", TILEPRO_OPC_JRP, 0x2, 1, TREG_ZERO, 1,
394 { "lb.sn", TILEPRO_OPC_LB_SN, 0x2, 2, TREG_SN, 1,
400 { "lb_u.sn", TILEPRO_OPC_LB_U_SN, 0x2, 2, TREG_SN, 1,
403 { "lbadd", TILEPRO_OPC_LBADD, 0x2, 3, TREG_ZERO, 1,
406 { "lbadd.sn", TILEPRO_OPC_LBADD_SN, 0x2, 3, TREG_SN, 1,
409 { "lbadd_u", TILEPRO_OPC_LBADD_U, 0x2, 3, TREG_ZERO, 1,
412 { "lbadd_u.sn", TILEPRO_OPC_LBADD_U_SN, 0x2, 3, TREG_SN, 1,
418 { "lh.sn", TILEPRO_OPC_LH_SN, 0x2, 2, TREG_SN, 1,
424 { "lh_u.sn", TILEPRO_OPC_LH_U_SN, 0x2, 2, TREG_SN, 1,
427 { "lhadd", TILEPRO_OPC_LHADD, 0x2, 3, TREG_ZERO, 1,
430 { "lhadd.sn", TILEPRO_OPC_LHADD_SN, 0x2, 3, TREG_SN, 1,
433 { "lhadd_u", TILEPRO_OPC_LHADD_U, 0x2, 3, TREG_ZERO, 1,
436 { "lhadd_u.sn", TILEPRO_OPC_LHADD_U_SN, 0x2, 3, TREG_SN, 1,
439 { "lnk", TILEPRO_OPC_LNK, 0x2, 1, TREG_ZERO, 1,
442 { "lnk.sn", TILEPRO_OPC_LNK_SN, 0x2, 1, TREG_SN, 1,
448 { "lw.sn", TILEPRO_OPC_LW_SN, 0x2, 2, TREG_SN, 1,
451 { "lw_na", TILEPRO_OPC_LW_NA, 0x2, 2, TREG_ZERO, 1,
454 { "lw_na.sn", TILEPRO_OPC_LW_NA_SN, 0x2, 2, TREG_SN, 1,
457 { "lwadd", TILEPRO_OPC_LWADD, 0x2, 3, TREG_ZERO, 1,
460 { "lwadd.sn", TILEPRO_OPC_LWADD_SN, 0x2, 3, TREG_SN, 1,
463 { "lwadd_na", TILEPRO_OPC_LWADD_NA, 0x2, 3, TREG_ZERO, 1,
466 { "lwadd_na.sn", TILEPRO_OPC_LWADD_NA_SN, 0x2, 3, TREG_SN, 1,
493 { "mf", TILEPRO_OPC_MF, 0x2, 0, TREG_ZERO, 1,
496 { "mfspr", TILEPRO_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
544 { "mtspr", TILEPRO_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
715 { "nap", TILEPRO_OPC_NAP, 0x2, 0, TREG_ZERO, 0,
838 { "sbadd", TILEPRO_OPC_SBADD, 0x2, 3, TREG_ZERO, 1,
880 { "shadd", TILEPRO_OPC_SHADD, 0x2, 3, TREG_ZERO, 1,
1156 { "swadd", TILEPRO_OPC_SWADD, 0x2, 3, TREG_ZERO, 1,
1159 { "swint0", TILEPRO_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0,
1162 { "swint1", TILEPRO_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0,
1165 { "swint2", TILEPRO_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0,
1168 { "swint3", TILEPRO_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0,
1195 { "tns", TILEPRO_OPC_TNS, 0x2, 2, TREG_ZERO, 1,
1198 { "tns.sn", TILEPRO_OPC_TNS_SN, 0x2, 2, TREG_SN, 1,
1201 { "wh64", TILEPRO_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
/linux-4.4.14/arch/arm64/kernel/vdso/
H A Dgettimeofday.S54 mov x2, x30
55 .cfi_register x30, x2
79 ret x2
84 ret x2
95 mov x2, x30
96 .cfi_register x30, x2
106 mov x30, x2
166 mov x30, x2
181 ldr x2, 5f
187 ldr x2, 6f
190 stp xzr, x2, [x1]
/linux-4.4.14/arch/sparc/include/asm/
H A Dsfp-machine_32.h78 #define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
85 : "%rJ" ((USItype)(x2)), \
93 #define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
100 : "%rJ" ((USItype)(x2)), \
108 #define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
122 "%rJ" ((USItype)(x2)), \
133 #define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
147 "%rJ" ((USItype)(x2)), \
158 #define __FP_FRAC_DEC_3(x2,x1,x0,y2,y1,y0) __FP_FRAC_SUB_3(x2,x1,x0,x2,x1,x0,y2,y1,y0)
160 #define __FP_FRAC_DEC_4(x3,x2,x1,x0,y3,y2,y1,y0) __FP_FRAC_SUB_4(x3,x2,x1,x0,x3,x2,x1,x0,y3,y2,y1,y0)
162 #define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i) \
168 "=&r" (x2), \
173 "1" ((USItype)(x2)), \
H A Dide.h43 if(((unsigned long)ps) & 0x2) { __ide_insw()
73 if(((unsigned long)src) & 0x2) { __ide_outsw()
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/phy/
H A Dphy-pistachio-usb.h14 #define REFCLK_CLK_CORE 0x2
/linux-4.4.14/include/video/
H A Diga.h19 #define MEM_SIZE_4M 0x2
H A Dsamsung_fimd.h28 #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
38 #define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
47 #define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
56 #define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
85 #define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
106 #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
199 #define WINCONx_BURSTLEN_4WORD (0x2 << 9)
206 #define WINCON0_BPPMODE_4BPP (0x2 << 2)
219 #define WINCON1_BPPMODE_4BPP (0x2 << 2)
333 #define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
340 #define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
347 #define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
356 #define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
393 #define DITHMODE_R_POS_5BIT (0x2 << 5)
398 #define DITHMODE_G_POS_5BIT (0x2 << 3)
403 #define DITHMODE_B_POS_5BIT (0x2 << 1)
424 #define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
433 #define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
448 #define DP_MIE_CLK_DP_ENABLE 0x2
/linux-4.4.14/include/dt-bindings/phy/
H A Dphy-pistachio-usb.h14 #define REFCLK_CLK_CORE 0x2
/linux-4.4.14/include/linux/ceph/
H A Dceph_hash.h5 #define CEPH_STR_HASH_RJENKINS 0x2 /* robert jenkins' */
/linux-4.4.14/arch/sh/include/uapi/asm/
H A Dcachectl.h7 #define CACHEFLUSH_D_WB 0x2 /* write back (without invalidate) */
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/phy/
H A Dphy-pistachio-usb.h14 #define REFCLK_CLK_CORE 0x2
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/phy/
H A Dphy-pistachio-usb.h14 #define REFCLK_CLK_CORE 0x2
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/phy/
H A Dphy-pistachio-usb.h14 #define REFCLK_CLK_CORE 0x2
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/phy/
H A Dphy-pistachio-usb.h14 #define REFCLK_CLK_CORE 0x2
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/phy/
H A Dphy-pistachio-usb.h14 #define REFCLK_CLK_CORE 0x2
/linux-4.4.14/arch/s390/include/asm/
H A Dsfp-machine.h75 #define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) ({ \
76 unsigned int __r2 = (x2) + (y2); \
101 #define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) ({ \
102 unsigned int __r2 = (x2) - (y2); \
127 #define __FP_FRAC_DEC_3(x2,x1,x0,y2,y1,y0) __FP_FRAC_SUB_3(x2,x1,x0,x2,x1,x0,y2,y1,y0)
/linux-4.4.14/arch/arm64/kernel/
H A Defi-entry.S50 add x2, sp, 16
51 str x8, [x2]
72 adrp x2, _edata
73 add x2, x2, #:lo12:_edata
74 sub x1, x2, x1
114 mov x2, xzr
H A Dentry-ftrace.S102 ldr x2, [x0, #:lo12:ftrace_trace_function]
104 cmp x0, x2 // if (ftrace_trace_function
109 blr x2 // (*ftrace_trace_function)(pc, lr);
119 ldr x2, [x1, #:lo12:ftrace_graph_return]
120 cmp x0, x2 // if ((ftrace_graph_return
125 ldr x2, [x1, #:lo12:ftrace_graph_entry]
127 cmp x0, x2
185 stp x2, x3, [sp, #16]
193 ldp x2, x3, [sp, #16]
211 mcount_get_parent_fp x2 // parent's fp
H A Dentry.S46 ldp x2, x3, [sp, #S_X2]
74 stp x2, x3, [sp, #16 * 1]
147 ldp x2, x3, [sp, #16 * 1]
235 mrs x2, esr_el1
312 mov x2, sp // struct pt_regs
324 mov x2, sp
341 mov x2, sp // struct pt_regs
348 mov x2, x1
475 mov x2, sp
488 mov x2, sp
521 mov x2, sp
541 mov x2, sp
551 mov x2, x25
613 and x2, x1, #_TIF_SYSCALL_WORK
614 cbnz x2, ret_fast_syscall_trace
615 and x2, x1, #_TIF_WORK_MASK
616 cbnz x2, work_pending
617 enable_step_tsk x1, x2
629 ldr x2, [sp, #S_PSTATE]
631 tst x2, #PSR_MODE_MASK // user mode regs?
645 and x2, x1, #_TIF_WORK_MASK
646 cbnz x2, work_pending
647 enable_step_tsk x1, x2
710 ldp x2, x3, [sp, #S_X2]
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb/
H A Dvsc7326_reg.h21 #define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */
22 #define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */
23 #define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */
49 /*#define REG_RAM_BIST_CMD CRA(0x7,0x2,0x00)*/ /* RAM BIST Command Register */
50 /*#define REG_RAM_BIST_RESULT CRA(0x7,0x2,0x01)*/ /* RAM BIST Read Status/Result */
70 #define REG_TEST(ie,fn) CRA(0x2,ie&1,0x00+fn) /* Mode & Test Register */
71 #define REG_TOP_BOTTOM(ie,fn) CRA(0x2,ie&1,0x10+fn) /* FIFO Buffer Top & Bottom */
72 #define REG_TAIL(ie,fn) CRA(0x2,ie&1,0x20+fn) /* FIFO Write Pointer */
73 #define REG_HEAD(ie,fn) CRA(0x2,ie&1,0x30+fn) /* FIFO Read Pointer */
74 #define REG_HIGH_LOW_WM(ie,fn) CRA(0x2,ie&1,0x40+fn) /* Flow Control Water Marks */
75 #define REG_CT_THRHLD(ie,fn) CRA(0x2,ie&1,0x50+fn) /* Cut Through Threshold */
76 #define REG_FIFO_DROP_CNT(ie,fn) CRA(0x2,ie&1,0x60+fn) /* Drop & CRC Error Counter */
77 #define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */
78 #define REG_BUCKI(fn) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */
79 #define REG_BUCKE(fn) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */
86 #define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) CRA(0x2,ie&1,0x0a + (bn>7) | ((bn&7)<<4))
87 #define REG_TRAFFIC_SHAPER_CONTROL(ie) CRA(0x2,ie&1,0x3b)
89 #define REG_SRAM_ADR(ie) CRA(0x2,ie&1,0x0e) /* FIFO SRAM address */
90 #define REG_SRAM_WR_STRB(ie) CRA(0x2,ie&1,0x1e) /* FIFO SRAM write strobe */
91 #define REG_SRAM_RD_STRB(ie) CRA(0x2,ie&1,0x2e) /* FIFO SRAM read strobe */
92 #define REG_SRAM_DATA_0(ie) CRA(0x2,ie&1,0x3e) /* FIFO SRAM data lo 8b */
93 #define REG_SRAM_DATA_1(ie) CRA(0x2,ie&1,0x4e) /* FIFO SRAM data lomid 8b */
94 #define REG_SRAM_DATA_2(ie) CRA(0x2,ie&1,0x5e) /* FIFO SRAM data himid 8b */
95 #define REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e) /* FIFO SRAM data hi 8b */
96 #define REG_SRAM_DATA_BLK_TYPE(ie) CRA(0x2,ie&1,0x7e) /* FIFO SRAM tag */
98 #define REG_CONTROL(ie) CRA(0x2,ie&1,0x0f) /* FIFO control */
99 #define REG_ING_CONTROL CRA(0x2,0x0,0x0f) /* Ingress control (alias) */
100 #define REG_EGR_CONTROL CRA(0x2,0x1,0x0f) /* Egress control (alias) */
101 #define REG_AGE_TIMER(ie) CRA(0x2,ie&1,0x1f) /* Aging timer */
102 #define REG_AGE_INC(ie) CRA(0x2,ie&1,0x2f) /* Aging increment */
103 #define DEBUG_OUT(ie) CRA(0x2,ie&1,0x3f) /* Output debug counter control */
104 #define DEBUG_CNT(ie) CRA(0x2,ie&1,0x4f) /* Output debug counter */
285 #define REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd)
286 #define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d)
287 #define REG_ING_FFILT_VAL0 CRA(0x2, 0, 0x2d)
288 #define REG_ING_FFILT_VAL1 CRA(0x2, 0, 0x3d)
289 #define REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d)
290 #define REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d)
291 #define REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d)
292 #define REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d)
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_enum.h30 NUMBER_USCALED = 0x2,
40 SWAP_STD_REV = 0x2,
46 CB_ELIMINATE_FAST_CLEAR = 0x2,
59 EXPORT_2C_32BPC_GR = 0x2,
65 BLEND_SRC_COLOR = 0x2,
88 COMB_MIN_DST_SRC = 0x2,
95 FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x2,
105 CMASK_CLR00_F2 = 0x2,
123 CMASK_ADDR_COMPATIBLE = 0x2,
128 CB_PERF_SEL_CORE_SCLK_VLD = 0x2,
535 CB_PERF_OP_FILTER_SEL_RESOLVE = 0x2,
547 RINGID2 = 0x2,
553 PIPE_ID2 = 0x2,
559 ME_ID2 = 0x2,
565 STRM_PERFMON_STATE_STOP_COUNTING = 0x2,
573 CP_PERFMON_STATE_STOP_COUNTING = 0x2,
581 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x2,
587 CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x2,
638 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x2,
660 CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x2,
687 CPF_TAG_RAM = 0x2,
692 #define SEM_FAILED 0x2
696 #define IQ_SCH_WAVE_MSG 0x2
701 #define IQ_INTR_TYPE_MQD 0x2
718 FORCE_DISABLE = 0x2,
728 RE_Z = 0x2,
734 ZPASS_PIXELS = 0x2,
739 FORCE_LATE_Z = 0x2,
745 FORCE_SUMM_MAXZ = 0x2,
751 FRAG_EQUAL = 0x2,
761 STENCIL_ONES = 0x2,
779 EXPORT_GREATER_THAN_Z = 0x2,
785 PSLC_ASAP = 0x2,
791 DB_PERF_SEL_SC_DB_tile_stalls = 0x2,
1059 COUNTER_RING_1 = 0x2,
1064 PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x2,
1074 PIXEL_PIPE_STRIDE_128_BITS = 0x2,
1080 GB_EDC_DED_MODE_INT_HALT = 0x2,
1087 GRBM_PERF_SEL_GUI_ACTIVE = 0x2,
1123 GRBM_SE0_PERF_SEL_CB_BUSY = 0x2,
1140 GRBM_SE1_PERF_SEL_CB_BUSY = 0x2,
1157 GRBM_SE2_PERF_SEL_CB_BUSY = 0x2,
1174 GRBM_SE3_PERF_SEL_CB_BUSY = 0x2,
1191 PERF_PAPC_PASX_FIRST_VECTOR = 0x2,
1346 SC_TPQZ_WINDOW_VALID = 0x2,
1745 RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x2,
1751 RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x2,
1757 RASTER_CONFIG_SE_PAIR_MAP_2 = 0x2,
1763 RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x2,
1769 RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x2,
1775 RASTER_CONFIG_SE_MAP_2 = 0x2,
1781 RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x2,
1787 RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x2,
1793 RASTER_CONFIG_SC_MAP_2 = 0x2,
1799 RASTER_CONFIG_PKR_XSEL2_2 = 0x2,
1805 RASTER_CONFIG_PKR_XSEL_2 = 0x2,
1811 RASTER_CONFIG_PKR_YSEL_2 = 0x2,
1817 RASTER_CONFIG_PKR_MAP_2 = 0x2,
1831 RASTER_CONFIG_RB_XSEL2_2 = 0x2,
1837 RASTER_CONFIG_RB_MAP_2 = 0x2,
1843 CSDATA_TYPE_EVENT = 0x2,
1846 #define CSDATA_TYPE_WIDTH 0x2
1852 CENTROIDS_AND_CENTERS = 0x2,
1858 SPI_FOG_EXP2 = 0x2,
1864 SPI_PNT_SPRITE_SEL_S = 0x2,
1871 SPI_PERF_VS_FIRST_WAVE = 0x2,
2070 SPI_SHADER_2COMP = 0x2,
2077 SPI_SHADER_32_GR = 0x2,
2089 PROG_SEQ = 0x2,
2100 SQ_TEX_CLAMP_LAST_TEXEL = 0x2,
2110 SQ_TEX_XY_FILTER_ANISO_POINT = 0x2,
2116 SQ_TEX_Z_FILTER_LINEAR = 0x2,
2121 SQ_TEX_MIP_FILTER_LINEAR = 0x2,
2127 SQ_TEX_ANISO_RATIO_4 = 0x2,
2134 SQ_TEX_DEPTH_COMPARE_EQUAL = 0x2,
2144 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x2,
2150 SQ_RSRC_BUF_RSVD_2 = 0x2,
2156 SQ_RSRC_IMG_RSVD_2 = 0x2,
2174 SQ_RSRC_FLAT_RSVD_2 = 0x2,
2180 SQ_IMG_FILTER_MODE_MAX = 0x2,
2185 SQ_SEL_RESERVED_0 = 0x2,
2195 SQ_WAVE_TYPE_GS = 0x2,
2205 SQ_THREAD_TRACE_TOKEN_REG = 0x2,
2223 SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x2,
2233 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x2,
2260 SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x2,
2278 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x2,
2283 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x2,
2292 SQ_THREAD_TRACE_ISSUE_INST = 0x2,
2298 SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x2,
2304 SQ_PERF_SEL_CYCLES = 0x2,
2598 SQ_CAC_POWER_VALU1 = 0x2,
2609 SQ_IND_CMD_CMD_SAVECTX = 0x2,
2618 SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x2,
2625 SQ_EDC_INFO_SOURCE_SGPR = 0x2,
2634 SQ_ROUND_MINUS_INFINITY = 0x2,
2640 SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x2,
2645 SQ_EXPORT_RAT_INST_STORE_RAW = 0x2,
2689 SQ_IBUF_IB_INI_WAIT_DRET = 0x2,
2699 SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x2,
2709 SQ_WAVE_IB_ECC_ERR_HALT = 0x2,
2715 SH_MEM_ADDRESS_MODE_HSA64 = 0x2,
2721 SH_MEM_ALIGNMENT_MODE_STRICT = 0x2,
2759 #define SQ_EX_MODE_EXCP_DIV0 0x2
2787 #define SQ_ENC_SOP2_FIELD 0x2
2826 #define SQ_SENDMSG_STREAMID_SIZE 0x2
2839 #define SQ_SENDMSG_GSOP_SIZE 0x2
2873 #define SQ_S_CMOV_B32 0x2
2925 #define SQ_S_CMPK_EQ_I32 0x2
2969 #define SQ_CNT3 0x2
2973 #define SQ_S_LOAD_DWORDX4 0x2
3023 #define SQ_EQ 0x2
3236 #define SQ_L2 0x2
3253 #define SQ_SDWA_UNUSED_PRESERVE 0x2
3256 #define SQ_EQ 0x2
3354 #define SQ_DS_RSUB_U32 0x2
3499 #define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2
3561 #define SQ_OMOD_M4 0x2
3620 #define SQ_GS_OP_EMIT 0x2
3624 #define SQ_IMAGE_LOAD_PCK 0x2
3717 #define SQ_SDWA_BYTE_2 0x2
3726 #define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2
3742 #define SQ_CHAN_Z 0x2
3746 #define SQ_V_READFIRSTLANE_B32 0x2
3830 #define SQ_V_INTERP_MOV_F32 0x2
3833 #define SQ_S_BRANCH 0x2
3867 #define SQ_PARAM_P0 0x2
3871 #define SQ_V_SUB_F32 0x2
3963 #define SQ_S_CMP_GT_I32 0x2
4066 #define SQ_SYSMSG_OP_REG_RD 0x2
4070 #define SQ_HW_REG_STATUS 0x2
4085 #define SQ_R2 0x2
4101 #define SQ_S_ADD_I32 0x2
4144 #define SQ_MSG_GS 0x2
4151 BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x2,
4161 OPT_COMB_SUBTRACT = 0x2,
4171 SX_RT_EXPORT_32_A = 0x2,
4184 TEX_BorderColor_OpaqueWhite = 0x2,
4190 TEX_ChromaKey_Blend = 0x2,
4196 TEX_Clamp_ClampToLast = 0x2,
4210 TEX_DepthCompareFunction_Equal = 0x2,
4220 TEX_Dim_3D = 0x2,
4230 TEX_FormatComp_UnsignedBiased = 0x2,
4236 TEX_MaxAnisoRatio_4to1 = 0x2,
4246 TEX_MipFilter_Linear = 0x2,
4252 TEX_RequestSize_128B = 0x2,
4262 TEX_XYFilter_AnisoPoint = 0x2,
4268 TEX_ZFilter_Linear = 0x2,
4278 VTX_FetchType_NoIndexOffset = 0x2,
4292 TVX_FMT_4_4 = 0x2,
4358 TVX_DstSel_Z = 0x2,
4368 TVX_EndianSwap_8in32 = 0x2,
4374 TVX_Inst_RESERVED_2 = 0x2,
4408 TVX_NumFormatAll_Scaled = 0x2,
4414 TVX_SrcSel_Z = 0x2,
4426 TVX_Type_ValidTextureResource = 0x2,
4437 TC_OP_ATOMIC_FMIN_RTN_32 = 0x2,
4573 TC_NACK_PROTECTION_FAULT = 0x2,
4579 TCC_PERF_SEL_BUSY = 0x2,
4817 TCA_PERF_SEL_BUSY = 0x2,
4854 TA_TC_ADDR_MODE_COMP1 = 0x2,
4863 TA_PERF_SEL_sh_fifo_cmd_busy = 0x2,
4984 TD_PERF_SEL_input_busy = 0x2,
5042 TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x2,
5240 TCP_CACHE_POLICY_HIT_LRU = 0x2,
5250 TCP_WATCH_MODE_ATOMIC = 0x2,
5256 TCP_DSM_SEL1 = 0x2,
5265 VGT_OUT_TRI = 0x2,
5282 DI_PT_LINELIST = 0x2,
5313 DI_SRC_SEL_AUTO_INDEX = 0x2,
5323 DI_INDEX_SIZE_8_BIT = 0x2,
5328 SAMPLE_STREAMOUTSTATS2 = 0x2,
5391 VGT_DMA_SWAP_32_BIT = 0x2,
5397 VGT_INDEX_8 = 0x2,
5402 VGT_DMA_BUF_SETUP = 0x2,
5408 VGT_OUTPATH_PASSTHRU = 0x2,
5415 VGT_GRP_3D_TRI = 0x2,
5435 VGT_GRP_FAN = 0x2,
5442 VGT_GRP_UINT_16 = 0x2,
5453 GS_SCENARIO_B = 0x2,
5461 GS_CUT_256 = 0x2,
5467 TRISTRIP = 0x2,
5472 VC_AND_TC = 0x2,
5477 TESS_QUAD = 0x2,
5482 PART_FRAC_ODD = 0x2,
5488 OUTPUT_TRIANGLE_CW = 0x2,
5498 DONUTS = 0x2,
5503 CS_STAGE_ON = 0x2,
5513 ES_STAGE_REAL = 0x2,
5523 VS_STAGE_COPY_SHADER = 0x2,
5529 vgt_perf_VGT_SPI_ESVERT_EOV = 0x2,
5677 ia_perf_RESERVED1 = 0x2,
5703 wd_perf_RBIU_DR_FIFO_STALLED = 0x2,
5742 WD_IA_DRAW_TYPE_EVENT_INIT = 0x2,
5752 WD_IA_DRAW_SOURCE_AUTO = 0x2,
5755 #define GSTHREADID_SIZE 0x2
5759 DBG_BLOCK_ID_VMC = 0x2,
6016 DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
6138 DBG_BLOCK_ID_CSC_BY4 = 0x2,
6200 DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
6232 DBG_BLOCK_ID_SXM_BY16 = 0x2,
6249 ENDIAN_8IN32 = 0x2,
6255 ARRAY_1D_TILED_THIN1 = 0x2,
6273 CONFIG_4_PIPE = 0x2,
6287 CONFIG_4KB_ROW = 0x2,
6297 CONFIG_512B_SWAPS = 0x2,
6303 CONFIG_4KB_SPLIT = 0x2,
6309 ADDR_CONFIG_4_PIPE = 0x2,
6319 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
6333 ADDR_CONFIG_4_GPU = 0x2,
6338 ADDR_CONFIG_GPU_TILE_64 = 0x2,
6344 ADDR_CONFIG_4KB_ROW = 0x2,
6353 ABGR_TO_A_BG_G_RB = 0x2,
6359 REF_EQUAL = 0x2,
6373 DEPTH_X8_24 = 0x2,
6383 Z_24 = 0x2,
6393 CMASK_CLEAR_ALL = 0x2,
6411 EXPORT_32_GR = 0x2,
6425 EXPORT_4P_32BPC_GR = 0x2,
6433 COLOR_16 = 0x2,
6466 FMT_16 = 0x2,
6532 BUF_DATA_FORMAT_16 = 0x2,
6550 IMG_DATA_FORMAT_16 = 0x2,
6616 BUF_NUM_FORMAT_USCALED = 0x2,
6626 IMG_NUM_FORMAT_USCALED = 0x2,
6652 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
6659 ADDR_SURF_TILE_SPLIT_256B = 0x2,
6668 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
6674 ADDR_SURF_P2_RESERVED1 = 0x2,
6694 ADDR_SURF_8_BANK = 0x2,
6700 ADDR_SURF_BANK_WIDTH_4 = 0x2,
6706 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
6712 ADDR_SURF_BANK_WH_4 = 0x2,
6718 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
6724 GATCL1_TYPE_BYPASS = 0x2,
6733 MTYPE_CC = 0x2,
6739 PERFMON_COUNTER_MODE_MAX = 0x2,
6752 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
6769 ARRAY_3D = 0x2,
6787 FORCE_DEEP_SLEEP_REQUEST = 0x2,
6801 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
H A Dgfx_8_0_enum.h30 NUMBER_USCALED = 0x2,
40 SWAP_STD_REV = 0x2,
46 CB_ELIMINATE_FAST_CLEAR = 0x2,
59 EXPORT_2C_32BPC_GR = 0x2,
65 BLEND_SRC_COLOR = 0x2,
88 COMB_MIN_DST_SRC = 0x2,
95 FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x2,
105 CMASK_CLR00_F2 = 0x2,
123 CMASK_ADDR_COMPATIBLE = 0x2,
128 CB_PERF_SEL_CORE_SCLK_VLD = 0x2,
526 CB_PERF_OP_FILTER_SEL_RESOLVE = 0x2,
538 RINGID2 = 0x2,
544 PIPE_ID2 = 0x2,
550 ME_ID2 = 0x2,
556 STRM_PERFMON_STATE_STOP_COUNTING = 0x2,
564 CP_PERFMON_STATE_STOP_COUNTING = 0x2,
572 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x2,
578 CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x2,
629 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x2,
651 CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x2,
678 CPF_TAG_RAM = 0x2,
683 #define SEM_FAILED 0x2
687 #define IQ_SCH_WAVE_MSG 0x2
692 #define IQ_INTR_TYPE_MQD 0x2
709 FORCE_DISABLE = 0x2,
719 RE_Z = 0x2,
725 ZPASS_PIXELS = 0x2,
730 FORCE_LATE_Z = 0x2,
736 FORCE_SUMM_MAXZ = 0x2,
742 FRAG_EQUAL = 0x2,
752 STENCIL_ONES = 0x2,
770 EXPORT_GREATER_THAN_Z = 0x2,
776 PSLC_ASAP = 0x2,
782 DB_PERF_SEL_SC_DB_tile_stalls = 0x2,
1041 COUNTER_RING_1 = 0x2,
1046 PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x2,
1056 PIXEL_PIPE_STRIDE_128_BITS = 0x2,
1062 GB_EDC_DED_MODE_INT_HALT = 0x2,
1069 GRBM_PERF_SEL_GUI_ACTIVE = 0x2,
1105 GRBM_SE0_PERF_SEL_CB_BUSY = 0x2,
1122 GRBM_SE1_PERF_SEL_CB_BUSY = 0x2,
1139 GRBM_SE2_PERF_SEL_CB_BUSY = 0x2,
1156 GRBM_SE3_PERF_SEL_CB_BUSY = 0x2,
1173 PERF_PAPC_PASX_FIRST_VECTOR = 0x2,
1328 SC_TPQZ_WINDOW_VALID = 0x2,
1727 RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x2,
1733 RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x2,
1739 RASTER_CONFIG_SE_PAIR_MAP_2 = 0x2,
1745 RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x2,
1751 RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x2,
1757 RASTER_CONFIG_SE_MAP_2 = 0x2,
1763 RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x2,
1769 RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x2,
1775 RASTER_CONFIG_SC_MAP_2 = 0x2,
1781 RASTER_CONFIG_PKR_XSEL2_2 = 0x2,
1787 RASTER_CONFIG_PKR_XSEL_2 = 0x2,
1793 RASTER_CONFIG_PKR_YSEL_2 = 0x2,
1799 RASTER_CONFIG_PKR_MAP_2 = 0x2,
1813 RASTER_CONFIG_RB_XSEL2_2 = 0x2,
1819 RASTER_CONFIG_RB_MAP_2 = 0x2,
1825 CSDATA_TYPE_EVENT = 0x2,
1828 #define CSDATA_TYPE_WIDTH 0x2
1834 CENTROIDS_AND_CENTERS = 0x2,
1840 SPI_FOG_EXP2 = 0x2,
1846 SPI_PNT_SPRITE_SEL_S = 0x2,
1853 SPI_PERF_VS_FIRST_WAVE = 0x2,
2052 SPI_SHADER_2COMP = 0x2,
2059 SPI_SHADER_32_GR = 0x2,
2071 PROG_SEQ = 0x2,
2082 SQ_TEX_CLAMP_LAST_TEXEL = 0x2,
2092 SQ_TEX_XY_FILTER_ANISO_POINT = 0x2,
2098 SQ_TEX_Z_FILTER_LINEAR = 0x2,
2103 SQ_TEX_MIP_FILTER_LINEAR = 0x2,
2109 SQ_TEX_ANISO_RATIO_4 = 0x2,
2116 SQ_TEX_DEPTH_COMPARE_EQUAL = 0x2,
2126 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x2,
2132 SQ_RSRC_BUF_RSVD_2 = 0x2,
2138 SQ_RSRC_IMG_RSVD_2 = 0x2,
2156 SQ_RSRC_FLAT_RSVD_2 = 0x2,
2162 SQ_IMG_FILTER_MODE_MAX = 0x2,
2167 SQ_SEL_RESERVED_0 = 0x2,
2177 SQ_WAVE_TYPE_GS = 0x2,
2187 SQ_THREAD_TRACE_TOKEN_REG = 0x2,
2205 SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x2,
2215 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x2,
2242 SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x2,
2260 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x2,
2265 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x2,
2274 SQ_THREAD_TRACE_ISSUE_INST = 0x2,
2280 SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x2,
2286 SQ_PERF_SEL_CYCLES = 0x2,
2580 SQ_CAC_POWER_VALU1 = 0x2,
2591 SQ_IND_CMD_CMD_SAVECTX = 0x2,
2600 SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x2,
2607 SQ_EDC_INFO_SOURCE_SGPR = 0x2,
2616 SQ_ROUND_MINUS_INFINITY = 0x2,
2622 SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x2,
2627 SQ_EXPORT_RAT_INST_STORE_RAW = 0x2,
2671 SQ_IBUF_IB_INI_WAIT_DRET = 0x2,
2681 SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x2,
2691 SQ_WAVE_IB_ECC_ERR_HALT = 0x2,
2697 SH_MEM_ADDRESS_MODE_HSA64 = 0x2,
2703 SH_MEM_ALIGNMENT_MODE_STRICT = 0x2,
2741 #define SQ_EX_MODE_EXCP_DIV0 0x2
2769 #define SQ_ENC_SOP2_FIELD 0x2
2808 #define SQ_SENDMSG_STREAMID_SIZE 0x2
2821 #define SQ_SENDMSG_GSOP_SIZE 0x2
2855 #define SQ_S_CMOV_B32 0x2
2907 #define SQ_S_CMPK_EQ_I32 0x2
2951 #define SQ_CNT3 0x2
2955 #define SQ_S_LOAD_DWORDX4 0x2
3005 #define SQ_EQ 0x2
3218 #define SQ_L2 0x2
3235 #define SQ_SDWA_UNUSED_PRESERVE 0x2
3238 #define SQ_EQ 0x2
3336 #define SQ_DS_RSUB_U32 0x2
3481 #define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2
3543 #define SQ_OMOD_M4 0x2
3602 #define SQ_GS_OP_EMIT 0x2
3606 #define SQ_IMAGE_LOAD_PCK 0x2
3699 #define SQ_SDWA_BYTE_2 0x2
3708 #define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2
3724 #define SQ_CHAN_Z 0x2
3728 #define SQ_V_READFIRSTLANE_B32 0x2
3810 #define SQ_V_INTERP_MOV_F32 0x2
3813 #define SQ_S_BRANCH 0x2
3847 #define SQ_PARAM_P0 0x2
3851 #define SQ_V_SUB_F32 0x2
3943 #define SQ_S_CMP_GT_I32 0x2
4044 #define SQ_SYSMSG_OP_REG_RD 0x2
4048 #define SQ_HW_REG_STATUS 0x2
4063 #define SQ_R2 0x2
4079 #define SQ_S_ADD_I32 0x2
4122 #define SQ_MSG_GS 0x2
4129 TEX_BorderColor_OpaqueWhite = 0x2,
4135 TEX_ChromaKey_Blend = 0x2,
4141 TEX_Clamp_ClampToLast = 0x2,
4155 TEX_DepthCompareFunction_Equal = 0x2,
4165 TEX_Dim_3D = 0x2,
4175 TEX_FormatComp_UnsignedBiased = 0x2,
4181 TEX_MaxAnisoRatio_4to1 = 0x2,
4191 TEX_MipFilter_Linear = 0x2,
4197 TEX_RequestSize_128B = 0x2,
4207 TEX_XYFilter_AnisoPoint = 0x2,
4213 TEX_ZFilter_Linear = 0x2,
4223 VTX_FetchType_NoIndexOffset = 0x2,
4237 TVX_FMT_4_4 = 0x2,
4303 TVX_DstSel_Z = 0x2,
4313 TVX_EndianSwap_8in32 = 0x2,
4319 TVX_Inst_RESERVED_2 = 0x2,
4353 TVX_NumFormatAll_Scaled = 0x2,
4359 TVX_SrcSel_Z = 0x2,
4371 TVX_Type_ValidTextureResource = 0x2,
4382 TC_OP_ATOMIC_FMIN_RTN_32 = 0x2,
4518 TC_NACK_PROTECTION_FAULT = 0x2,
4524 TCC_PERF_SEL_BUSY = 0x2,
4762 TCA_PERF_SEL_BUSY = 0x2,
4799 TA_TC_ADDR_MODE_COMP1 = 0x2,
4808 TA_PERF_SEL_sh_fifo_cmd_busy = 0x2,
4929 TD_PERF_SEL_input_busy = 0x2,
4986 TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x2,
5171 TCP_CACHE_POLICY_HIT_LRU = 0x2,
5181 TCP_WATCH_MODE_ATOMIC = 0x2,
5187 TCP_DSM_SEL1 = 0x2,
5196 VGT_OUT_TRI = 0x2,
5213 DI_PT_LINELIST = 0x2,
5244 DI_SRC_SEL_AUTO_INDEX = 0x2,
5254 DI_INDEX_SIZE_8_BIT = 0x2,
5259 SAMPLE_STREAMOUTSTATS2 = 0x2,
5322 VGT_DMA_SWAP_32_BIT = 0x2,
5328 VGT_INDEX_8 = 0x2,
5333 VGT_DMA_BUF_SETUP = 0x2,
5339 VGT_OUTPATH_PASSTHRU = 0x2,
5346 VGT_GRP_3D_TRI = 0x2,
5366 VGT_GRP_FAN = 0x2,
5373 VGT_GRP_UINT_16 = 0x2,
5384 GS_SCENARIO_B = 0x2,
5392 GS_CUT_256 = 0x2,
5398 TRISTRIP = 0x2,
5403 VC_AND_TC = 0x2,
5408 TESS_QUAD = 0x2,
5413 PART_FRAC_ODD = 0x2,
5419 OUTPUT_TRIANGLE_CW = 0x2,
5429 DONUTS = 0x2,
5434 CS_STAGE_ON = 0x2,
5444 ES_STAGE_REAL = 0x2,
5454 VS_STAGE_COPY_SHADER = 0x2,
5460 vgt_perf_VGT_SPI_ESVERT_EOV = 0x2,
5608 ia_perf_RESERVED1 = 0x2,
5634 wd_perf_RBIU_DR_FIFO_STALLED = 0x2,
5673 WD_IA_DRAW_TYPE_EVENT_INIT = 0x2,
5683 WD_IA_DRAW_SOURCE_AUTO = 0x2,
5686 #define GSTHREADID_SIZE 0x2
5690 ENDIAN_8IN32 = 0x2,
5696 ARRAY_1D_TILED_THIN1 = 0x2,
5714 CONFIG_4_PIPE = 0x2,
5728 CONFIG_4KB_ROW = 0x2,
5738 CONFIG_512B_SWAPS = 0x2,
5744 CONFIG_4KB_SPLIT = 0x2,
5750 ADDR_CONFIG_4_PIPE = 0x2,
5760 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
5774 ADDR_CONFIG_4_GPU = 0x2,
5779 ADDR_CONFIG_GPU_TILE_64 = 0x2,
5785 ADDR_CONFIG_4KB_ROW = 0x2,
5794 DBG_CLIENT_BLKID_scf2 = 0x2,
5954 DBG_BLOCK_ID_VMC = 0x2,
6188 DBG_BLOCK_ID_CG_BY2 = 0x2,
6306 DBG_BLOCK_ID_CSC_BY4 = 0x2,
6366 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
6397 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
6414 ABGR_TO_A_BG_G_RB = 0x2,
6420 REF_EQUAL = 0x2,
6434 DEPTH_X8_24 = 0x2,
6444 Z_24 = 0x2,
6454 CMASK_CLEAR_ALL = 0x2,
6472 EXPORT_32_GR = 0x2,
6482 EXPORT_4P_32BPC_GR = 0x2,
6490 COLOR_16 = 0x2,
6516 FMT_16 = 0x2,
6582 BUF_DATA_FORMAT_16 = 0x2,
6600 IMG_DATA_FORMAT_16 = 0x2,
6666 BUF_NUM_FORMAT_USCALED = 0x2,
6676 IMG_NUM_FORMAT_USCALED = 0x2,
6702 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
6709 ADDR_SURF_TILE_SPLIT_256B = 0x2,
6718 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
6724 ADDR_SURF_P2_RESERVED1 = 0x2,
6744 ADDR_SURF_8_BANK = 0x2,
6750 ADDR_SURF_BANK_WIDTH_4 = 0x2,
6756 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
6762 ADDR_SURF_BANK_WH_4 = 0x2,
6768 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
6774 GATCL1_TYPE_BYPASS = 0x2,
6783 MTYPE_CC = 0x2,
6789 PERFMON_COUNTER_MODE_MAX = 0x2,
6802 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
6819 ARRAY_3D = 0x2,
6837 FORCE_DEEP_SLEEP_REQUEST = 0x2,
6851 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
H A Dgfx_7_2_enum.h30 NUMBER_USCALED = 0x2,
40 SWAP_STD_REV = 0x2,
46 CB_ELIMINATE_FAST_CLEAR = 0x2,
58 EXPORT_2C_32BPC_GR = 0x2,
64 BLEND_SRC_COLOR = 0x2,
87 COMB_MIN_DST_SRC = 0x2,
94 FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x2,
104 CMASK_CLR00_F2 = 0x2,
122 CB_PERF_SEL_CORE_SCLK_VLD = 0x2,
350 CB_PERF_OP_FILTER_SEL_RESOLVE = 0x2,
362 RINGID2 = 0x2,
368 PIPE_ID2 = 0x2,
374 ME_ID2 = 0x2,
380 STRM_PERFMON_STATE_STOP_COUNTING = 0x2,
388 CP_PERFMON_STATE_STOP_COUNTING = 0x2,
396 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x2,
402 CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x2,
450 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x2,
469 CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x2,
493 CPF_TAG_RAM = 0x2,
498 #define SEM_FAILED 0x2
502 #define IQ_SCH_WAVE_MSG 0x2
507 #define IQ_INTR_TYPE_MQD 0x2
524 FORCE_DISABLE = 0x2,
534 RE_Z = 0x2,
540 ZPASS_PIXELS = 0x2,
545 FORCE_LATE_Z = 0x2,
551 FORCE_SUMM_MAXZ = 0x2,
557 FRAG_EQUAL = 0x2,
567 STENCIL_ONES = 0x2,
585 EXPORT_GREATER_THAN_Z = 0x2,
591 PSLC_ASAP = 0x2,
597 DB_PERF_SEL_SC_DB_tile_stalls = 0x2,
856 COUNTER_RING_1 = 0x2,
861 PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x2,
871 PIXEL_PIPE_STRIDE_128_BITS = 0x2,
877 GB_EDC_DED_MODE_INT_HALT = 0x2,
884 GRBM_PERF_SEL_GUI_ACTIVE = 0x2,
920 GRBM_SE0_PERF_SEL_CB_BUSY = 0x2,
937 GRBM_SE1_PERF_SEL_CB_BUSY = 0x2,
954 GRBM_SE2_PERF_SEL_CB_BUSY = 0x2,
971 GRBM_SE3_PERF_SEL_CB_BUSY = 0x2,
988 PERF_PAPC_PASX_FIRST_VECTOR = 0x2,
1143 SC_TPQZ_WINDOW_VALID = 0x2,
1540 RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x2,
1546 RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x2,
1552 RASTER_CONFIG_SE_PAIR_MAP_2 = 0x2,
1558 RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x2,
1564 RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x2,
1570 RASTER_CONFIG_SE_MAP_2 = 0x2,
1576 RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x2,
1582 RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x2,
1588 RASTER_CONFIG_SC_MAP_2 = 0x2,
1594 RASTER_CONFIG_PKR_XSEL2_2 = 0x2,
1600 RASTER_CONFIG_PKR_XSEL_2 = 0x2,
1606 RASTER_CONFIG_PKR_YSEL_2 = 0x2,
1612 RASTER_CONFIG_PKR_MAP_2 = 0x2,
1626 RASTER_CONFIG_RB_XSEL2_2 = 0x2,
1632 RASTER_CONFIG_RB_MAP_2 = 0x2,
1638 CSDATA_TYPE_EVENT = 0x2,
1641 #define CSDATA_TYPE_WIDTH 0x2
1647 CENTROIDS_AND_CENTERS = 0x2,
1653 SPI_FOG_EXP2 = 0x2,
1659 SPI_PNT_SPRITE_SEL_S = 0x2,
1666 SPI_PERF_VS_FIRST_WAVE = 0x2,
1854 SPI_SHADER_2COMP = 0x2,
1861 SPI_SHADER_32_GR = 0x2,
1873 PROG_SEQ = 0x2,
1884 SQ_TEX_CLAMP_LAST_TEXEL = 0x2,
1894 SQ_TEX_XY_FILTER_ANISO_POINT = 0x2,
1900 SQ_TEX_Z_FILTER_LINEAR = 0x2,
1905 SQ_TEX_MIP_FILTER_LINEAR = 0x2,
1910 SQ_TEX_ANISO_RATIO_4 = 0x2,
1917 SQ_TEX_DEPTH_COMPARE_EQUAL = 0x2,
1927 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x2,
1933 SQ_RSRC_BUF_RSVD_2 = 0x2,
1939 SQ_RSRC_IMG_RSVD_2 = 0x2,
1957 SQ_RSRC_FLAT_RSVD_2 = 0x2,
1963 SQ_IMG_FILTER_MODE_MAX = 0x2,
1968 SQ_SEL_RESERVED_0 = 0x2,
1978 SQ_WAVE_TYPE_GS = 0x2,
1988 SQ_THREAD_TRACE_TOKEN_REG = 0x2,
2006 SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x2,
2014 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x2,
2032 SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x2,
2046 SQ_THREAD_TRACE_MODE_RANDOM = 0x2,
2051 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x2,
2056 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x2,
2061 SQ_THREAD_TRACE_WAVE_MASK_1_2 = 0x2,
2071 SQ_THREAD_TRACE_ISSUE_INST = 0x2,
2077 SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x2,
2083 SQ_PERF_SEL_CYCLES = 0x2,
2338 SQ_CAC_POWER_VALU1 = 0x2,
2349 SQ_IND_CMD_CMD_RESUME = 0x2,
2357 SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x2,
2364 SQ_DED_INFO_SOURCE_SGPR = 0x2,
2373 SQ_ROUND_MINUS_INFINITY = 0x2,
2379 SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x2,
2384 SQ_EXPORT_RAT_INST_STORE_RAW = 0x2,
2428 SQ_IBUF_IB_INI_WAIT_DRET = 0x2,
2438 SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x2,
2448 SQ_WAVE_IB_ECC_ERR_HALT = 0x2,
2454 SH_MEM_ALIGNMENT_MODE_STRICT = 0x2,
2496 #define SQ_EX_MODE_EXCP_DIV0 0x2
2522 #define SQ_ENC_SOP2_FIELD 0x2
2560 #define SQ_SENDMSG_STREAMID_SIZE 0x2
2569 #define SQ_SENDMSG_GSOP_SIZE 0x2
2643 #define SQ_S_CMOVK_I32 0x2
2688 #define SQ_CNT3 0x2
2692 #define SQ_EQ 0x2
2708 #define SQ_V_CMP_EQ_F32 0x2
2905 #define SQ_EQ 0x2
3002 #define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2
3058 #define SQ_DS_RSUB_U32 0x2
3199 #define SQ_OMOD_M4 0x2
3204 #define SQ_GS_OP_EMIT 0x2
3208 #define SQ_IMAGE_LOAD_PCK 0x2
3304 #define SQ_DFMT_16 0x2
3319 #define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2
3327 #define SQ_CHAN_Z 0x2
3333 #define SQ_S_LOAD_DWORDX4 0x2
3346 #define SQ_V_READFIRSTLANE_B32 0x2
3412 #define SQ_NFMT_USCALED 0x2
3423 #define SQ_V_INTERP_MOV_F32 0x2
3426 #define SQ_S_BRANCH 0x2
3455 #define SQ_PARAM_P0 0x2
3461 #define SQ_V_WRITELANE_B32 0x2
3557 #define SQ_S_CMP_GT_I32 0x2
3632 #define SQ_SYSMSG_OP_REG_RD 0x2
3636 #define SQ_HW_REG_STATUS 0x2
3649 #define SQ_S_ADD_I32 0x2
3691 #define SQ_MSG_GS 0x2
3697 TEX_BorderColor_OpaqueWhite = 0x2,
3703 TEX_ChromaKey_Blend = 0x2,
3709 TEX_Clamp_ClampToLast = 0x2,
3723 TEX_DepthCompareFunction_Equal = 0x2,
3733 TEX_Dim_3D = 0x2,
3743 TEX_FormatComp_UnsignedBiased = 0x2,
3749 TEX_MaxAnisoRatio_4to1 = 0x2,
3759 TEX_MipFilter_Linear = 0x2,
3765 TEX_RequestSize_128B = 0x2,
3775 TEX_XYFilter_AnisoPoint = 0x2,
3781 TEX_ZFilter_Linear = 0x2,
3791 VTX_FetchType_NoIndexOffset = 0x2,
3805 TVX_FMT_4_4 = 0x2,
3871 TVX_DstSel_Z = 0x2,
3881 TVX_EndianSwap_8in32 = 0x2,
3887 TVX_Inst_RESERVED_2 = 0x2,
3921 TVX_NumFormatAll_Scaled = 0x2,
3927 TVX_SrcSel_Z = 0x2,
3939 TVX_Type_ValidTextureResource = 0x2,
3950 TC_OP_ATOMIC_FMIN_RTN_32 = 0x2,
4086 TC_NACK_PROTECTION_FAULT = 0x2,
4092 TCC_PERF_SEL_BUSY = 0x2,
4235 TCA_PERF_SEL_BUSY = 0x2,
4276 TCS_PERF_SEL_BUSY = 0x2,
4363 TA_TC_ADDR_MODE_COMP1 = 0x2,
4372 TA_PERF_SEL_sh_fifo_cmd_busy = 0x2,
4485 TD_PERF_SEL_output_busy = 0x2,
4542 TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x2,
4698 TCP_CACHE_POLICY_HIT_LRU = 0x2,
4708 TCP_WATCH_MODE_ATOMIC = 0x2,
4714 VGT_OUT_TRI = 0x2,
4731 DI_PT_LINELIST = 0x2,
4762 DI_SRC_SEL_AUTO_INDEX = 0x2,
4776 SAMPLE_STREAMOUTSTATS2 = 0x2,
4838 VGT_DMA_SWAP_32_BIT = 0x2,
4848 VGT_DMA_BUF_SETUP = 0x2,
4853 VGT_OUTPATH_PASSTHRU = 0x2,
4860 VGT_GRP_3D_TRI = 0x2,
4880 VGT_GRP_FAN = 0x2,
4887 VGT_GRP_UINT_16 = 0x2,
4898 GS_SCENARIO_B = 0x2,
4906 GS_CUT_256 = 0x2,
4912 TRISTRIP = 0x2,
4917 VC_AND_TC = 0x2,
4922 TESS_QUAD = 0x2,
4927 PART_FRAC_ODD = 0x2,
4933 OUTPUT_TRIANGLE_CW = 0x2,
4939 VGT_POLICY_BYPASS = 0x2,
4945 CS_STAGE_ON = 0x2,
4955 ES_STAGE_REAL = 0x2,
4965 VS_STAGE_COPY_SHADER = 0x2,
4971 vgt_perf_VGT_SPI_ESVERT_EOV = 0x2,
5113 ia_perf_MC_LAT_BIN_1 = 0x2,
5133 wd_perf_RBIU_DR_FIFO_STALLED = 0x2,
5145 WD_IA_DRAW_TYPE_EVENT_INIT = 0x2,
5152 #define GSTHREADID_SIZE 0x2
5156 ENDIAN_8IN32 = 0x2,
5162 ARRAY_1D_TILED_THIN1 = 0x2,
5180 CONFIG_4_PIPE = 0x2,
5194 CONFIG_4KB_ROW = 0x2,
5204 CONFIG_512B_SWAPS = 0x2,
5210 CONFIG_4KB_SPLIT = 0x2,
5216 ADDR_CONFIG_4_PIPE = 0x2,
5227 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
5241 ADDR_CONFIG_4_GPU = 0x2,
5246 ADDR_CONFIG_GPU_TILE_64 = 0x2,
5252 ADDR_CONFIG_4KB_ROW = 0x2,
5261 DBG_CLIENT_BLKID_dco0 = 0x2,
5412 DBG_BLOCK_ID_VMC = 0x2,
5646 DBG_BLOCK_ID_CG_BY2 = 0x2,
5764 DBG_BLOCK_ID_CSC_BY4 = 0x2,
5824 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
5855 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
5872 REF_EQUAL = 0x2,
5886 DEPTH_X8_24 = 0x2,
5896 Z_24 = 0x2,
5906 CMASK_CLEAR_ALL = 0x2,
5924 EXPORT_32_GR = 0x2,
5934 EXPORT_4P_32BPC_GR = 0x2,
5942 COLOR_16 = 0x2,
5968 FMT_16 = 0x2,
6034 BUF_DATA_FORMAT_16 = 0x2,
6052 IMG_DATA_FORMAT_16 = 0x2,
6118 BUF_NUM_FORMAT_USCALED = 0x2,
6128 IMG_NUM_FORMAT_USCALED = 0x2,
6154 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
6161 ADDR_SURF_TILE_SPLIT_256B = 0x2,
6170 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
6176 ADDR_SURF_P2_RESERVED1 = 0x2,
6196 ADDR_SURF_8_BANK = 0x2,
6202 ADDR_SURF_BANK_WIDTH_4 = 0x2,
6208 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
6214 ADDR_SURF_BANK_WH_4 = 0x2,
6220 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
6226 TCC_CACHE_POLICY_BYPASS = 0x2,
6231 PERFMON_COUNTER_MODE_MAX = 0x2,
6244 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
6261 ARRAY_3D = 0x2,
/linux-4.4.14/arch/sparc/lib/
H A DNG2memcpy.S88 #define FREG_FROB(x0, x1, x2, x3, x4, x5, x6, x7, x8) \
90 faligndata %x1, %x2, %f2; \
91 faligndata %x2, %x3, %f4; \
103 #define FREG_MOVE_3(x0, x1, x2) \
106 fsrc2 %x2, %f4;
107 #define FREG_MOVE_4(x0, x1, x2, x3) \
110 fsrc2 %x2, %f4; \
112 #define FREG_MOVE_5(x0, x1, x2, x3, x4) \
115 fsrc2 %x2, %f4; \
118 #define FREG_MOVE_6(x0, x1, x2, x3, x4, x5) \
121 fsrc2 %x2, %f4; \
125 #define FREG_MOVE_7(x0, x1, x2, x3, x4, x5, x6) \
128 fsrc2 %x2, %f4; \
133 #define FREG_MOVE_8(x0, x1, x2, x3, x4, x5, x6, x7) \
136 fsrc2 %x2, %f4; \
147 #define FREG_LOAD_3(base, x0, x1, x2) \
150 EX_LD_FP(LOAD(ldd, base + 0x10, %x2));
151 #define FREG_LOAD_4(base, x0, x1, x2, x3) \
154 EX_LD_FP(LOAD(ldd, base + 0x10, %x2)); \
156 #define FREG_LOAD_5(base, x0, x1, x2, x3, x4) \
159 EX_LD_FP(LOAD(ldd, base + 0x10, %x2)); \
162 #define FREG_LOAD_6(base, x0, x1, x2, x3, x4, x5) \
165 EX_LD_FP(LOAD(ldd, base + 0x10, %x2)); \
169 #define FREG_LOAD_7(base, x0, x1, x2, x3, x4, x5, x6) \
172 EX_LD_FP(LOAD(ldd, base + 0x10, %x2)); \
/linux-4.4.14/drivers/phy/
H A Dphy-berlin-usb.c56 #define TX_VDD15_16 (0x2 << 4)
60 #define TX_VDD12_12 (0x2 << 6)
70 #define IMP_CAL_FS_HS_DLY_2 (0x2 << 6)
80 #define ACK_LENGTH_16_CL (0x2 << 2)
84 #define SQ_LENGTH_9 (0x2 << 4)
88 #define DISCON_THRESHOLD_280 (0x2 << 6)
94 #define INTPL_CUR_30 (0x2 << 14)
132 DISCON_THRESHOLD_260 | SQ_THRESHOLD(0xa) | LPF_COEF(0x2) | phy_berlin_usb_power_on()
140 EXT_FS_RCAL_DIV(0x2), priv->base + USB_PHY_TX_CTRL0); phy_berlin_usb_power_on()
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h78 #define IH_RB_RPTR__OFFSET__SHIFT 0x2
82 #define IH_RB_WPTR__OFFSET__SHIFT 0x2
90 #define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
110 #define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
119 #define IH_STATUS__INPUT_IDLE_MASK 0x2
122 #define IH_STATUS__RB_IDLE__SHIFT 0x2
141 #define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
144 #define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
164 #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
178 #define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
215 #define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
218 #define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
243 #define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
279 #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
282 #define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2
298 #define SRBM_GFX_CNTL__MEID__SHIFT 0x2
307 #define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
310 #define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
345 #define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
348 #define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2
387 #define SRBM_STATUS3__MCC1_BUSY_MASK 0x2
390 #define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2
419 #define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
422 #define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2
527 #define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
530 #define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
547 #define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY_MASK 0x2
550 #define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
612 #define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
641 #define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2
644 #define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2
651 #define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2
655 #define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2
659 #define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2
663 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2
666 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT 0x2
712 #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2
894 #define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2
936 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
955 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
958 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
984 #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
986 #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
991 #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
994 #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
1049 #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
1052 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
1075 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
1078 #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
1091 #define SDMA0_F32_CNTL__STEP_MASK 0x2
1094 #define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
1115 #define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
1118 #define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
1151 #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
1154 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
1166 #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
1190 #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
1192 #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
1195 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1204 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1208 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1218 #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
1220 #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
1231 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
1234 #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
1268 #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
1298 #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
1300 #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
1303 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1312 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1316 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1326 #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
1328 #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
1339 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
1342 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
1376 #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
1382 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
1412 #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
1414 #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
1417 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1426 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1430 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1440 #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
1442 #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
1453 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
1456 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
1490 #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
1496 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
1534 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
1553 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
1556 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
1582 #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
1584 #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
1589 #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
1592 #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
1647 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
1650 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
1673 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
1676 #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
1689 #define SDMA1_F32_CNTL__STEP_MASK 0x2
1692 #define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
1711 #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
1714 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
1726 #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
1750 #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
1752 #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
1755 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1764 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1768 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1778 #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
1780 #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
1791 #define SDMA1_GFX_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
1794 #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
1828 #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
1858 #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
1860 #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
1863 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1872 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1876 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1886 #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
1888 #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
1899 #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
1902 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
1936 #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
1942 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
1972 #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
1974 #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
1977 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1986 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1990 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
2000 #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
2002 #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
2013 #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
2016 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
2050 #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
2056 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
2127 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
2131 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
2217 #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
2220 #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
2235 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
2238 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
H A Doss_3_0_1_enum.h56 IH_PERF_SEL_INPUT_IDLE = 0x2,
98 SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x2,
303 GRBM_GFX_INDEX_SDMA1 = 0x2,
320 SRBM_GFX_CNTL_SDMA1 = 0x2,
337 SDMA_PERF_SEL_REG_IDLE = 0x2,
426 DBG_BLOCK_ID_VMC = 0x2,
683 DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
805 DBG_BLOCK_ID_CSC_BY4 = 0x2,
867 DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
899 DBG_BLOCK_ID_SXM_BY16 = 0x2,
916 ENDIAN_8IN32 = 0x2,
922 ARRAY_1D_TILED_THIN1 = 0x2,
940 CONFIG_4_PIPE = 0x2,
954 CONFIG_4KB_ROW = 0x2,
964 CONFIG_512B_SWAPS = 0x2,
970 CONFIG_4KB_SPLIT = 0x2,
976 ADDR_CONFIG_4_PIPE = 0x2,
986 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
1000 ADDR_CONFIG_4_GPU = 0x2,
1005 ADDR_CONFIG_GPU_TILE_64 = 0x2,
1011 ADDR_CONFIG_4KB_ROW = 0x2,
1020 ABGR_TO_A_BG_G_RB = 0x2,
1026 REF_EQUAL = 0x2,
1040 DEPTH_X8_24 = 0x2,
1050 Z_24 = 0x2,
1060 CMASK_CLEAR_ALL = 0x2,
1078 EXPORT_32_GR = 0x2,
1088 EXPORT_4P_32BPC_GR = 0x2,
1096 COLOR_16 = 0x2,
1122 FMT_16 = 0x2,
1188 BUF_DATA_FORMAT_16 = 0x2,
1206 IMG_DATA_FORMAT_16 = 0x2,
1272 BUF_NUM_FORMAT_USCALED = 0x2,
1282 IMG_NUM_FORMAT_USCALED = 0x2,
1308 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1315 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1324 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1330 ADDR_SURF_P2_RESERVED1 = 0x2,
1350 ADDR_SURF_8_BANK = 0x2,
1356 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1362 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1368 ADDR_SURF_BANK_WH_4 = 0x2,
1374 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1380 GATCL1_TYPE_BYPASS = 0x2,
1389 MTYPE_CC = 0x2,
1395 PERFMON_COUNTER_MODE_MAX = 0x2,
1408 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1425 ARRAY_3D = 0x2,
1443 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1457 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
H A Doss_3_0_enum.h56 IH_PERF_SEL_INPUT_IDLE = 0x2,
238 GRBM_GFX_INDEX_SDMA1 = 0x2,
255 SRBM_GFX_CNTL_SDMA1 = 0x2,
272 SDMA_PERF_SEL_REG_IDLE = 0x2,
329 ENDIAN_8IN32 = 0x2,
335 ARRAY_1D_TILED_THIN1 = 0x2,
353 CONFIG_4_PIPE = 0x2,
367 CONFIG_4KB_ROW = 0x2,
377 CONFIG_512B_SWAPS = 0x2,
383 CONFIG_4KB_SPLIT = 0x2,
389 ADDR_CONFIG_4_PIPE = 0x2,
399 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
413 ADDR_CONFIG_4_GPU = 0x2,
418 ADDR_CONFIG_GPU_TILE_64 = 0x2,
424 ADDR_CONFIG_4KB_ROW = 0x2,
433 DBG_CLIENT_BLKID_scf2 = 0x2,
593 DBG_BLOCK_ID_VMC = 0x2,
827 DBG_BLOCK_ID_CG_BY2 = 0x2,
945 DBG_BLOCK_ID_CSC_BY4 = 0x2,
1005 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
1036 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
1053 ABGR_TO_A_BG_G_RB = 0x2,
1059 REF_EQUAL = 0x2,
1073 DEPTH_X8_24 = 0x2,
1083 Z_24 = 0x2,
1093 CMASK_CLEAR_ALL = 0x2,
1111 EXPORT_32_GR = 0x2,
1121 EXPORT_4P_32BPC_GR = 0x2,
1129 COLOR_16 = 0x2,
1155 FMT_16 = 0x2,
1221 BUF_DATA_FORMAT_16 = 0x2,
1239 IMG_DATA_FORMAT_16 = 0x2,
1305 BUF_NUM_FORMAT_USCALED = 0x2,
1315 IMG_NUM_FORMAT_USCALED = 0x2,
1341 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1348 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1357 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1363 ADDR_SURF_P2_RESERVED1 = 0x2,
1383 ADDR_SURF_8_BANK = 0x2,
1389 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1395 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1401 ADDR_SURF_BANK_WH_4 = 0x2,
1407 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1413 GATCL1_TYPE_BYPASS = 0x2,
1422 MTYPE_CC = 0x2,
1428 PERFMON_COUNTER_MODE_MAX = 0x2,
1441 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1458 ARRAY_3D = 0x2,
1476 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1490 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
H A Doss_3_0_1_sh_mask.h78 #define IH_RB_RPTR__OFFSET__SHIFT 0x2
82 #define IH_RB_WPTR__OFFSET__SHIFT 0x2
90 #define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
110 #define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
119 #define IH_STATUS__INPUT_IDLE_MASK 0x2
122 #define IH_STATUS__RB_IDLE__SHIFT 0x2
141 #define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
144 #define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
164 #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
178 #define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
183 #define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
186 #define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
209 #define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
212 #define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
241 #define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
277 #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
280 #define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2
306 #define SRBM_GFX_CNTL__MEID__SHIFT 0x2
315 #define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
318 #define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
353 #define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
356 #define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2
395 #define SRBM_STATUS3__MCC1_BUSY_MASK 0x2
398 #define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2
427 #define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
430 #define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2
537 #define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
540 #define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
559 #define SRBM_DEBUG_SNAPSHOT__GIONB_RDY_MASK 0x2
562 #define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
624 #define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
653 #define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2
656 #define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2
663 #define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2
667 #define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2
671 #define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2
675 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2
678 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VP8__SHIFT 0x2
724 #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2
898 #define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2
947 #define SDMA0_CNTL__ATC_L1_ENABLE_MASK 0x2
950 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
973 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
976 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
1002 #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
1004 #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
1009 #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
1012 #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
1067 #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
1070 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
1095 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
1098 #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
1111 #define SDMA0_F32_CNTL__STEP_MASK 0x2
1114 #define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
1135 #define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
1138 #define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
1171 #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
1174 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
1186 #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
1192 #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
1239 #define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2
1242 #define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
1289 #define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2
1292 #define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
1339 #define SDMA0_ATCL1_INV0__RD_TIMEOUT_MASK 0x2
1342 #define SDMA0_ATCL1_INV0__WR_TIMEOUT__SHIFT 0x2
1397 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT_MASK 0x2
1400 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x2
1405 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x2
1408 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2
1469 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x2
1472 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2
1491 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x2
1494 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2
1551 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO_MASK 0x2
1554 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI__SHIFT 0x2
1600 #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
1602 #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
1605 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1608 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
1616 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1620 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1630 #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
1632 #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
1644 #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
1669 #define SDMA0_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2
1684 #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
1690 #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
1719 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2
1746 #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
1748 #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
1751 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1754 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
1762 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1766 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1776 #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
1778 #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
1790 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
1811 #define SDMA0_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2
1826 #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
1832 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
1861 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2
1888 #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
1890 #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
1893 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1896 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
1904 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1908 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1918 #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
1920 #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
1932 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
1953 #define SDMA0_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2
1968 #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
1974 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
2003 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2
2045 #define SDMA1_CNTL__ATC_L1_ENABLE_MASK 0x2
2048 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
2071 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
2074 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
2100 #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
2102 #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
2107 #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
2110 #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
2165 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
2168 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
2193 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
2196 #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
2209 #define SDMA1_F32_CNTL__STEP_MASK 0x2
2212 #define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
2231 #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
2234 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
2246 #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2
2252 #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
2299 #define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2
2302 #define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
2349 #define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2
2352 #define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
2399 #define SDMA1_ATCL1_INV0__RD_TIMEOUT_MASK 0x2
2402 #define SDMA1_ATCL1_INV0__WR_TIMEOUT__SHIFT 0x2
2457 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT_MASK 0x2
2460 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x2
2465 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x2
2468 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2
2533 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x2
2536 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2
2555 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x2
2558 #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x2
2609 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO_MASK 0x2
2612 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI__SHIFT 0x2
2658 #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
2660 #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
2663 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
2666 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
2674 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
2678 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
2688 #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
2690 #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
2702 #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
2727 #define SDMA1_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2
2742 #define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
2748 #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
2777 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2
2804 #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
2806 #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
2809 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
2812 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
2820 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
2824 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
2834 #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
2836 #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
2848 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
2869 #define SDMA1_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2
2884 #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
2890 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
2919 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2
2946 #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
2948 #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
2951 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
2954 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
2962 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
2966 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
2976 #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
2978 #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
2990 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
3011 #define SDMA1_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2
3026 #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
3032 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
3061 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2
3129 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
3133 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
3223 #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
3226 #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
3245 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
3248 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
H A Doss_2_4_enum.h56 IH_PERF_SEL_INPUT_IDLE = 0x2,
124 GRBM_GFX_INDEX_SDMA1 = 0x2,
141 SRBM_GFX_CNTL_SDMA1 = 0x2,
158 SDMA_PERF_SEL_REG_IDLE = 0x2,
215 ENDIAN_8IN32 = 0x2,
221 ARRAY_1D_TILED_THIN1 = 0x2,
239 CONFIG_4_PIPE = 0x2,
253 CONFIG_4KB_ROW = 0x2,
263 CONFIG_512B_SWAPS = 0x2,
269 CONFIG_4KB_SPLIT = 0x2,
275 ADDR_CONFIG_4_PIPE = 0x2,
285 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
299 ADDR_CONFIG_4_GPU = 0x2,
304 ADDR_CONFIG_GPU_TILE_64 = 0x2,
310 ADDR_CONFIG_4KB_ROW = 0x2,
319 DBG_CLIENT_BLKID_uvdu_0 = 0x2,
459 DBG_BLOCK_ID_VMC = 0x2,
693 DBG_BLOCK_ID_CG_BY2 = 0x2,
811 DBG_BLOCK_ID_CSC_BY4 = 0x2,
871 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
902 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
919 ABGR_TO_A_BG_G_RB = 0x2,
925 REF_EQUAL = 0x2,
939 DEPTH_X8_24 = 0x2,
949 Z_24 = 0x2,
959 CMASK_CLEAR_ALL = 0x2,
977 EXPORT_32_GR = 0x2,
987 EXPORT_4P_32BPC_GR = 0x2,
995 COLOR_16 = 0x2,
1021 FMT_16 = 0x2,
1087 BUF_DATA_FORMAT_16 = 0x2,
1105 IMG_DATA_FORMAT_16 = 0x2,
1171 BUF_NUM_FORMAT_USCALED = 0x2,
1181 IMG_NUM_FORMAT_USCALED = 0x2,
1207 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1214 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1223 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1229 ADDR_SURF_P2_RESERVED1 = 0x2,
1249 ADDR_SURF_8_BANK = 0x2,
1255 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1261 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1267 ADDR_SURF_BANK_WH_4 = 0x2,
1273 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1279 GATCL1_TYPE_BYPASS = 0x2,
1288 MTYPE_CC = 0x2,
1294 PERFMON_COUNTER_MODE_MAX = 0x2,
1307 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1324 ARRAY_3D = 0x2,
H A Doss_3_0_sh_mask.h80 #define IH_RB_RPTR__OFFSET__SHIFT 0x2
84 #define IH_RB_WPTR__OFFSET__SHIFT 0x2
92 #define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
106 #define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
115 #define IH_STATUS__INPUT_IDLE_MASK 0x2
118 #define IH_STATUS__RB_IDLE__SHIFT 0x2
139 #define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
142 #define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
155 #define IH_DEBUG__WPTR_OVERFLOW_ENABLE_MASK 0x2
158 #define IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE__SHIFT 0x2
167 #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x2
170 #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
211 #define IH_RESET_INCOMPLETE_INT_CNTL__DC_MASK 0x2
257 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC_MASK 0x2
300 #define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
335 #define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
338 #define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
365 #define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
401 #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
404 #define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2
420 #define SRBM_GFX_CNTL__MEID__SHIFT 0x2
429 #define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
432 #define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
469 #define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
472 #define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2
511 #define SRBM_STATUS3__MCC1_BUSY_MASK 0x2
514 #define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2
543 #define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
546 #define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2
615 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU_MASK 0x2
618 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_DC__SHIFT 0x2
679 #define SRBM_CREDIT_RESET__CREDIT_RESET_SMU_MASK 0x2
682 #define SRBM_CREDIT_RESET__CREDIT_RESET_DC__SHIFT 0x2
787 #define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
790 #define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
809 #define SRBM_DEBUG_SNAPSHOT__GIONB_RDY_MASK 0x2
812 #define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
874 #define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
903 #define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2
906 #define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2
913 #define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2
917 #define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2
921 #define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2
925 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2
928 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT 0x2
974 #define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2
1160 #define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2
1453 #define SDMA0_CNTL__ATC_L1_ENABLE_MASK 0x2
1456 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
1479 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
1482 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
1508 #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
1510 #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
1515 #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
1518 #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
1573 #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
1576 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
1601 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
1604 #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
1617 #define SDMA0_F32_CNTL__STEP_MASK 0x2
1620 #define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
1641 #define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
1644 #define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
1677 #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
1680 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
1684 #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
1690 #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
1731 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT_MASK 0x2
1734 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x2
1739 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x2
1742 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2
1803 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x2
1806 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2
1819 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x2
1822 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2
1879 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO_MASK 0x2
1882 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI__SHIFT 0x2
1922 #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
1924 #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
1927 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1930 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
1938 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1942 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1952 #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
1954 #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
1966 #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
1991 #define SDMA0_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2
2006 #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
2012 #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
2035 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2
2062 #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
2064 #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
2067 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
2070 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
2078 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
2082 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
2092 #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
2094 #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
2106 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
2127 #define SDMA0_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2
2142 #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
2148 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
2171 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2
2198 #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
2200 #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
2203 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
2206 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
2214 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
2218 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
2228 #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
2230 #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
2242 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
2263 #define SDMA0_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2
2278 #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
2284 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
2307 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2
2349 #define SDMA1_CNTL__ATC_L1_ENABLE_MASK 0x2
2352 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
2375 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
2378 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
2404 #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
2406 #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
2411 #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
2414 #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
2469 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
2472 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
2497 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
2500 #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
2513 #define SDMA1_F32_CNTL__STEP_MASK 0x2
2516 #define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
2535 #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
2538 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
2542 #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2
2548 #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
2589 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT_MASK 0x2
2592 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x2
2597 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x2
2600 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2
2665 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x2
2668 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2
2681 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x2
2684 #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x2
2735 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO_MASK 0x2
2738 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI__SHIFT 0x2
2778 #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
2780 #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
2783 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
2786 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
2794 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
2798 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
2808 #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
2810 #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
2822 #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
2847 #define SDMA1_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2
2862 #define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
2868 #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
2891 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2
2918 #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
2920 #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
2923 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
2926 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
2934 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
2938 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
2948 #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
2950 #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
2962 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
2983 #define SDMA1_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2
2998 #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
3004 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
3027 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2
3054 #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
3056 #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
3059 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
3062 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
3070 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
3074 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
3084 #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
3086 #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
3098 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
3119 #define SDMA1_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2
3134 #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
3140 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
3163 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2
3231 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
3235 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
3325 #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
3328 #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
3347 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
3350 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
H A Doss_2_0_sh_mask.h78 #define IH_RB_RPTR__OFFSET__SHIFT 0x2
82 #define IH_RB_WPTR__OFFSET__SHIFT 0x2
86 #define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
108 #define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
117 #define IH_STATUS__INPUT_IDLE_MASK 0x2
120 #define IH_STATUS__RB_IDLE__SHIFT 0x2
139 #define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
142 #define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
166 #define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
203 #define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
206 #define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
229 #define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
257 #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
268 #define SRBM_GFX_CNTL__MEID__SHIFT 0x2
275 #define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
278 #define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
293 #define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
296 #define SRBM_STATUS__SAM_RQ_PENDING__SHIFT 0x2
335 #define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
425 #define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
428 #define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
443 #define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY_MASK 0x2
446 #define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
502 #define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
863 #define SDMA0_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK 0x2
866 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
904 #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
906 #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
911 #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
914 #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
965 #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
968 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
989 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
992 #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
1005 #define SDMA0_F32_CNTL__STEP_MASK 0x2
1025 #define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
1028 #define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
1061 #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
1064 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
1086 #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
1088 #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
1091 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1100 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1104 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1114 #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
1116 #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
1128 #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
1178 #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
1180 #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
1183 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1192 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1196 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1206 #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
1208 #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
1220 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
1250 #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
1276 #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
1278 #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
1281 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1290 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1294 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1304 #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
1306 #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
1318 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
1348 #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
1381 #define SDMA1_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK 0x2
1384 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
1422 #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
1424 #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
1429 #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
1432 #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
1483 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
1486 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
1507 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
1510 #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
1523 #define SDMA1_F32_CNTL__STEP_MASK 0x2
1541 #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
1544 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
1566 #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
1568 #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
1571 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1580 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1584 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1594 #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
1596 #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
1608 #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
1658 #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
1660 #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
1663 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1672 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1676 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1686 #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
1688 #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
1700 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
1730 #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
1756 #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
1758 #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
1761 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1770 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1774 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1784 #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
1786 #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
1798 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
1828 #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
2059 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
2063 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
2149 #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
2152 #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
2167 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
2170 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
/linux-4.4.14/arch/arm/mach-omap2/
H A Dcm-regbits-44xx.h33 #define OMAP4430_CLKSEL_0_1_WIDTH 0x2
35 #define OMAP4430_CLKSEL_24_25_WIDTH 0x2
45 #define OMAP4430_CLKSEL_FCLK_WIDTH 0x2
53 #define OMAP4430_CLKSEL_OPP_WIDTH 0x2
136 #define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2
138 #define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2
H A Dcm-regbits-54xx.h41 #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2
43 #define OMAP54XX_CLKSEL_OPP_WIDTH 0x2
45 #define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2
H A Dclock.h49 #define CORE_CLK_SRC_DPLL_X2 0x2
53 #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
/linux-4.4.14/drivers/media/dvb-frontends/drx39xyj/
H A Ddrxj_map.h62 #define ATV_COMM_EXEC_HOLD 0x2
108 #define ATV_TOP_COMM_EXEC_HOLD 0x2
129 #define ATV_TOP_COMM_MB_OBS__M 0x2
176 #define ATV_TOP_COMM_INT_STA_OVM_STA__M 0x2
196 #define ATV_TOP_COMM_INT_MSK_OVM_MSK__M 0x2
216 #define ATV_TOP_COMM_INT_STM_OVM_STM__M 0x2
380 #define ATV_TOP_STD_VID_POL__M 0x2
383 #define ATV_TOP_STD_VID_POL_POS 0x2
440 #define ATV_TOP_AF_SIF_ATT_M6DB 0x2
457 #define ATV_TOP_STDBY_CVBS_STDBY__M 0x2
460 #define ATV_TOP_STDBY_CVBS_STDBY_A1_STANDBY 0x2
461 #define ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE 0x2
499 #define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__M 0x2
502 #define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_SIGNED 0x2
531 #define ATV_AFT_COMM_EXEC_HOLD 0x2
571 #define AUD_TOP_COMM_MB_OBS__M 0x2
574 #define AUD_TOP_COMM_MB_OBS_OBS_ON 0x2
627 #define AUD_TOP_TR_CTR_FIFO_EMPTY__M 0x2
630 #define AUD_TOP_TR_CTR_FIFO_EMPTY_EMPTY 0x2
685 #define AUD_DEM_WR_MODUS_MOD_STATINTERR__M 0x2
688 #define AUD_DEM_WR_MODUS_MOD_STATINTERR_ENABLE 0x2
758 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA 0x2
782 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM 0x2
811 #define AUD_DEM_RD_STATUS_STAT_CARR_A__M 0x2
814 #define AUD_DEM_RD_STATUS_STAT_CARR_A_NOT_DETECTED 0x2
1053 #define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M 0x2
1056 #define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY 0x2
1100 #define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC 0x2
1248 #define AUD_DEM_RD_NIC_CIB_CIB1__M 0x2
1275 #define AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX 0x2
1370 #define FEC_COMM_EXEC_HOLD 0x2
1386 #define FEC_COMM_INT_REQ_RS_REQ__M 0x2
1412 #define FEC_TOP_COMM_EXEC_HOLD 0x2
1420 #define FEC_TOP_ANNEX_C 0x2
1429 #define FEC_DI_COMM_EXEC_HOLD 0x2
1443 #define FEC_DI_COMM_MB_OBS__M 0x2
1446 #define FEC_DI_COMM_MB_OBS_ON 0x2
1464 #define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2
1477 #define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2
1490 #define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2
1509 #define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2
1543 #define FEC_RS_COMM_EXEC_HOLD 0x2
1557 #define FEC_RS_COMM_MB_OBS__M 0x2
1560 #define FEC_RS_COMM_MB_OBS_ON 0x2
1578 #define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2
1591 #define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2
1604 #define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2
1707 #define FEC_OC_COMM_EXEC_HOLD 0x2
1721 #define FEC_OC_COMM_MB_OBS__M 0x2
1724 #define FEC_OC_COMM_MB_OBS_ON 0x2
1742 #define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2
1785 #define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2
1822 #define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2
1886 #define FEC_OC_MODE_TRANSPARENT__M 0x2
1911 #define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2
1930 #define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2
1984 #define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2
1990 #define FEC_OC_FCT_USAGE__PRE 0x2
1995 #define FEC_OC_FCT_USAGE_USAGE__PRE 0x2
2359 #define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2
2424 #define FEC_OC_IPR_INVERT_MD1__M 0x2
2489 #define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2
2624 #define IQM_COMM_EXEC_HOLD 0x2
2642 #define IQM_COMM_INT_REQ_CF_REQ__M 0x2
2664 #define IQM_FS_COMM_EXEC_HOLD 0x2
2678 #define IQM_FS_COMM_MB_OBS__M 0x2
2681 #define IQM_FS_COMM_MB_OBS_OBS_ON 0x2
2706 #define IQM_FS_ADJ_SEL_VSB 0x2
2714 #define IQM_FD_COMM_EXEC_HOLD 0x2
2728 #define IQM_FD_COMM_MB_OBS__M 0x2
2731 #define IQM_FD_COMM_MB_OBS_OBS_ON 0x2
2739 #define IQM_RC_COMM_EXEC_HOLD 0x2
2753 #define IQM_RC_COMM_MB_OBS__M 0x2
2756 #define IQM_RC_COMM_MB_OBS_OBS_ON 0x2
2781 #define IQM_RC_ADJ_SEL_VSB 0x2
2807 #define IQM_RT_COMM_EXEC_HOLD 0x2
2821 #define IQM_RT_COMM_MB_OBS__M 0x2
2824 #define IQM_RT_COMM_MB_OBS_OBS_ON 0x2
2840 #define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2
2843 #define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2
2866 #define IQM_RT_ROT_BP_ROT_BPF__M 0x2
2885 #define IQM_CF_COMM_EXEC_HOLD 0x2
2899 #define IQM_CF_COMM_MB_OBS__M 0x2
2902 #define IQM_CF_COMM_MB_OBS_OBS_ON 0x2
2947 #define IQM_CF_SYMMETRIC_IM__M 0x2
2962 #define IQM_CF_MIDTAP_IM__M 0x2
2963 #define IQM_CF_MIDTAP_IM__PRE 0x2
2977 #define IQM_CF_OUT_ENA_QAM__M 0x2
3007 #define IQM_CF_POW_MEAS_LEN__PRE 0x2
3014 #define IQM_CF_POW__PRE 0x2
3018 #define IQM_CF_TAP_RE0__PRE 0x2
3022 #define IQM_CF_TAP_RE1__PRE 0x2
3026 #define IQM_CF_TAP_RE2__PRE 0x2
3030 #define IQM_CF_TAP_RE3__PRE 0x2
3034 #define IQM_CF_TAP_RE4__PRE 0x2
3038 #define IQM_CF_TAP_RE5__PRE 0x2
3042 #define IQM_CF_TAP_RE6__PRE 0x2
3046 #define IQM_CF_TAP_RE7__PRE 0x2
3050 #define IQM_CF_TAP_RE8__PRE 0x2
3054 #define IQM_CF_TAP_RE9__PRE 0x2
3058 #define IQM_CF_TAP_RE10__PRE 0x2
3062 #define IQM_CF_TAP_RE11__PRE 0x2
3066 #define IQM_CF_TAP_RE12__PRE 0x2
3070 #define IQM_CF_TAP_RE13__PRE 0x2
3074 #define IQM_CF_TAP_RE14__PRE 0x2
3078 #define IQM_CF_TAP_RE15__PRE 0x2
3082 #define IQM_CF_TAP_RE16__PRE 0x2
3086 #define IQM_CF_TAP_RE17__PRE 0x2
3090 #define IQM_CF_TAP_RE18__PRE 0x2
3094 #define IQM_CF_TAP_RE19__PRE 0x2
3098 #define IQM_CF_TAP_RE20__PRE 0x2
3102 #define IQM_CF_TAP_RE21__PRE 0x2
3106 #define IQM_CF_TAP_RE22__PRE 0x2
3110 #define IQM_CF_TAP_RE23__PRE 0x2
3114 #define IQM_CF_TAP_RE24__PRE 0x2
3118 #define IQM_CF_TAP_RE25__PRE 0x2
3122 #define IQM_CF_TAP_RE26__PRE 0x2
3126 #define IQM_CF_TAP_RE27__PRE 0x2
3130 #define IQM_CF_TAP_IM0__PRE 0x2
3134 #define IQM_CF_TAP_IM1__PRE 0x2
3138 #define IQM_CF_TAP_IM2__PRE 0x2
3142 #define IQM_CF_TAP_IM3__PRE 0x2
3146 #define IQM_CF_TAP_IM4__PRE 0x2
3150 #define IQM_CF_TAP_IM5__PRE 0x2
3154 #define IQM_CF_TAP_IM6__PRE 0x2
3158 #define IQM_CF_TAP_IM7__PRE 0x2
3162 #define IQM_CF_TAP_IM8__PRE 0x2
3166 #define IQM_CF_TAP_IM9__PRE 0x2
3170 #define IQM_CF_TAP_IM10__PRE 0x2
3174 #define IQM_CF_TAP_IM11__PRE 0x2
3178 #define IQM_CF_TAP_IM12__PRE 0x2
3182 #define IQM_CF_TAP_IM13__PRE 0x2
3186 #define IQM_CF_TAP_IM14__PRE 0x2
3190 #define IQM_CF_TAP_IM15__PRE 0x2
3194 #define IQM_CF_TAP_IM16__PRE 0x2
3198 #define IQM_CF_TAP_IM17__PRE 0x2
3202 #define IQM_CF_TAP_IM18__PRE 0x2
3206 #define IQM_CF_TAP_IM19__PRE 0x2
3210 #define IQM_CF_TAP_IM20__PRE 0x2
3214 #define IQM_CF_TAP_IM21__PRE 0x2
3218 #define IQM_CF_TAP_IM22__PRE 0x2
3222 #define IQM_CF_TAP_IM23__PRE 0x2
3226 #define IQM_CF_TAP_IM24__PRE 0x2
3230 #define IQM_CF_TAP_IM25__PRE 0x2
3234 #define IQM_CF_TAP_IM26__PRE 0x2
3238 #define IQM_CF_TAP_IM27__PRE 0x2
3246 #define IQM_AF_COMM_EXEC_HOLD 0x2
3260 #define IQM_AF_COMM_MB_OBS__M 0x2
3263 #define IQM_AF_COMM_MB_OBS_OBS_ON 0x2
3297 #define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x2
3310 #define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x2
3323 #define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2
3349 #define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2
3352 #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2
3437 #define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x2
3440 #define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x2
3534 #define IQM_AF_STDBY_STDBY_ADC__M 0x2
3537 #define IQM_AF_STDBY_STDBY_ADC_A1_STANDBY 0x2
3538 #define IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE 0x2
3600 #define ORX_COMM_EXEC_HOLD 0x2
3620 #define ORX_COMM_INT_REQ_DDC_REQ__M 0x2
3654 #define ORX_TOP_COMM_EXEC_HOLD 0x2
3665 #define ORX_TOP_MDE_W__PRE 0x2
3668 #define ORX_TOP_MDE_W_RATE_2048KBPS_SQRT 0x2
3683 #define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__M 0x2
3686 #define ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REVERSAL_BIT_ORDER_ADC 0x2
3700 #define ORX_FWP_COMM_EXEC_HOLD 0x2
3714 #define ORX_FWP_COMM_MB_OBS__M 0x2
3717 #define ORX_FWP_COMM_MB_OBS_ON 0x2
3781 #define ORX_FWP_KR1_LDT_W__PRE 0x2
3818 #define ORX_EQU_COMM_EXEC_HOLD 0x2
3832 #define ORX_EQU_COMM_MB_OBS__M 0x2
3835 #define ORX_EQU_COMM_MB_OBS_ON 0x2
3863 #define ORX_EQU_COMM_INT_STA_FBF_READ__M 0x2
3876 #define ORX_EQU_COMM_INT_MSK_FBF_READ__M 0x2
3889 #define ORX_EQU_COMM_INT_STM_FBF_READ__M 0x2
3909 #define ORX_EQU_FFF_STP_W__PRE 0x2
4048 #define ORX_EQU_FBF_STP_W__PRE 0x2
4175 #define ORX_DDC_COMM_EXEC_HOLD 0x2
4189 #define ORX_DDC_COMM_MB_OBS__M 0x2
4192 #define ORX_DDC_COMM_MB_OBS_ON 0x2
4267 #define ORX_DDC_OFO_SET_W_PHASE__PRE 0x2
4290 #define ORX_CON_COMM_EXEC_HOLD 0x2
4314 #define ORX_CON_RST_W_CTI__M 0x2
4437 #define ORX_NSU_COMM_EXEC_HOLD 0x2
4455 #define ORX_NSU_AOX_STDBY_W_STDBYAMP__M 0x2
4458 #define ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_OFF 0x2
4460 #define ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON 0x2
4546 #define ORX_NSU_AOX_LOPOW_W_POWER_MINUS10DB 0x2
4580 #define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__M 0x2
4594 #define ORX_TST_COMM_EXEC_HOLD 0x2
4607 #define QAM_COMM_EXEC_HOLD 0x2
4625 #define QAM_COMM_INT_REQ_LC_REQ__M 0x2
4657 #define QAM_TOP_COMM_EXEC_HOLD 0x2
4665 #define QAM_TOP_ANNEX_C 0x2
4674 #define QAM_TOP_CONSTELLATION_QAM8 0x2
4687 #define QAM_FQ_COMM_EXEC_HOLD 0x2
4702 #define QAM_FQ_MODE_TAPLMS__M 0x2
4704 #define QAM_FQ_MODE_TAPLMS_UPD 0x2
4744 #define QAM_FQ_TAP_RE_EL0__PRE 0x2
4749 #define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x2
4754 #define QAM_FQ_TAP_IM_EL0__PRE 0x2
4759 #define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x2
4764 #define QAM_FQ_TAP_RE_EL1__PRE 0x2
4769 #define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x2
4774 #define QAM_FQ_TAP_IM_EL1__PRE 0x2
4779 #define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x2
4784 #define QAM_FQ_TAP_RE_EL2__PRE 0x2
4789 #define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x2
4794 #define QAM_FQ_TAP_IM_EL2__PRE 0x2
4799 #define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x2
4804 #define QAM_FQ_TAP_RE_EL3__PRE 0x2
4809 #define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x2
4814 #define QAM_FQ_TAP_IM_EL3__PRE 0x2
4819 #define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x2
4824 #define QAM_FQ_TAP_RE_EL4__PRE 0x2
4829 #define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x2
4834 #define QAM_FQ_TAP_IM_EL4__PRE 0x2
4839 #define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x2
4844 #define QAM_FQ_TAP_RE_EL5__PRE 0x2
4849 #define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x2
4854 #define QAM_FQ_TAP_IM_EL5__PRE 0x2
4859 #define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x2
4864 #define QAM_FQ_TAP_RE_EL6__PRE 0x2
4869 #define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x2
4874 #define QAM_FQ_TAP_IM_EL6__PRE 0x2
4879 #define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x2
4884 #define QAM_FQ_TAP_RE_EL7__PRE 0x2
4889 #define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x2
4894 #define QAM_FQ_TAP_IM_EL7__PRE 0x2
4899 #define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x2
4904 #define QAM_FQ_TAP_RE_EL8__PRE 0x2
4909 #define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x2
4914 #define QAM_FQ_TAP_IM_EL8__PRE 0x2
4919 #define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x2
4924 #define QAM_FQ_TAP_RE_EL9__PRE 0x2
4929 #define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x2
4934 #define QAM_FQ_TAP_IM_EL9__PRE 0x2
4939 #define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x2
4944 #define QAM_FQ_TAP_RE_EL10__PRE 0x2
4949 #define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x2
4954 #define QAM_FQ_TAP_IM_EL10__PRE 0x2
4959 #define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x2
4964 #define QAM_FQ_TAP_RE_EL11__PRE 0x2
4969 #define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x2
4974 #define QAM_FQ_TAP_IM_EL11__PRE 0x2
4979 #define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x2
4984 #define QAM_FQ_TAP_RE_EL12__PRE 0x2
4989 #define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x2
4994 #define QAM_FQ_TAP_IM_EL12__PRE 0x2
4999 #define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x2
5004 #define QAM_FQ_TAP_RE_EL13__PRE 0x2
5009 #define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x2
5014 #define QAM_FQ_TAP_IM_EL13__PRE 0x2
5019 #define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x2
5024 #define QAM_FQ_TAP_RE_EL14__PRE 0x2
5029 #define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x2
5034 #define QAM_FQ_TAP_IM_EL14__PRE 0x2
5039 #define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x2
5044 #define QAM_FQ_TAP_RE_EL15__PRE 0x2
5049 #define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x2
5054 #define QAM_FQ_TAP_IM_EL15__PRE 0x2
5059 #define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x2
5064 #define QAM_FQ_TAP_RE_EL16__PRE 0x2
5069 #define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x2
5074 #define QAM_FQ_TAP_IM_EL16__PRE 0x2
5079 #define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x2
5084 #define QAM_FQ_TAP_RE_EL17__PRE 0x2
5089 #define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x2
5094 #define QAM_FQ_TAP_IM_EL17__PRE 0x2
5099 #define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x2
5104 #define QAM_FQ_TAP_RE_EL18__PRE 0x2
5109 #define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x2
5114 #define QAM_FQ_TAP_IM_EL18__PRE 0x2
5119 #define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x2
5134 #define QAM_FQ_TAP_IM_EL19__PRE 0x2
5139 #define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x2
5144 #define QAM_FQ_TAP_RE_EL20__PRE 0x2
5149 #define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x2
5154 #define QAM_FQ_TAP_IM_EL20__PRE 0x2
5159 #define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x2
5164 #define QAM_FQ_TAP_RE_EL21__PRE 0x2
5169 #define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x2
5174 #define QAM_FQ_TAP_IM_EL21__PRE 0x2
5179 #define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x2
5184 #define QAM_FQ_TAP_RE_EL22__PRE 0x2
5189 #define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x2
5194 #define QAM_FQ_TAP_IM_EL22__PRE 0x2
5199 #define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x2
5204 #define QAM_FQ_TAP_RE_EL23__PRE 0x2
5209 #define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x2
5214 #define QAM_FQ_TAP_IM_EL23__PRE 0x2
5219 #define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2
5227 #define QAM_SL_COMM_EXEC_HOLD 0x2
5241 #define QAM_SL_COMM_MB_OBS__M 0x2
5244 #define QAM_SL_COMM_MB_OBS_ON 0x2
5270 #define QAM_SL_COMM_INT_STA_MER_INT__M 0x2
5283 #define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x2
5296 #define QAM_SL_COMM_INT_STM_MER_STM__M 0x2
5310 #define QAM_SL_MODE_SLICER4LC_RAD 0x2
5422 #define QAM_DQ_COMM_EXEC_HOLD 0x2
5437 #define QAM_DQ_MODE_TAPLMS__M 0x2
5439 #define QAM_DQ_MODE_TAPLMS_UPD 0x2
5572 #define QAM_DQ_TAP_RE_EL0__PRE 0x2
5577 #define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x2
5582 #define QAM_DQ_TAP_IM_EL0__PRE 0x2
5587 #define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x2
5592 #define QAM_DQ_TAP_RE_EL1__PRE 0x2
5597 #define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x2
5602 #define QAM_DQ_TAP_IM_EL1__PRE 0x2
5607 #define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x2
5612 #define QAM_DQ_TAP_RE_EL2__PRE 0x2
5617 #define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x2
5622 #define QAM_DQ_TAP_IM_EL2__PRE 0x2
5627 #define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x2
5632 #define QAM_DQ_TAP_RE_EL3__PRE 0x2
5637 #define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x2
5642 #define QAM_DQ_TAP_IM_EL3__PRE 0x2
5647 #define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x2
5652 #define QAM_DQ_TAP_RE_EL4__PRE 0x2
5657 #define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x2
5662 #define QAM_DQ_TAP_IM_EL4__PRE 0x2
5667 #define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x2
5672 #define QAM_DQ_TAP_RE_EL5__PRE 0x2
5677 #define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x2
5682 #define QAM_DQ_TAP_IM_EL5__PRE 0x2
5687 #define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x2
5692 #define QAM_DQ_TAP_RE_EL6__PRE 0x2
5697 #define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x2
5702 #define QAM_DQ_TAP_IM_EL6__PRE 0x2
5707 #define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x2
5712 #define QAM_DQ_TAP_RE_EL7__PRE 0x2
5717 #define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x2
5722 #define QAM_DQ_TAP_IM_EL7__PRE 0x2
5727 #define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x2
5732 #define QAM_DQ_TAP_RE_EL8__PRE 0x2
5737 #define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x2
5742 #define QAM_DQ_TAP_IM_EL8__PRE 0x2
5747 #define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x2
5752 #define QAM_DQ_TAP_RE_EL9__PRE 0x2
5757 #define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x2
5762 #define QAM_DQ_TAP_IM_EL9__PRE 0x2
5767 #define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x2
5772 #define QAM_DQ_TAP_RE_EL10__PRE 0x2
5777 #define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x2
5782 #define QAM_DQ_TAP_IM_EL10__PRE 0x2
5787 #define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x2
5792 #define QAM_DQ_TAP_RE_EL11__PRE 0x2
5797 #define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x2
5802 #define QAM_DQ_TAP_IM_EL11__PRE 0x2
5807 #define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x2
5812 #define QAM_DQ_TAP_RE_EL12__PRE 0x2
5817 #define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x2
5822 #define QAM_DQ_TAP_IM_EL12__PRE 0x2
5827 #define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x2
5832 #define QAM_DQ_TAP_RE_EL13__PRE 0x2
5837 #define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x2
5842 #define QAM_DQ_TAP_IM_EL13__PRE 0x2
5847 #define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x2
5852 #define QAM_DQ_TAP_RE_EL14__PRE 0x2
5857 #define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x2
5862 #define QAM_DQ_TAP_IM_EL14__PRE 0x2
5867 #define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x2
5872 #define QAM_DQ_TAP_RE_EL15__PRE 0x2
5877 #define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x2
5882 #define QAM_DQ_TAP_IM_EL15__PRE 0x2
5887 #define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x2
5892 #define QAM_DQ_TAP_RE_EL16__PRE 0x2
5897 #define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x2
5902 #define QAM_DQ_TAP_IM_EL16__PRE 0x2
5907 #define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x2
5912 #define QAM_DQ_TAP_RE_EL17__PRE 0x2
5917 #define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x2
5922 #define QAM_DQ_TAP_IM_EL17__PRE 0x2
5927 #define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x2
5932 #define QAM_DQ_TAP_RE_EL18__PRE 0x2
5937 #define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x2
5942 #define QAM_DQ_TAP_IM_EL18__PRE 0x2
5947 #define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x2
5952 #define QAM_DQ_TAP_RE_EL19__PRE 0x2
5957 #define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x2
5962 #define QAM_DQ_TAP_IM_EL19__PRE 0x2
5967 #define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x2
5972 #define QAM_DQ_TAP_RE_EL20__PRE 0x2
5977 #define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x2
5982 #define QAM_DQ_TAP_IM_EL20__PRE 0x2
5987 #define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x2
5992 #define QAM_DQ_TAP_RE_EL21__PRE 0x2
5997 #define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x2
6002 #define QAM_DQ_TAP_IM_EL21__PRE 0x2
6007 #define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x2
6012 #define QAM_DQ_TAP_RE_EL22__PRE 0x2
6017 #define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x2
6022 #define QAM_DQ_TAP_IM_EL22__PRE 0x2
6027 #define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x2
6032 #define QAM_DQ_TAP_RE_EL23__PRE 0x2
6037 #define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x2
6042 #define QAM_DQ_TAP_IM_EL23__PRE 0x2
6047 #define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x2
6052 #define QAM_DQ_TAP_RE_EL24__PRE 0x2
6057 #define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x2
6062 #define QAM_DQ_TAP_IM_EL24__PRE 0x2
6067 #define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x2
6072 #define QAM_DQ_TAP_RE_EL25__PRE 0x2
6077 #define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x2
6082 #define QAM_DQ_TAP_IM_EL25__PRE 0x2
6087 #define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x2
6092 #define QAM_DQ_TAP_RE_EL26__PRE 0x2
6097 #define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x2
6102 #define QAM_DQ_TAP_IM_EL26__PRE 0x2
6107 #define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x2
6112 #define QAM_DQ_TAP_RE_EL27__PRE 0x2
6117 #define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x2
6122 #define QAM_DQ_TAP_IM_EL27__PRE 0x2
6127 #define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2
6135 #define QAM_LC_COMM_EXEC_HOLD 0x2
6149 #define QAM_LC_COMM_MB_OBS__M 0x2
6152 #define QAM_LC_COMM_MB_OBS_ON 0x2
6170 #define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x2
6188 #define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x2
6205 #define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x2
6224 #define QAM_LC_MODE_ENABLE_F__M 0x2
6225 #define QAM_LC_MODE_ENABLE_F__PRE 0x2
6507 #define QAM_LC_MTA_LENGTH__PRE 0x2
6512 #define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x2
6590 #define QAM_VD_COMM_EXEC_HOLD 0x2
6604 #define QAM_VD_COMM_MB_OBS__M 0x2
6607 #define QAM_VD_COMM_MB_OBS_ON 0x2
6625 #define QAM_VD_COMM_INT_STA_PERIOD_INT__M 0x2
6638 #define QAM_VD_COMM_INT_MSK_PERIOD_INT__M 0x2
6651 #define QAM_VD_COMM_INT_STM_PERIOD_INT__M 0x2
6789 #define QAM_SY_COMM_EXEC_HOLD 0x2
6803 #define QAM_SY_COMM_MB_OBS__M 0x2
6806 #define QAM_SY_COMM_MB_OBS_ON 0x2
6824 #define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x2
6847 #define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2
6868 #define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2
6897 #define QAM_SY_SYNC_LWM__PRE 0x2
6935 #define SCU_COMM_EXEC_HOLD 0x2
6953 #define SCU_TOP_COMM_EXEC_HOLD 0x2
6973 #define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x2
6976 #define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2
7335 #define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x2
7338 #define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x2
7727 #define SCU_RAM_ORX_SCU_STATE_DGN_HUNT 0x2
7747 #define SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT 0x2
8111 #define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x2
8156 #define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x2
8159 #define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x2
8465 #define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x2
8495 #define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x2
8723 #define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x2
9207 #define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x2
9312 #define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x2
9348 #define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x2
9376 #define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x2
9446 #define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x2
9660 #define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x2
9678 #define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x2
9697 #define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x2
9766 #define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x2
9857 #define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__M 0x2
9860 #define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_ON 0x2
10050 #define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2
10060 #define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2
10073 #define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2
10164 #define SIO_COMM_EXEC_HOLD 0x2
10186 #define SIO_COMM_INT_REQ_SA_REQ__M 0x2
10208 #define SIO_TOP_COMM_EXEC_HOLD 0x2
10278 #define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x2
10382 #define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x2
10447 #define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x2
10457 #define SIO_HI_RA_RAM_CMD_RESET 0x2
10492 #define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2
10495 #define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2
10636 #define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2
10639 #define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2
10854 #define SIO_HI_IF_COMM_EXEC_HOLD 0x2
10895 #define SIO_HI_IF_STK_0__PRE 0x2
10900 #define SIO_HI_IF_STK_0_ADDR__PRE 0x2
10905 #define SIO_HI_IF_STK_1__PRE 0x2
10909 #define SIO_HI_IF_STK_1_ADDR__PRE 0x2
10914 #define SIO_HI_IF_STK_2__PRE 0x2
10918 #define SIO_HI_IF_STK_2_ADDR__PRE 0x2
10923 #define SIO_HI_IF_STK_3__PRE 0x2
10928 #define SIO_HI_IF_STK_3_ADDR__PRE 0x2
10943 #define SIO_HI_IF_BPT__PRE 0x2
10948 #define SIO_HI_IF_BPT_ADDR__PRE 0x2
10956 #define SIO_CC_COMM_EXEC_HOLD 0x2
10969 #define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x2
11020 #define SIO_CC_PWD_MODE_LEVEL_PLL 0x2
11040 #define SIO_CC_SOFT_RST_OSC__M 0x2
11055 #define SIO_SA_COMM_EXEC_HOLD 0x2
11073 #define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x2
11098 #define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x2
11123 #define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x2
11172 #define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x2
11173 #define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x2
11187 #define SIO_SA_TX_STATUS_BUFF_FULL__M 0x2
11224 #define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2
11233 #define SIO_PDR_COMM_EXEC_HOLD 0x2
11247 #define SIO_PDR_MON_CFG_IACT__M 0x2
12053 #define VSB_COMM_EXEC_HOLD 0x2
12090 #define VSB_TOP_COMM_EXEC_HOLD 0x2
12106 #define VSB_TOP_COMM_MB_OBS__M 0x2
12109 #define VSB_TOP_COMM_MB_OBS_OBS_ON 0x2
12146 #define VSB_TOP_COMM_INT_STA_LOCK_STA__M 0x2
12181 #define VSB_TOP_COMM_INT_MSK_LOCK_MSK__M 0x2
12216 #define VSB_TOP_COMM_INT_STM_LOCK_STM__M 0x2
12252 #define VSB_TOP_CKGN2ACQ__PRE 0x2
12282 #define VSB_TOP_CYGN2TRK__PRE 0x2
12300 #define VSB_TOP_SYNCCTRLWORD_DCFREEZ__M 0x2
12339 #define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__M 0x2
12484 #define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__M 0x2
12567 #define VSB_TOP_EQSMRSTCTRL_DFEON__M 0x2
12607 #define VSB_TOP_EQSMTRNCTRL_DFEON__M 0x2
12647 #define VSB_TOP_EQSMRCA1CTRL_DFEON__M 0x2
12687 #define VSB_TOP_EQSMRCA2CTRL_DFEON__M 0x2
12688 #define VSB_TOP_EQSMRCA2CTRL_DFEON__PRE 0x2
12727 #define VSB_TOP_EQSMDDM1CTRL_DFEON__M 0x2
12728 #define VSB_TOP_EQSMDDM1CTRL_DFEON__PRE 0x2
12767 #define VSB_TOP_EQSMDDM2CTRL_DFEON__M 0x2
12768 #define VSB_TOP_EQSMDDM2CTRL_DFEON__PRE 0x2
12807 #define VSB_TOP_SYSSMRSTCTRL_CTCALEN__M 0x2
12867 #define VSB_TOP_SYSSMCYCTRL_CTCALEN__M 0x2
12927 #define VSB_TOP_SYSSMTRNCTRL_CTCALEN__M 0x2
12987 #define VSB_TOP_SYSSMEQCTRL_CTCALEN__M 0x2
13047 #define VSB_TOP_SYSSMAGCCTRL_CTCALEN__M 0x2
13107 #define VSB_TOP_SYSSMCTCTRL_CTCALEN__M 0x2
13108 #define VSB_TOP_SYSSMCTCTRL_CTCALEN__PRE 0x2
13167 #define VSB_TOP_EQCTRL_ORCANCMAEN__M 0x2
13168 #define VSB_TOP_EQCTRL_ORCANCMAEN__PRE 0x2
13553 #define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__M 0x2
/linux-4.4.14/net/bluetooth/
H A Decc.c603 /* P = (x1, y1) => 2P, (x2, y2) => P' */ xycz_initial_double()
604 static void xycz_initial_double(u64 *x1, u64 *y1, u64 *x2, u64 *y2, xycz_initial_double() argument
609 vli_set(x2, x1); xycz_initial_double()
622 apply_z(x2, y2, z); xycz_initial_double()
625 /* Input P = (x1, y1, Z), Q = (x2, y2, Z)
629 static void xycz_add(u64 *x1, u64 *y1, u64 *x2, u64 *y2) xycz_add() argument
634 vli_mod_sub(t5, x2, x1, curve_p); /* t5 = x2 - x1 */ xycz_add()
635 vli_mod_square_fast(t5, t5); /* t5 = (x2 - x1)^2 = A */ xycz_add()
637 vli_mod_mult_fast(x2, x2, t5); /* t3 = x2*A = C */ xycz_add()
642 vli_mod_sub(t5, t5, x2, curve_p); /* t5 = D - B - C = x3 */ xycz_add()
643 vli_mod_sub(x2, x2, x1, curve_p); /* t3 = C - B */ xycz_add()
644 vli_mod_mult_fast(y1, y1, x2); /* t2 = y1*(C - B) */ xycz_add()
645 vli_mod_sub(x2, x1, t5, curve_p); /* t3 = B - x3 */ xycz_add()
646 vli_mod_mult_fast(y2, y2, x2); /* t4 = (y2 - y1)*(B - x3) */ xycz_add()
649 vli_set(x2, t5); xycz_add()
652 /* Input P = (x1, y1, Z), Q = (x2, y2, Z)
656 static void xycz_add_c(u64 *x1, u64 *y1, u64 *x2, u64 *y2) xycz_add_c() argument
663 vli_mod_sub(t5, x2, x1, curve_p); /* t5 = x2 - x1 */ xycz_add_c()
664 vli_mod_square_fast(t5, t5); /* t5 = (x2 - x1)^2 = A */ xycz_add_c()
666 vli_mod_mult_fast(x2, x2, t5); /* t3 = x2*A = C */ xycz_add_c()
670 vli_mod_sub(t6, x2, x1, curve_p); /* t6 = C - B */ xycz_add_c()
672 vli_mod_add(t6, x1, x2, curve_p); /* t6 = B + C */ xycz_add_c()
673 vli_mod_square_fast(x2, y2); /* t3 = (y2 - y1)^2 */ xycz_add_c()
674 vli_mod_sub(x2, x2, t6, curve_p); /* t3 = x3 */ xycz_add_c()
676 vli_mod_sub(t7, x1, x2, curve_p); /* t7 = B - x3 */ xycz_add_c()
/linux-4.4.14/drivers/net/wireless/brcm80211/brcmsmac/phy/
H A Dphyreg_n.h71 #define NPHY_ClassifierCtrl_ofdm_en 0x2
83 #define NPHY_IqestCmd_iqMode 0x2
92 #define NPHY_RFSEQ_RESET2RX 0x2
99 #define NPHY_RFSEQ_CMD_TR_SWITCH 0x2
110 #define NPHY_REV3_RFSEQ_CMD_TR_SWITCH 0x2
128 #define NPHY_RSSI_SEL_NB 0x2
141 #define NPHY_REV7_RfctrlOverride_cmd_tx_pu 0x2
155 #define NPHY_REV7_RFCTRLOVERRIDE_ID2 0x2
/linux-4.4.14/arch/tile/include/arch/
H A Dmpipe_def.h27 #define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_512 0x2
35 #define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_ALWAYS_PICK 0x2
H A Dtrio_def.h23 #define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD 0x2
39 #define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_REL_ORD 0x2
H A Dmpipe_shm_def.h21 #define MPIPE_EDMA_DESC_WORD1__C_VAL_NOT_RDY 0x2
/linux-4.4.14/include/drm/
H A Ddrm_rect.h37 * @x2: horizontal ending coordinate (exclusive)
42 int x1, y1, x2, y2; member in struct:drm_rect
61 r->x2 += (dw + 1) >> 1; drm_rect_adjust_size()
78 r->x2 += dx; drm_rect_translate()
94 r->x2 /= horz; drm_rect_downscale()
107 return r->x2 - r->x1; drm_rect_width()
145 return r1->x1 == r2->x1 && r1->x2 == r2->x2 && drm_rect_equals()
/linux-4.4.14/arch/arm64/crypto/
H A Daes-modes.S43 encrypt_block2x v0, v1, w3, x2, x6, w7
48 decrypt_block2x v0, v1, w3, x2, x6, w7
55 encrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
60 decrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
89 encrypt_block2x v0, v1, w3, x2, x6, w7
93 decrypt_block2x v0, v1, w3, x2, x6, w7
97 encrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
101 decrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
117 enc_prepare w3, x2, x5
139 encrypt_block v0, w3, x2, x5, w6
153 dec_prepare w3, x2, x5
175 decrypt_block v0, w3, x2, x5, w6
196 enc_prepare w3, x2, x5
201 encrypt_block v0, w3, x2, x5, w6
214 dec_prepare w3, x2, x5
251 decrypt_block v0, w3, x2, x5, w6
282 enc_prepare w3, x2, x6
344 encrypt_block v0, w3, x2, x6, w7
398 enc_switch_key w3, x2, x6
450 encrypt_block v0, w3, x2, x6, w7
470 dec_prepare w3, x2, x6
522 decrypt_block v0, w3, x2, x6, w7
/linux-4.4.14/drivers/scsi/qla4xxx/
H A Dql4_bsg.h21 #define QL_DIAG_CMD_TEST_DDR_SIZE 0x2
/linux-4.4.14/drivers/power/
H A Dpm2301_charger.h87 #define PM2XXX_CH_WD_CC_PHASE_10MIN 0x2
96 #define PM2XXX_CH_WD_CV_PHASE_10MIN (0x2<<3)
106 #define PM2XXX_CH_WD_PRECH_PHASE_5MIN 0x2
120 #define PM2XXX_DIR_CH_CC_CURRENT_400MA 0x2
138 #define PM2XXX_CH_PRECH_CURRENT_75MA (0x2<<4)
144 #define PM2XXX_CH_EOC_CURRENT_300MA (0x2<<6)
150 #define PM2XXX_CH_PRECH_VOL_2_9 0x2
155 #define PM2XXX_CH_VRESUME_VOL_3_6 (0x2<<2)
173 #define PM2XXX_BTEMP_HIGH_TH_55 0x2
179 #define PM2XXX_BTEMP_LOW_TH_5 (0x2<<3)
188 #define PM2XXX_NTC_RES_100K (0x2<<2)
197 #define PM2XXX_CH_CC_REDUCED_CURRENT_400MA (0x2<<1)
210 #define PM2XXX_CHG_STATUS_FULL 0x2
218 #define PM2XXX_VPWR2_OVV_10 0x2
234 #define PM2XXX_VPWR1_OVV_10 0x2
254 #define PM2XXX_VBAT_LOW_LEVEL_2_5 0x2
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/interrupt-controller/
H A Dirq-st.h27 #define ST_IRQ_SYSCFG_EXT_2_INV 0x2
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/pinctrl/
H A Dat91.h25 #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
H A Ddra.h18 #define MUX_MODE2 0x2
36 #define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
/linux-4.4.14/include/net/tc_act/
H A Dtc_vlan.h16 #define VLAN_F_PUSH 0x2
/linux-4.4.14/include/dt-bindings/interrupt-controller/
H A Dirq-st.h27 #define ST_IRQ_SYSCFG_EXT_2_INV 0x2
/linux-4.4.14/include/dt-bindings/pinctrl/
H A Dat91.h25 #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
H A Ddra.h18 #define MUX_MODE2 0x2
36 #define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
/linux-4.4.14/include/uapi/linux/
H A Dcoda_psdev.h23 #define CODA_REQ_READ 0x2
H A Dif_plip.h25 #define PLIP_SET_TIMEOUT 0x2
H A Dfirewire-constants.h31 #define TCODE_WRITE_RESPONSE 0x2
42 #define EXTCODE_COMPARE_SWAP 0x2
73 #define SCODE_400 0x2
80 #define ACK_PENDING 0x2
H A Disdn_ppp.h17 #define CALLTYPE_OUTGOING 0x2
58 #define IPPP_COMP_FLAG_LINK 0x2
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/interrupt-controller/
H A Dirq-st.h27 #define ST_IRQ_SYSCFG_EXT_2_INV 0x2
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/pinctrl/
H A Dat91.h25 #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
H A Ddra.h18 #define MUX_MODE2 0x2
36 #define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/interrupt-controller/
H A Dirq-st.h27 #define ST_IRQ_SYSCFG_EXT_2_INV 0x2
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/pinctrl/
H A Dat91.h25 #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
H A Ddra.h18 #define MUX_MODE2 0x2
36 #define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/interrupt-controller/
H A Dirq-st.h27 #define ST_IRQ_SYSCFG_EXT_2_INV 0x2
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/pinctrl/
H A Dat91.h25 #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
H A Ddra.h18 #define MUX_MODE2 0x2
36 #define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/interrupt-controller/
H A Dirq-st.h27 #define ST_IRQ_SYSCFG_EXT_2_INV 0x2
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/pinctrl/
H A Dat91.h25 #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
H A Ddra.h18 #define MUX_MODE2 0x2
36 #define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
/linux-4.4.14/arch/blackfin/include/asm/
H A Dbfin_watchdog.h20 #define ICTL_NMI 0x2
H A Dbfin_pfmon.h17 #define PFCEN_ENABLE_SUPV 0x2
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/interrupt-controller/
H A Dirq-st.h27 #define ST_IRQ_SYSCFG_EXT_2_INV 0x2
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/pinctrl/
H A Dat91.h25 #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
H A Ddra.h18 #define MUX_MODE2 0x2
36 #define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
/linux-4.4.14/sound/soc/atmel/
H A Datmel-classd.h41 #define CLASSD_MR_NOVR_VAL_15NS 0x2
70 #define CLASSD_INTPMR_FRAME_32K 0x2
81 #define CLASSD_INTPMR_EQCFG_B_BOOST_6 0x2
101 #define CLASSD_INTPMR_MONO_MODE_LEFT 0x2
/linux-4.4.14/drivers/scsi/
H A Dultrastor.h63 #define OP_SCSI 0x2
69 #define DTD_OUT 0x2
74 #define HA_CMD_SELF_DIAG 0x2
/linux-4.4.14/drivers/iio/dac/
H A Dad5624r.h15 #define AD5624R_ADDR_DAC2 0x2
21 #define AD5624R_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2
30 #define AD5624R_LDAC_PWRDN_100K 0x2
/linux-4.4.14/arch/arm/mach-pxa/
H A Dsmemc.c44 __raw_writel(0x2, CSMSADRCFG); pxa3xx_smemc_resume()
58 * it must be programmed to 0x2. smemc_init()
63 __raw_writel(0x2, CSMSADRCFG); smemc_init()
/linux-4.4.14/drivers/gpu/drm/virtio/
H A Dvirtgpu_fb.c48 int x2, y2; virtio_gpu_dirty_update() local
71 x2 = x + width - 1; virtio_gpu_dirty_update()
82 if (fb->x2 > x2) virtio_gpu_dirty_update()
83 x2 = fb->x2; virtio_gpu_dirty_update()
87 fb->x2 = x2; virtio_gpu_dirty_update()
95 fb->x2 = fb->y2 = 0; virtio_gpu_dirty_update()
101 uint32_t w = x2 - x + 1; virtio_gpu_dirty_update()
116 x, y, x2 - x + 1, y2 - y + 1); virtio_gpu_dirty_update()
135 norect.x2 = vgfb->base.width; virtio_gpu_surface_dirty()
139 right = clips->x2; virtio_gpu_surface_dirty()
147 right = max_t(int, right, (int)clips_ptr->x2); virtio_gpu_surface_dirty()
169 vgfb->x2 - vgfb->x1, vgfb->y2 - vgfb->y1); virtio_gpu_fb_dirty_work()
/linux-4.4.14/drivers/pinctrl/spear/
H A Dpinctrl-spear320.c54 .val = 0x2,
115 #define PMX_PWM_3_PL_6_VAL (0x2 << 18)
116 #define PMX_PWM_2_PL_7_VAL (0x2 << 21)
121 #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27))
139 #define PMX_PWM2_PL_13_VAL (0x2 << 9)
140 #define PMX_PWM1_PL_14_VAL (0x2 << 12)
143 #define PMX_PWM0_PL_15_VAL (0x2 << 15)
188 #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12)
193 #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15)
198 #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18)
203 #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24))
208 #define PMX_UART4_PL_39_VAL (0x2 << 27)
214 #define PMX_UART4_PL_40_VAL (0x2 << 0)
221 #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6))
227 #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9)
232 #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15))
237 #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21))
242 #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27))
247 #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3))
256 #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9))
260 #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
269 #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27))
279 #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
283 #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
288 #define PMX_EMI_PL_69_VAL (0x2 << 27)
295 #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0)
301 #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6))
307 #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9)
313 #define PMX_EMI_PL_74_VAL (0x2 << 12)
319 #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18))
325 #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
333 #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
342 #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21))
349 #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27))
357 #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3))
364 #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9))
371 #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15))
378 #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21))
384 #define PMX_I2C1_PL_98_VAL (0x2 << 24)
389 #define PMX_I2C1_PL_99_VAL (0x2 << 27)
400 #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8)
407 #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11)
414 #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14)
420 #define PMX_UART3_PORT_52_VAL (0x2 << 16)
429 #define PMX_UART4_PORT_39_VAL (0x2 << 19)
437 #define PMX_UART5_PORT_37_VAL (0x2 << 22)
451 #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26)
/linux-4.4.14/drivers/gpu/drm/exynos/
H A Dexynos_dp_reg.h128 #define IN_BPC_10_BITS (0x2 << 4)
133 #define IN_COLOR_F_YCBCR444 (0x2 << 0)
160 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6)
164 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4)
168 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2)
172 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0)
188 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4)
203 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
284 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
327 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
328 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
/linux-4.4.14/arch/x86/math-emu/
H A Dpoly.h41 asmlinkage void div_Xsig(Xsig *x1, const Xsig *x2, const Xsig *dest);
72 /* Add the 12 byte Xsig x2 to Xsig dest, with no checks for overflow. */ add_Xsig_Xsig()
73 static inline void add_Xsig_Xsig(Xsig *dest, const Xsig *x2) add_Xsig_Xsig() argument
79 (*dest):"g"(dest), "g"(x2) add_Xsig_Xsig()
83 /* Add the 12 byte Xsig x2 to Xsig dest, adjust exp if overflow occurs. */
87 static inline void add_two_Xsig(Xsig *dest, const Xsig *x2, long int *exp) add_two_Xsig() argument
98 :"g"(dest), "g"(x2), "g"(exp) add_two_Xsig()
/linux-4.4.14/drivers/atm/
H A Dfirestream.h98 #define Q_EMPTY 0x2
159 #define QE_CMD_IMM (0x2 << 30)
167 #define TD_OAM_CELL (0x2 << 29)
205 #define SARMODE0_TXVCS_2k (0x2 << 0)
215 #define SARMODE0_ABRVCS_1k (0x2 << 4)
226 #define SARMODE0_RXVCS_2k (0x2 << 8)
236 #define SARMODE0_CALSUP_3 (0x2 << 12)
241 #define SARMODE0_PRPWT_FS50_5 (0x2 << 14)
246 #define SARMODE0_PRPWT_FS155_2 (0x2 << 14)
260 #define SARMODE0_INTMODE_READNOCLEARINHIBIT (0x2 << 28)
339 #define CELLOSCONF_SC4 (0x2 << 24)
361 #define DMAMR_TX_MODE_NONE (0x2 << 0) /* And 3 */
383 #define TC_FLAGS_TRANSPARENT_CELL (0x2 << 29)
388 #define TC_FLAGS_TYPE_VBR (0x2 << 22)
392 #define TC_FLAGS_CAL2 (0x2 << 20)
399 #define RC_FLAGS_RXBM_PMB (0x2 << 14)
409 #define RC_FLAGS_BFPS_BFP2 (0x2 << 17)
428 #define RC_FLAGS_TRANSC (0x2 << 24)
506 #define FS_IS155 0x2
/linux-4.4.14/drivers/regulator/
H A Ds5m8767.c128 {0x0, 0x3, 0x2, 0x1}, /* LDO1 */
129 {0x0, 0x3, 0x2, 0x1},
130 {0x0, 0x3, 0x2, 0x1},
132 {0x0, 0x3, 0x2, 0x1}, /* LDO5 */
133 {0x0, 0x3, 0x2, 0x1},
134 {0x0, 0x3, 0x2, 0x1},
135 {0x0, 0x3, 0x2, 0x1},
136 {0x0, 0x3, 0x2, 0x1},
137 {0x0, 0x3, 0x2, 0x1}, /* LDO10 */
138 {0x0, 0x3, 0x2, 0x1},
139 {0x0, 0x3, 0x2, 0x1},
140 {0x0, 0x3, 0x2, 0x1},
141 {0x0, 0x3, 0x2, 0x1},
142 {0x0, 0x3, 0x2, 0x1}, /* LDO15 */
143 {0x0, 0x3, 0x2, 0x1},
144 {0x0, 0x3, 0x2, 0x1},
146 {0x0, 0x3, 0x2, 0x1},
147 {0x0, 0x3, 0x2, 0x1}, /* LDO20 */
148 {0x0, 0x3, 0x2, 0x1},
149 {0x0, 0x3, 0x2, 0x1},
151 {0x0, 0x3, 0x2, 0x1},
152 {0x0, 0x3, 0x2, 0x1}, /* LDO25 */
153 {0x0, 0x3, 0x2, 0x1},
154 {0x0, 0x3, 0x2, 0x1},
155 {0x0, 0x3, 0x2, 0x1}, /* LDO28 */
162 {0x0, 0x3, 0x2, 0x1}, /* BUCK5 */
H A Dmt6311-regulator.h50 #define MT6311_PMIC_RG_INT_EN_MASK 0x2
54 #define MT6311_PMIC_VDVFS11_VOSEL_CTRL_MASK 0x2
/linux-4.4.14/drivers/video/fbdev/mb862xx/
H A Dmb862xxfb_accel.c201 int x2, y2, vxres, vyres; mb86290fb_imageblit() local
204 x2 = image->dx + image->width; mb86290fb_imageblit()
208 x2 = min(x2, vxres); mb86290fb_imageblit()
210 width = x2 - dx; mb86290fb_imageblit()
260 u32 x2, y2, vxres, vyres, height, width, fg; mb86290fb_fillrect() local
272 x2 = rect->dx + rect->width; mb86290fb_fillrect()
274 x2 = min(x2, vxres); mb86290fb_fillrect()
276 width = x2 - rect->dx; mb86290fb_fillrect()
/linux-4.4.14/drivers/gpu/drm/mgag200/
H A Dmgag200_fb.c33 int x2, y2; mga_dirty_update() local
53 x2 = x + width - 1; mga_dirty_update()
63 if (mfbdev->x2 > x2) mga_dirty_update()
64 x2 = mfbdev->x2; mga_dirty_update()
68 mfbdev->x2 = x2; mga_dirty_update()
76 mfbdev->x2 = mfbdev->y2 = 0; mga_dirty_update()
91 memcpy_toio(bo->kmap.virtual + src_offset, mfbdev->sysram + src_offset, (x2 - x + 1) * bpp); mga_dirty_update()
/linux-4.4.14/drivers/media/dvb-frontends/
H A Ddrxk_map.h24 #define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2
48 #define FEC_OC_IPR_INVERT_MD1__M 0x2
67 #define IQM_FS_ADJ_SEL_B_VSB 0x2
76 #define IQM_RC_ADJ_SEL_B_VSB 0x2
103 #define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2
105 #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2
118 #define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2
137 #define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2
188 #define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2
194 #define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2
216 #define QAM_TOP_ANNEX_C 0x2
254 #define SCU_COMM_EXEC_HOLD 0x2
270 #define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2
368 #define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2
380 #define SIO_HI_RA_RAM_CMD_RESET 0x2
404 #define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2
409 #define SIO_CC_SOFT_RST_SYS__M 0x2
/linux-4.4.14/arch/m68k/include/asm/
H A Dm68360_quicc.h97 volatile unsigned char RESERVED2[0x2]; /* Reserved area */
100 volatile unsigned char RESERVED3[0x2]; /* Reserved area */
104 volatile unsigned char RESERVED63[0x2]; /* Reserved area */
110 volatile unsigned char RESERVED6[0x2]; /* Reserved area */
112 volatile unsigned char RESERVED7[0x2]; /* Reserved area */
157 volatile unsigned char RESERVED19[0x2]; /* Reserved area */
159 volatile unsigned char RESERVED68[0x2]; /* Reserved area */
175 volatile unsigned char RESERVED69[0x2]; /* Reserved area */
229 volatile unsigned char RESERVED35[0x2]; /* Reserved area */
238 volatile unsigned char RESERVED59[0x2]; /* Reserved area */
240 volatile unsigned char RESERVED38[0x2]; /* Reserved area */
303 volatile unsigned char RESERVED42[0x2]; /* Reserved area */
307 volatile unsigned char RESERVED43[0x2];/* Reserved area */
315 volatile unsigned char RESERVED46[0x2]; /* Reserved area */
317 volatile unsigned char RESERVED60[0x2]; /* Reserved area */
329 volatile unsigned char RESERVED53[0x2]; /* Reserved area */
334 volatile unsigned char RESERVED65[0x2]; /* Reserved area */
/linux-4.4.14/drivers/extcon/
H A Dextcon-sm5502.h137 #define TIMING_KEY_PRESS_300MS 0x2
149 #define TIMING_ADC_DET_150MS 0x2
164 #define TIMING_SW_WAIT_50MS 0x2
177 #define TIMING_LONG_KEY_500MS 0x2
229 #define VBUSIN_SWITCH_MIC 0x2
233 #define DM_DP_CON_SWITCH_AUDIO 0x2
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
H A Dgk20a.c36 nvkm_wr32(device, 0x122204, 0x2); gk20a_ibus_init_ibus_ring()
60 nvkm_mask(device, 0x12004c, 0x2, 0x2); gk20a_ibus_intr()
/linux-4.4.14/drivers/usb/image/
H A Dmicrotek.h49 #define MTS_EP_RESPONSE 0x2
/linux-4.4.14/drivers/staging/sm750fb/
H A Dddk750_power.h7 crtDPMS_SUSPEND = 0x2,
/linux-4.4.14/drivers/scsi/aic7xxx/
H A Dscsi_iu.h11 #define SIU_SNSVALID 0x2
/linux-4.4.14/drivers/ipack/devices/
H A Dscc2698.h90 #define MR1_CHRL_7_BITS (0x2 << 0)
96 #define MR1_PARITY_OFF (0x2 << 3)
113 #define MR2_CH_MODE_LOCAL (0x2 << 6)
121 #define CR_CMD_RESET_RX (0x2 << 4)
150 #define ACR_CTxCB (0x2 << 4)
161 #define TX_CLK_38400 (0x2 << 0)
174 #define RX_CLK_38400 (0x2 << 4)
188 #define OPCR_MPOa_TxC1X (0x2 << 0)
197 #define OPCR_MPOb_TxC1X (0x2 << 4)
/linux-4.4.14/drivers/gpu/drm/qxl/
H A Dqxl_fb.c56 unsigned x2; member in struct:qxl_fbdev::__anon4549
93 u32 x1, x2, y1, y2; qxl_fb_dirty_flush() local
101 x2 = qfbdev->dirty.x2; qxl_fb_dirty_flush()
105 qfbdev->dirty.x2 = 0; qxl_fb_dirty_flush()
114 qxl_io_log(qdev, "dirty x[%d, %d], y[%d, %d]", x1, x2, y1, y2); qxl_fb_dirty_flush()
117 image->width = x2 - x1 + 1; qxl_fb_dirty_flush()
140 int x2, y2; qxl_dirty_update() local
142 x2 = x + width - 1; qxl_dirty_update()
148 (qfbdev->dirty.x2 - qfbdev->dirty.x1)) { qxl_dirty_update()
155 if (qfbdev->dirty.x2 > x2) qxl_dirty_update()
156 x2 = qfbdev->dirty.x2; qxl_dirty_update()
160 qfbdev->dirty.x2 = x2; qxl_dirty_update()
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_2_0_sh_mask.h73 #define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x2
76 #define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x2
94 #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2
98 #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2
H A Dvce_3_0_sh_mask.h89 #define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x2
92 #define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x2
110 #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2
114 #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2
/linux-4.4.14/drivers/gpu/drm/cirrus/
H A Dcirrus_fbdev.c31 int x2, y2; cirrus_dirty_update() local
50 x2 = x + width - 1; cirrus_dirty_update()
60 if (afbdev->x2 > x2) cirrus_dirty_update()
61 x2 = afbdev->x2; cirrus_dirty_update()
65 afbdev->x2 = x2; cirrus_dirty_update()
73 afbdev->x2 = afbdev->y2 = 0; cirrus_dirty_update()
/linux-4.4.14/drivers/crypto/ux500/cryp/
H A Dcryp_irq.h18 CRYP_IRQ_SRC_OUTPUT_FIFO = 0x2,
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A DM0203.h16 #define M0203E_TYPE_GDDR3 0x2
/linux-4.4.14/arch/cris/include/asm/
H A Detraxi2c.h24 #define I2C_READREG 0x2 /* read from an i2c register */
/linux-4.4.14/arch/arm/include/debug/
H A Dvt8500.S30 ands \rd, \rd, #0x2
/linux-4.4.14/arch/arm/mach-davinci/include/mach/
H A Dtime.h26 #define IS_TIMER1(id) (id & 0x2)
/linux-4.4.14/include/linux/
H A Djz4740-adc.h22 #define JZ_ADC_CONFIG_XYZ_MASK (0x2 << 13)
H A Dleds-lp3944.h29 LP3944_LED_STATUS_DIM0 = 0x2,
/linux-4.4.14/drivers/isdn/hisax/
H A Disac.h46 #define ISAC_CMD_SSZ 0x2
55 #define ISAC_IND_SD 0x2
/linux-4.4.14/drivers/mmc/host/
H A Dsdhci-s3c-regs.h45 #define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
82 #define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
/linux-4.4.14/arch/x86/kernel/
H A Ddoublefault.c59 /* 0x2 bit is always set */
60 .flags = X86_EFLAGS_SF | 0x2,
/linux-4.4.14/include/scsi/
H A Dosd_attributes.h163 OSD_ATTR_CI_COLLECTION_OBJECT_ID = 0x2, /* 8 */
175 OSD_ATTR_OI_OBJECT_ID = 0x2, /* 8 */
230 OSD_ATTR_RT_ATTRIBUTES_ACCESSED_TIME = 0x2, /* 6 */
247 OSD_ATTR_PT_ATTRIBUTES_ACCESSED_TIME = 0x2, /* 6 */
269 OSD_ATTR_OT_ATTRIBUTES_ACCESSED_TIME = 0x2, /* 6 */
302 OSD_ATTR_RS_OLDEST_VALID_NONCE_LIMIT = 0x2, /* 6 */
333 OSD_ATTR_PS_OLDEST_VALID_NONCE = 0x2, /* 6 */
377 OSD_ATTR_CC_OBJECT_TYPE = 0x2, /* 1 */
/linux-4.4.14/arch/arm/mach-socfpga/
H A Dcore.h33 #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */
35 #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
/linux-4.4.14/drivers/gpu/drm/armada/
H A Darmada_hw.h157 CFG_DSCALE_QUAR = 0x2 << 18,
161 CFG_ALPHAM_CFG = 0x2 << 16,
201 SCLK_510_PLL = 0x2 << 30,
220 DUMB18_RGB666_0 = 0x2 << 28,
252 CFG_IOPAD_DUMB18GPIO = 0x2 << 0,

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