/linux-4.4.14/drivers/media/usb/pvrusb2/ |
H A D | pvrusb2-debugifc.c | 69 const char *wptr; debugifc_isolate_word() local 74 wptr = NULL; debugifc_isolate_word() 82 wptr = buf; debugifc_isolate_word() 87 *wstrPtr = wptr; debugifc_isolate_word() 198 const char *wptr; pvr2_debugifc_do1cmd() local 202 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); pvr2_debugifc_do1cmd() 205 if (!wptr) return 0; pvr2_debugifc_do1cmd() 207 pvr2_trace(PVR2_TRACE_DEBUGIFC,"debugifc cmd: \"%.*s\"",wlen,wptr); pvr2_debugifc_do1cmd() 208 if (debugifc_match_keyword(wptr,wlen,"reset")) { pvr2_debugifc_do1cmd() 209 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); pvr2_debugifc_do1cmd() 212 if (!wptr) return -EINVAL; pvr2_debugifc_do1cmd() 213 if (debugifc_match_keyword(wptr,wlen,"cpu")) { pvr2_debugifc_do1cmd() 217 } else if (debugifc_match_keyword(wptr,wlen,"bus")) { pvr2_debugifc_do1cmd() 219 } else if (debugifc_match_keyword(wptr,wlen,"soft")) { pvr2_debugifc_do1cmd() 221 } else if (debugifc_match_keyword(wptr,wlen,"deep")) { pvr2_debugifc_do1cmd() 223 } else if (debugifc_match_keyword(wptr,wlen,"firmware")) { pvr2_debugifc_do1cmd() 225 } else if (debugifc_match_keyword(wptr,wlen,"decoder")) { pvr2_debugifc_do1cmd() 227 } else if (debugifc_match_keyword(wptr,wlen,"worker")) { pvr2_debugifc_do1cmd() 229 } else if (debugifc_match_keyword(wptr,wlen,"usbstats")) { pvr2_debugifc_do1cmd() 235 } else if (debugifc_match_keyword(wptr,wlen,"cpufw")) { pvr2_debugifc_do1cmd() 236 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); pvr2_debugifc_do1cmd() 239 if (!wptr) return -EINVAL; pvr2_debugifc_do1cmd() 240 if (debugifc_match_keyword(wptr,wlen,"fetch")) { pvr2_debugifc_do1cmd() 241 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); pvr2_debugifc_do1cmd() 242 if (scnt && wptr) { pvr2_debugifc_do1cmd() 244 if (debugifc_match_keyword(wptr, wlen, pvr2_debugifc_do1cmd() 247 } else if (debugifc_match_keyword(wptr, wlen, pvr2_debugifc_do1cmd() 250 } else if (debugifc_match_keyword(wptr, wlen, pvr2_debugifc_do1cmd() 259 } else if (debugifc_match_keyword(wptr,wlen,"done")) { pvr2_debugifc_do1cmd() 265 } else if (debugifc_match_keyword(wptr,wlen,"gpio")) { pvr2_debugifc_do1cmd() 269 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); pvr2_debugifc_do1cmd() 272 if (!wptr) return -EINVAL; pvr2_debugifc_do1cmd() 273 if (debugifc_match_keyword(wptr,wlen,"dir")) { pvr2_debugifc_do1cmd() 275 } else if (!debugifc_match_keyword(wptr,wlen,"out")) { pvr2_debugifc_do1cmd() 278 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); pvr2_debugifc_do1cmd() 281 if (!wptr) return -EINVAL; pvr2_debugifc_do1cmd() 282 ret = debugifc_parse_unsigned_number(wptr,wlen,&msk); pvr2_debugifc_do1cmd() 284 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); pvr2_debugifc_do1cmd() 285 if (wptr) { pvr2_debugifc_do1cmd() 286 ret = debugifc_parse_unsigned_number(wptr,wlen,&val); pvr2_debugifc_do1cmd() 300 "debugifc failed to recognize cmd: \"%.*s\"",wlen,wptr); pvr2_debugifc_do1cmd()
|
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
H A D | cz_ih.c | 40 * host is currently reading, and a wptr (write pointer) 44 * wptr. When there is an interrupt, the host then starts 86 /* set rptr, wptr to 0 */ cz_ih_disable_interrupts() 143 /* set rptr, wptr to 0 */ cz_ih_irq_init() 179 * cz_ih_get_wptr - get the IH ring buffer wptr 183 * Get the IH ring buffer wptr from either the register 187 * Returns the value of the wptr. 191 u32 wptr, tmp; cz_ih_get_wptr() local 193 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); cz_ih_get_wptr() 195 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { cz_ih_get_wptr() 196 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); cz_ih_get_wptr() 198 * from the last not overwritten vector (wptr + 16). Hopefully cz_ih_get_wptr() 202 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); cz_ih_get_wptr() 203 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; cz_ih_get_wptr() 208 return (wptr & adev->irq.ih.ptr_mask); cz_ih_get_wptr() 222 /* wptr/rptr are in bytes! */ cz_ih_decode_iv() 237 /* wptr/rptr are in bytes! */ cz_ih_decode_iv()
|
H A D | iceland_ih.c | 40 * host is currently reading, and a wptr (write pointer) 44 * wptr. When there is an interrupt, the host then starts 86 /* set rptr, wptr to 0 */ iceland_ih_disable_interrupts() 143 /* set rptr, wptr to 0 */ iceland_ih_irq_init() 179 * iceland_ih_get_wptr - get the IH ring buffer wptr 183 * Get the IH ring buffer wptr from either the register 187 * Returns the value of the wptr. 191 u32 wptr, tmp; iceland_ih_get_wptr() local 193 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); iceland_ih_get_wptr() 195 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { iceland_ih_get_wptr() 196 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); iceland_ih_get_wptr() 198 * from the last not overwritten vector (wptr + 16). Hopefully iceland_ih_get_wptr() 202 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); iceland_ih_get_wptr() 203 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; iceland_ih_get_wptr() 208 return (wptr & adev->irq.ih.ptr_mask); iceland_ih_get_wptr() 222 /* wptr/rptr are in bytes! */ iceland_ih_decode_iv() 237 /* wptr/rptr are in bytes! */ iceland_ih_decode_iv()
|
H A D | cik_ih.c | 40 * host is currently reading, and a wptr (write pointer) 44 * wptr. When there is an interrupt, the host then starts 86 /* set rptr, wptr to 0 */ cik_ih_disable_interrupts() 141 /* set rptr, wptr to 0 */ cik_ih_irq_init() 177 * cik_ih_get_wptr - get the IH ring buffer wptr 181 * Get the IH ring buffer wptr from either the register 185 * Returns the value of the wptr. 189 u32 wptr, tmp; cik_ih_get_wptr() local 191 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); cik_ih_get_wptr() 193 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { cik_ih_get_wptr() 194 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; cik_ih_get_wptr() 196 * from the last not overwritten vector (wptr + 16). Hopefully cik_ih_get_wptr() 200 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); cik_ih_get_wptr() 201 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; cik_ih_get_wptr() 206 return (wptr & adev->irq.ih.ptr_mask); cik_ih_get_wptr() 243 /* wptr/rptr are in bytes! */ cik_ih_decode_iv() 258 /* wptr/rptr are in bytes! */ cik_ih_decode_iv()
|
H A D | tonga_ih.c | 40 * host is currently reading, and a wptr (write pointer) 44 * wptr. When there is an interrupt, the host then starts 82 /* set rptr, wptr to 0 */ tonga_ih_disable_interrupts() 147 /* set rptr, wptr to 0 */ tonga_ih_irq_init() 187 * tonga_ih_get_wptr - get the IH ring buffer wptr 191 * Get the IH ring buffer wptr from either the register 195 * Returns the value of the wptr. 199 u32 wptr, tmp; tonga_ih_get_wptr() local 202 wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); tonga_ih_get_wptr() 204 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); tonga_ih_get_wptr() 206 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { tonga_ih_get_wptr() 207 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); tonga_ih_get_wptr() 209 * from the last not overwritten vector (wptr + 16). Hopefully tonga_ih_get_wptr() 213 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); tonga_ih_get_wptr() 214 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; tonga_ih_get_wptr() 219 return (wptr & adev->irq.ih.ptr_mask); tonga_ih_get_wptr() 233 /* wptr/rptr are in bytes! */ tonga_ih_decode_iv() 248 /* wptr/rptr are in bytes! */ tonga_ih_decode_iv()
|
H A D | amdgpu_ih.c | 98 /* add 8 bytes for the rptr/wptr shadows and amdgpu_ih_ring_init() 143 /* add 8 bytes for the rptr/wptr shadows and amdgpu_ih_ring_fini() 179 u32 wptr; amdgpu_ih_process() local 184 wptr = amdgpu_ih_get_wptr(adev); amdgpu_ih_process() 191 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr); amdgpu_ih_process() 193 /* Order reading of wptr vs. reading of IH ring data */ amdgpu_ih_process() 196 while (adev->irq.ih.rptr != wptr) { amdgpu_ih_process() 213 /* make sure wptr hasn't changed while processing */ amdgpu_ih_process() 214 wptr = amdgpu_ih_get_wptr(adev); amdgpu_ih_process() 215 if (wptr != adev->irq.ih.rptr) amdgpu_ih_process()
|
H A D | amdgpu_ring.c | 42 * GPU is currently reading, and a wptr (write pointer) 46 * wptr. The GPU then starts fetching commands and executes 65 ring->ring_free_dw -= ring->wptr; amdgpu_ring_free_size() 104 ring->wptr_old = ring->wptr; amdgpu_ring_alloc() 154 * Update the wptr (write pointer) to tell the GPU to 162 count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); amdgpu_ring_commit() 185 * amdgpu_ring_undo - reset the wptr 189 * Reset the driver's copy of the wptr (all asics). 193 ring->wptr = ring->wptr_old; amdgpu_ring_undo() 197 * amdgpu_ring_unlock_undo - reset the wptr and unlock the ring 238 size = ring->wptr + (ring->ring_size / 4); amdgpu_ring_backup() 476 uint32_t rptr, wptr, rptr_next; amdgpu_debugfs_ring_info() local 482 wptr = amdgpu_ring_get_wptr(ring); amdgpu_debugfs_ring_info() 483 seq_printf(m, "wptr: 0x%08x [%5d]\n", amdgpu_debugfs_ring_info() 484 wptr, wptr); amdgpu_debugfs_ring_info() 492 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", amdgpu_debugfs_ring_info() 493 ring->wptr, ring->wptr); amdgpu_debugfs_ring_info()
|
H A D | vce_v2_0.c | 94 WREG32(mmVCE_RB_WPTR, ring->wptr); vce_v2_0_ring_set_wptr() 96 WREG32(mmVCE_RB_WPTR2, ring->wptr); vce_v2_0_ring_set_wptr() 117 WREG32(mmVCE_RB_RPTR, ring->wptr); vce_v2_0_start() 118 WREG32(mmVCE_RB_WPTR, ring->wptr); vce_v2_0_start() 124 WREG32(mmVCE_RB_RPTR2, ring->wptr); vce_v2_0_start() 125 WREG32(mmVCE_RB_WPTR2, ring->wptr); vce_v2_0_start()
|
H A D | vce_v3_0.c | 101 WREG32(mmVCE_RB_WPTR, ring->wptr); vce_v3_0_ring_set_wptr() 103 WREG32(mmVCE_RB_WPTR2, ring->wptr); vce_v3_0_ring_set_wptr() 188 WREG32(mmVCE_RB_RPTR, ring->wptr); vce_v3_0_start() 189 WREG32(mmVCE_RB_WPTR, ring->wptr); vce_v3_0_start() 195 WREG32(mmVCE_RB_RPTR2, ring->wptr); vce_v3_0_start() 196 WREG32(mmVCE_RB_WPTR2, ring->wptr); vce_v3_0_start()
|
H A D | sdma_v3_0.c | 293 * Get the current wptr from the hardware (VI+). 298 u32 wptr; sdma_v3_0_ring_get_wptr() local 302 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; sdma_v3_0_ring_get_wptr() 306 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; sdma_v3_0_ring_get_wptr() 309 return wptr; sdma_v3_0_ring_get_wptr() 317 * Write the wptr back to the hardware (VI+). 325 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2; sdma_v3_0_ring_set_wptr() 326 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); sdma_v3_0_ring_set_wptr() 330 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); sdma_v3_0_ring_set_wptr() 359 u32 next_rptr = ring->wptr + 5; sdma_v3_0_ring_emit_ib() 373 sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); sdma_v3_0_ring_emit_ib() 627 ring->wptr = 0; sdma_v3_0_gfx_resume() 628 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); sdma_v3_0_gfx_resume()
|
H A D | sdma_v2_4.c | 197 * Get the current wptr from the hardware (VI+). 203 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; sdma_v2_4_ring_get_wptr() local 205 return wptr; sdma_v2_4_ring_get_wptr() 213 * Write the wptr back to the hardware (VI+). 220 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); sdma_v2_4_ring_set_wptr() 248 u32 next_rptr = ring->wptr + 5; sdma_v2_4_ring_emit_ib() 263 sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); sdma_v2_4_ring_emit_ib() 490 ring->wptr = 0; sdma_v2_4_gfx_resume() 491 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); sdma_v2_4_gfx_resume()
|
H A D | cik_sdma.c | 166 * Get the current wptr from the hardware (CIK+). 181 * Write the wptr back to the hardware (CIK+). 188 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); cik_sdma_ring_set_wptr() 216 u32 next_rptr = ring->wptr + 5; cik_sdma_ring_emit_ib() 229 cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8); cik_sdma_ring_emit_ib() 447 ring->wptr = 0; cik_sdma_gfx_resume() 448 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); cik_sdma_gfx_resume()
|
H A D | amdgpu_amdkfd_gfx_v7.c | 100 uint32_t queue_id, uint32_t __user *wptr); 303 uint32_t queue_id, uint32_t __user *wptr) kgd_hqd_load() 311 is_wptr_shadow_valid = !get_user(wptr_shadow, wptr); kgd_hqd_load() 302 kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr) kgd_hqd_load() argument
|
H A D | amdgpu_amdkfd_gfx_v8.c | 59 uint32_t queue_id, uint32_t __user *wptr); 245 uint32_t queue_id, uint32_t __user *wptr) kgd_hqd_load() 253 valid_wptr = copy_from_user(&shadow_wptr, wptr, sizeof(shadow_wptr)); kgd_hqd_load() 244 kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr) kgd_hqd_load() argument
|
H A D | uvd_v4_2.c | 83 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); uvd_v4_2_ring_set_wptr() 370 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); uvd_v4_2_start() 371 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); uvd_v4_2_start()
|
H A D | uvd_v5_0.c | 79 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); uvd_v5_0_ring_set_wptr() 420 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); uvd_v5_0_start() 421 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); uvd_v5_0_start()
|
H A D | uvd_v6_0.c | 79 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); uvd_v6_0_ring_set_wptr() 420 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); uvd_v6_0_start() 421 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); uvd_v6_0_start()
|
H A D | gfx_v7_0.c | 2569 u32 next_rptr = ring->wptr + 5; gfx_v7_0_ring_emit_ib_gfx() 2613 u32 next_rptr = ring->wptr + 5; gfx_v7_0_ring_emit_ib_compute() 2960 ring->wptr = 0; gfx_v7_0_cp_gfx_resume() 2961 WREG32(mmCP_RB0_WPTR, ring->wptr); gfx_v7_0_cp_gfx_resume() 3002 u32 wptr; gfx_v7_0_ring_get_wptr_gfx() local 3004 wptr = RREG32(mmCP_RB0_WPTR); gfx_v7_0_ring_get_wptr_gfx() 3006 return wptr; gfx_v7_0_ring_get_wptr_gfx() 3013 WREG32(mmCP_RB0_WPTR, ring->wptr); gfx_v7_0_ring_set_wptr_gfx() 3028 u32 wptr; gfx_v7_0_ring_get_wptr_compute() local 3031 wptr = ring->adev->wb.wb[ring->wptr_offs]; gfx_v7_0_ring_get_wptr_compute() 3033 return wptr; gfx_v7_0_ring_get_wptr_compute() 3041 adev->wb.wb[ring->wptr_offs] = ring->wptr; gfx_v7_0_ring_set_wptr_compute() 3042 WDOORBELL32(ring->doorbell_index, ring->wptr); gfx_v7_0_ring_set_wptr_compute() 3418 /* disable wptr polling */ gfx_v7_0_cp_compute_resume() 3529 ring->wptr = 0; gfx_v7_0_cp_compute_resume() 3530 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr; gfx_v7_0_cp_compute_resume()
|
H A D | gfx_v8_0.c | 3324 ring->wptr = 0; gfx_v8_0_cp_gfx_resume() 3325 WREG32(mmCP_RB0_WPTR, ring->wptr); gfx_v8_0_cp_gfx_resume() 3817 /* disable wptr polling */ gfx_v8_0_cp_compute_resume() 3931 ring->wptr = 0; gfx_v8_0_cp_compute_resume() 3932 mqd->cp_hqd_pq_wptr = ring->wptr; gfx_v8_0_cp_compute_resume() 4485 u32 wptr; gfx_v8_0_ring_get_wptr_gfx() local 4489 wptr = ring->adev->wb.wb[ring->wptr_offs]; gfx_v8_0_ring_get_wptr_gfx() 4491 wptr = RREG32(mmCP_RB0_WPTR); gfx_v8_0_ring_get_wptr_gfx() 4493 return wptr; gfx_v8_0_ring_get_wptr_gfx() 4502 adev->wb.wb[ring->wptr_offs] = ring->wptr; gfx_v8_0_ring_set_wptr_gfx() 4503 WDOORBELL32(ring->doorbell_index, ring->wptr); gfx_v8_0_ring_set_wptr_gfx() 4505 WREG32(mmCP_RB0_WPTR, ring->wptr); gfx_v8_0_ring_set_wptr_gfx() 4547 u32 next_rptr = ring->wptr + 5; gfx_v8_0_ring_emit_ib_gfx() 4591 u32 next_rptr = ring->wptr + 5; gfx_v8_0_ring_emit_ib_compute() 4761 adev->wb.wb[ring->wptr_offs] = ring->wptr; gfx_v8_0_ring_set_wptr_compute() 4762 WDOORBELL32(ring->doorbell_index, ring->wptr); gfx_v8_0_ring_set_wptr_compute()
|
H A D | amdgpu.h | 855 unsigned wptr; member in struct:amdgpu_ring 2205 ring->ring[ring->wptr++] = v; amdgpu_ring_write() 2206 ring->wptr &= ring->ptr_mask; amdgpu_ring_write()
|
/linux-4.4.14/drivers/gpu/drm/amd/amdkfd/ |
H A D | kfd_kernel_queue.c | 208 uint32_t wptr, rptr; acquire_packet_buffer() local 214 wptr = *kq->wptr_kernel; acquire_packet_buffer() 219 pr_debug("wptr: %d\n", wptr); acquire_packet_buffer() 222 available_size = (rptr - 1 - wptr + queue_size_dwords) % acquire_packet_buffer() 235 if (wptr + packet_size_in_dwords >= queue_size_dwords) { acquire_packet_buffer() 236 while (wptr > 0) { acquire_packet_buffer() 237 queue_address[wptr] = kq->nop_packet; acquire_packet_buffer() 238 wptr = (wptr + 1) % queue_size_dwords; acquire_packet_buffer() 242 *buffer_ptr = &queue_address[wptr]; acquire_packet_buffer() 243 kq->pending_wptr = wptr + packet_size_in_dwords; acquire_packet_buffer()
|
H A D | kfd_interrupt.c | 111 unsigned int wptr = atomic_read(&kfd->interrupt_ring_wptr); enqueue_ih_ring_entry() local 113 if ((rptr - wptr) % kfd->interrupt_ring_size == enqueue_ih_ring_entry() 121 memcpy(kfd->interrupt_ring + wptr, ih_ring_entry, enqueue_ih_ring_entry() 124 wptr = (wptr + kfd->device_info->ih_ring_entry_size) % enqueue_ih_ring_entry() 126 smp_wmb(); /* Ensure memcpy'd data is visible before wptr update. */ enqueue_ih_ring_entry() 127 atomic_set(&kfd->interrupt_ring_wptr, wptr); enqueue_ih_ring_entry() 143 unsigned int wptr = atomic_read(&kfd->interrupt_ring_wptr); dequeue_ih_ring_entry() local 146 if (rptr == wptr) dequeue_ih_ring_entry()
|
H A D | kfd_mqd_manager_cik.c | 153 uint32_t queue_id, uint32_t __user *wptr) load_mqd() 156 (mm->dev->kgd, mqd, pipe_id, queue_id, wptr); load_mqd() 161 uint32_t __user *wptr) load_mqd_sdma() 152 load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr) load_mqd() argument 159 load_mqd_sdma(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr) load_mqd_sdma() argument
|
H A D | kfd_kernel_queue.h | 51 * packet for some reason. It just overwrites the pending wptr with the current
|
H A D | kfd_mqd_manager.h | 70 uint32_t __user *wptr);
|
H A D | kfd_mqd_manager_vi.c | 95 uint32_t __user *wptr) load_mqd() 98 (mm->dev->kgd, mqd, pipe_id, queue_id, wptr); load_mqd() 93 load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr) load_mqd() argument
|
H A D | kfd_packet_manager.c | 33 static inline void inc_wptr(unsigned int *wptr, unsigned int increment_bytes, inc_wptr() argument 36 unsigned int temp = *wptr + increment_bytes / sizeof(uint32_t); inc_wptr() 39 *wptr = temp; inc_wptr()
|
H A D | kfd_doorbell.c | 41 * receives 32-bit writes that are passed to queues as wptr values.
|
/linux-4.4.14/drivers/gpu/drm/radeon/ |
H A D | radeon_ring.c | 38 * GPU is currently reading, and a wptr (write pointer) 42 * wptr. The GPU then starts fetching commands and executes 84 ring->ring_free_dw -= ring->wptr; radeon_ring_free_size() 125 ring->wptr_old = ring->wptr; radeon_ring_alloc() 161 * Update the wptr (write pointer) to tell the GPU to 173 while (ring->wptr & ring->align_mask) { radeon_ring_commit() 203 * radeon_ring_undo - reset the wptr 207 * Reset the driver's copy of the wptr (all asics). 211 ring->wptr = ring->wptr_old; radeon_ring_undo() 215 * radeon_ring_unlock_undo - reset the wptr and unlock the ring 308 size = ring->wptr + (ring->ring_size / 4); radeon_ring_backup() 468 uint32_t rptr, wptr, rptr_next; radeon_debugfs_ring_info() local 474 wptr = radeon_ring_get_wptr(rdev, ring); radeon_debugfs_ring_info() 475 seq_printf(m, "wptr: 0x%08x [%5d]\n", radeon_debugfs_ring_info() 476 wptr, wptr); radeon_debugfs_ring_info() 489 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", radeon_debugfs_ring_info() 490 ring->wptr, ring->wptr); radeon_debugfs_ring_info()
|
H A D | vce_v1_0.c | 97 WREG32(VCE_RB_WPTR, ring->wptr); vce_v1_0_set_wptr() 99 WREG32(VCE_RB_WPTR2, ring->wptr); vce_v1_0_set_wptr() 298 WREG32(VCE_RB_RPTR, ring->wptr); vce_v1_0_start() 299 WREG32(VCE_RB_WPTR, ring->wptr); vce_v1_0_start() 305 WREG32(VCE_RB_RPTR2, ring->wptr); vce_v1_0_start() 306 WREG32(VCE_RB_WPTR2, ring->wptr); vce_v1_0_start()
|
H A D | ni_dma.c | 78 * Get the current wptr from the hardware (cayman+). 99 * Write the wptr back to the hardware (cayman+). 111 WREG32(reg, (ring->wptr << 2) & 0x3fffc); cayman_dma_set_wptr() 129 u32 next_rptr = ring->wptr + 4; cayman_dma_ring_ib_execute() 142 while ((ring->wptr & 7) != 5) cayman_dma_ring_ib_execute() 243 ring->wptr = 0; cayman_dma_resume() 244 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2); cayman_dma_resume()
|
H A D | r600_dma.c | 70 * Get the current wptr from the hardware (r6xx+). 84 * Write the wptr back to the hardware (r6xx+). 89 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); r600_dma_set_wptr() 167 ring->wptr = 0; r600_dma_resume() 168 WREG32(DMA_RB_WPTR, ring->wptr << 2); r600_dma_resume() 405 u32 next_rptr = ring->wptr + 4; r600_dma_ring_ib_execute() 418 while ((ring->wptr & 7) != 5) r600_dma_ring_ib_execute()
|
H A D | evergreen_dma.c | 73 u32 next_rptr = ring->wptr + 4; evergreen_dma_ring_ib_execute() 86 while ((ring->wptr & 7) != 5) evergreen_dma_ring_ib_execute()
|
H A D | uvd_v1_0.c | 70 WREG32(UVD_RBC_RB_WPTR, ring->wptr); uvd_v1_0_set_wptr() 369 ring->wptr = RREG32(UVD_RBC_RB_RPTR); uvd_v1_0_start() 370 WREG32(UVD_RBC_RB_WPTR, ring->wptr); uvd_v1_0_start()
|
H A D | r600.c | 2627 u32 wptr; r600_gfx_get_wptr() local 2629 wptr = RREG32(R600_CP_RB_WPTR); r600_gfx_get_wptr() 2631 return wptr; r600_gfx_get_wptr() 2637 WREG32(R600_CP_RB_WPTR, ring->wptr); r600_gfx_set_wptr() 2741 ring->wptr = 0; r600_cp_resume() 2742 WREG32(CP_RB_WPTR, ring->wptr); r600_cp_resume() 3332 next_rptr = ring->wptr + 3 + 4; r600_ring_ib_execute() 3338 next_rptr = ring->wptr + 5 + 4; r600_ring_ib_execute() 3416 * increments the rptr. When the rptr catches up with the wptr, all the 3565 /* set rptr, wptr to 0 */ r600_disable_interrupts() 3677 /* set rptr, wptr to 0 */ r600_irq_init() 3993 u32 wptr, tmp; r600_get_ih_wptr() local 3996 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); r600_get_ih_wptr() 3998 wptr = RREG32(IH_RB_WPTR); r600_get_ih_wptr() 4000 if (wptr & RB_OVERFLOW) { r600_get_ih_wptr() 4001 wptr &= ~RB_OVERFLOW; r600_get_ih_wptr() 4003 * from the last not overwritten vector (wptr + 16). Hopefully r600_get_ih_wptr() 4007 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); r600_get_ih_wptr() 4008 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; r600_get_ih_wptr() 4013 return (wptr & rdev->ih.ptr_mask); r600_get_ih_wptr() 4048 u32 wptr; r600_irq_process() local 4063 wptr = r600_get_ih_wptr(rdev); r600_irq_process() 4071 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); r600_irq_process() 4073 /* Order reading of wptr vs. reading of IH ring data */ r600_irq_process() 4079 while (rptr != wptr) { r600_irq_process() 4080 /* wptr/rptr are in bytes! */ r600_irq_process() 4273 /* wptr/rptr are in bytes! */ r600_irq_process() 4287 /* make sure wptr hasn't changed while processing */ r600_irq_process() 4288 wptr = r600_get_ih_wptr(rdev); r600_irq_process() 4289 if (wptr != rptr) r600_irq_process()
|
H A D | cik_sdma.c | 88 * Get the current wptr from the hardware (CIK+). 109 * Write the wptr back to the hardware (CIK+). 121 WREG32(reg, (ring->wptr << 2) & 0x3fffc); cik_sdma_set_wptr() 140 u32 next_rptr = ring->wptr + 5; cik_sdma_ring_ib_execute() 152 while ((ring->wptr & 7) != 4) cik_sdma_ring_ib_execute() 411 ring->wptr = 0; cik_sdma_gfx_resume() 412 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); cik_sdma_gfx_resume()
|
H A D | cik.c | 4156 next_rptr = ring->wptr + 3 + 4; cik_ring_ib_execute() 4162 next_rptr = ring->wptr + 5 + 4; cik_ring_ib_execute() 4493 ring->wptr = 0; cik_cp_gfx_resume() 4494 WREG32(CP_RB0_WPTR, ring->wptr); cik_cp_gfx_resume() 4544 u32 wptr; cik_gfx_get_wptr() local 4546 wptr = RREG32(CP_RB0_WPTR); cik_gfx_get_wptr() 4548 return wptr; cik_gfx_get_wptr() 4554 WREG32(CP_RB0_WPTR, ring->wptr); cik_gfx_set_wptr() 4579 u32 wptr; cik_compute_get_wptr() local 4583 wptr = rdev->wb.wb[ring->wptr_offs/4]; cik_compute_get_wptr() 4587 wptr = RREG32(CP_HQD_PQ_WPTR); cik_compute_get_wptr() 4592 return wptr; cik_compute_get_wptr() 4599 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; cik_compute_set_wptr() 4600 WDOORBELL32(ring->doorbell_index, ring->wptr); cik_compute_set_wptr() 4609 /* Disable wptr polling. */ cik_compute_stop() 5022 /* disable wptr polling */ cik_cp_compute_resume() 5130 rdev->ring[idx].wptr = 0; cik_cp_compute_resume() 5131 mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr; cik_cp_compute_resume() 7241 * host is currently reading, and a wptr (write pointer) 7245 * wptr. When there is an interrupt, the host then starts 7285 /* set rptr, wptr to 0 */ cik_disable_interrupts() 7429 /* set rptr, wptr to 0 */ cik_irq_init() 7847 * cik_get_ih_wptr - get the IH ring buffer wptr 7851 * Get the IH ring buffer wptr from either the register 7855 * Returns the value of the wptr. 7859 u32 wptr, tmp; cik_get_ih_wptr() local 7862 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); cik_get_ih_wptr() 7864 wptr = RREG32(IH_RB_WPTR); cik_get_ih_wptr() 7866 if (wptr & RB_OVERFLOW) { cik_get_ih_wptr() 7867 wptr &= ~RB_OVERFLOW; cik_get_ih_wptr() 7869 * from the last not overwritten vector (wptr + 16). Hopefully cik_get_ih_wptr() 7873 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); cik_get_ih_wptr() 7874 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; cik_get_ih_wptr() 7879 return (wptr & rdev->ih.ptr_mask); cik_get_ih_wptr() 7918 u32 wptr; cik_irq_process() local 7932 wptr = cik_get_ih_wptr(rdev); cik_irq_process() 7940 DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr); cik_irq_process() 7942 /* Order reading of wptr vs. reading of IH ring data */ cik_irq_process() 7948 while (rptr != wptr) { cik_irq_process() 7949 /* wptr/rptr are in bytes! */ cik_irq_process() 8463 /* wptr/rptr are in bytes! */ cik_irq_process() 8481 /* make sure wptr hasn't changed while processing */ cik_irq_process() 8482 wptr = cik_get_ih_wptr(rdev); cik_irq_process() 8483 if (wptr != rptr) cik_irq_process()
|
H A D | evergreen.c | 3029 next_rptr = ring->wptr + 3 + 4; evergreen_ring_ib_execute() 3035 next_rptr = ring->wptr + 5 + 4; evergreen_ring_ib_execute() 3187 ring->wptr = 0; evergreen_cp_resume() 3188 WREG32(CP_RB_WPTR, ring->wptr); evergreen_cp_resume() 5012 u32 wptr, tmp; evergreen_get_ih_wptr() local 5015 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); evergreen_get_ih_wptr() 5017 wptr = RREG32(IH_RB_WPTR); evergreen_get_ih_wptr() 5019 if (wptr & RB_OVERFLOW) { evergreen_get_ih_wptr() 5020 wptr &= ~RB_OVERFLOW; evergreen_get_ih_wptr() 5022 * from the last not overwritten vector (wptr + 16). Hopefully evergreen_get_ih_wptr() 5026 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); evergreen_get_ih_wptr() 5027 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; evergreen_get_ih_wptr() 5032 return (wptr & rdev->ih.ptr_mask); evergreen_get_ih_wptr() 5037 u32 wptr; evergreen_irq_process() local 5050 wptr = evergreen_get_ih_wptr(rdev); evergreen_irq_process() 5058 DRM_DEBUG("evergreen_irq_process start: rptr %d, wptr %d\n", rptr, wptr); evergreen_irq_process() 5060 /* Order reading of wptr vs. reading of IH ring data */ evergreen_irq_process() 5066 while (rptr != wptr) { evergreen_irq_process() 5067 /* wptr/rptr are in bytes! */ evergreen_irq_process() 5494 /* wptr/rptr are in bytes! */ evergreen_irq_process() 5510 /* make sure wptr hasn't changed while processing */ evergreen_irq_process() 5511 wptr = evergreen_get_ih_wptr(rdev); evergreen_irq_process() 5512 if (wptr != rptr) evergreen_irq_process()
|
H A D | ni.c | 1443 uint32_t next_rptr = ring->wptr + 3 + 4 + 8; cayman_ring_ib_execute() 1502 u32 wptr; cayman_gfx_get_wptr() local 1505 wptr = RREG32(CP_RB0_WPTR); cayman_gfx_get_wptr() 1507 wptr = RREG32(CP_RB1_WPTR); cayman_gfx_get_wptr() 1509 wptr = RREG32(CP_RB2_WPTR); cayman_gfx_get_wptr() 1511 return wptr; cayman_gfx_get_wptr() 1518 WREG32(CP_RB0_WPTR, ring->wptr); cayman_gfx_set_wptr() 1521 WREG32(CP_RB1_WPTR, ring->wptr); cayman_gfx_set_wptr() 1524 WREG32(CP_RB2_WPTR, ring->wptr); cayman_gfx_set_wptr() 1724 ring->wptr = 0; cayman_cp_resume() 1726 WREG32(cp_rb_wptr[i], ring->wptr); cayman_cp_resume()
|
H A D | si.c | 3416 next_rptr = ring->wptr + 3 + 4 + 8; si_ring_ib_execute() 3422 next_rptr = ring->wptr + 5 + 4 + 8; si_ring_ib_execute() 3675 ring->wptr = 0; si_cp_resume() 3676 WREG32(CP_RB0_WPTR, ring->wptr); si_cp_resume() 3706 ring->wptr = 0; si_cp_resume() 3707 WREG32(CP_RB1_WPTR, ring->wptr); si_cp_resume() 3730 ring->wptr = 0; si_cp_resume() 3731 WREG32(CP_RB2_WPTR, ring->wptr); si_cp_resume() 5928 /* set rptr, wptr to 0 */ si_disable_interrupts() 6043 /* set rptr, wptr to 0 */ si_irq_init() 6398 u32 wptr, tmp; si_get_ih_wptr() local 6401 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); si_get_ih_wptr() 6403 wptr = RREG32(IH_RB_WPTR); si_get_ih_wptr() 6405 if (wptr & RB_OVERFLOW) { si_get_ih_wptr() 6406 wptr &= ~RB_OVERFLOW; si_get_ih_wptr() 6408 * from the last not overwritten vector (wptr + 16). Hopefully si_get_ih_wptr() 6412 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); si_get_ih_wptr() 6413 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; si_get_ih_wptr() 6418 return (wptr & rdev->ih.ptr_mask); si_get_ih_wptr() 6433 u32 wptr; si_irq_process() local 6445 wptr = si_get_ih_wptr(rdev); si_irq_process() 6453 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr); si_irq_process() 6455 /* Order reading of wptr vs. reading of IH ring data */ si_irq_process() 6461 while (rptr != wptr) { si_irq_process() 6462 /* wptr/rptr are in bytes! */ si_irq_process() 6846 /* wptr/rptr are in bytes! */ si_irq_process() 6860 /* make sure wptr hasn't changed while processing */ si_irq_process() 6861 wptr = si_get_ih_wptr(rdev); si_irq_process() 6862 if (wptr != rptr) si_irq_process()
|
H A D | radeon_kfd.c | 78 uint32_t queue_id, uint32_t __user *wptr); 483 uint32_t queue_id, uint32_t __user *wptr) kgd_hqd_load() 490 is_wptr_shadow_valid = !get_user(wptr_shadow, wptr); kgd_hqd_load() 482 kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr) kgd_hqd_load() argument
|
H A D | r100.c | 1072 u32 wptr; r100_gfx_get_wptr() local 1074 wptr = RREG32(RADEON_CP_RB_WPTR); r100_gfx_get_wptr() 1076 return wptr; r100_gfx_get_wptr() 1082 WREG32(RADEON_CP_RB_WPTR, ring->wptr); r100_gfx_set_wptr() 1182 ring->wptr = 0; r100_cp_init() 1183 WREG32(RADEON_CP_RB_WPTR, ring->wptr); r100_cp_init() 2996 seq_printf(m, "Ring wptr %u\n", r_wptr); r100_debugfs_cp_csq_fifo() 2998 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); r100_debugfs_cp_csq_fifo() 3000 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); r100_debugfs_cp_csq_fifo() 3691 u32 next_rptr = ring->wptr + 2 + 3; r100_ring_ib_execute()
|
H A D | radeon.h | 854 unsigned wptr; member in struct:radeon_ring 2703 ring->ring[ring->wptr++] = v; radeon_ring_write() 2704 ring->wptr &= ring->ptr_mask; radeon_ring_write()
|
/linux-4.4.14/drivers/gpu/drm/msm/adreno/ |
H A D | adreno_gpu.c | 112 adreno_gpu->memptrs->wptr = 0; adreno_recover() 207 uint32_t wptr = get_wptr(gpu->rb); adreno_flush() local 212 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); adreno_flush() 218 uint32_t wptr = get_wptr(gpu->rb); adreno_idle() local 221 if (spin_until(adreno_gpu->memptrs->rptr == wptr)) adreno_idle() 241 seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr); adreno_show() 242 seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb)); adreno_show() 282 printk("wptr: %d\n", adreno_gpu->memptrs->wptr); adreno_dump_info() 283 printk("rb wptr: %d\n", get_wptr(gpu->rb)); adreno_dump_info() 315 uint32_t wptr = get_wptr(gpu->rb); ring_freewords() local 317 return (rptr + (size - 1) - wptr) % size; ring_freewords()
|
H A D | adreno_gpu.h | 132 volatile uint32_t wptr; member in struct:adreno_rbmemptrs 150 /* ringbuffer rptr/wptr: */
|
/linux-4.4.14/drivers/video/fbdev/ |
H A D | maxinefb.c | 67 unsigned char *wptr; maxinefb_ims332_write_register() local 69 wptr = regs + 0xa0000 + (regno << 4); maxinefb_ims332_write_register() 71 *((volatile unsigned short *) (wptr)) = val; maxinefb_ims332_write_register()
|
/linux-4.4.14/drivers/net/ethernet/tehuti/ |
H A D | tehuti.c | 172 f->wptr = 0; bdx_fifo_init() 1116 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); bdx_rx_alloc_skbs() 1124 f->m.wptr += sizeof(struct rxf_desc); bdx_rx_alloc_skbs() 1125 delta = f->m.wptr - f->m.memsz; bdx_rx_alloc_skbs() 1127 f->m.wptr = delta; bdx_rx_alloc_skbs() 1135 /*TBD: to do - delayed rxf wptr like in txd */ bdx_rx_alloc_skbs() 1136 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); bdx_rx_alloc_skbs() 1173 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); bdx_recycle_skb() 1181 f->m.wptr += sizeof(struct rxf_desc); bdx_recycle_skb() 1182 delta = f->m.wptr - f->m.memsz; bdx_recycle_skb() 1184 f->m.wptr = delta; bdx_recycle_skb() 1225 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR; bdx_rx_receive() 1227 size = f->m.wptr - f->m.rptr; bdx_rx_receive() 1384 int taken = db->wptr - db->rptr; bdx_tx_db_size() 1401 *pptr != db->wptr); /* or write pointer */ __bdx_tx_db_ptr_next() 1417 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */ bdx_tx_db_inc_rptr() 1427 __bdx_tx_db_ptr_next(db, &db->wptr); bdx_tx_db_inc_wptr() 1428 BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as bdx_tx_db_inc_wptr() 1450 * avoid rptr == wptr which means db is empty bdx_tx_db_init() 1457 d->wptr = d->start; bdx_tx_db_init() 1506 db->wptr->len = skb_headlen(skb); bdx_tx_map_skb() 1507 db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data, bdx_tx_map_skb() 1508 db->wptr->len, PCI_DMA_TODEVICE); bdx_tx_map_skb() 1509 pbl->len = CPU_CHIP_SWAP32(db->wptr->len); bdx_tx_map_skb() 1510 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma)); bdx_tx_map_skb() 1511 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma)); bdx_tx_map_skb() 1521 db->wptr->len = skb_frag_size(frag); bdx_tx_map_skb() 1522 db->wptr->addr.dma = skb_frag_dma_map(&priv->pdev->dev, frag, bdx_tx_map_skb() 1527 pbl->len = CPU_CHIP_SWAP32(db->wptr->len); bdx_tx_map_skb() 1528 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma)); bdx_tx_map_skb() 1529 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma)); bdx_tx_map_skb() 1534 db->wptr->len = -txd_sizes[nr_frags].bytes; bdx_tx_map_skb() 1535 db->wptr->addr.skb = skb; bdx_tx_map_skb() 1598 fsize = f->m.rptr - f->m.wptr; bdx_tx_space() 1641 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */ bdx_tx_transmit() 1642 txdd = (struct txd_desc *)(f->m.va + f->m.wptr); bdx_tx_transmit() 1674 f->m.wptr += txd_sizes[nr_frags].bytes; bdx_tx_transmit() 1675 len = f->m.wptr - f->m.memsz; bdx_tx_transmit() 1677 f->m.wptr = len; bdx_tx_transmit() 1683 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */ bdx_tx_transmit() 1693 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); bdx_tx_transmit() 1698 f->m.wptr & TXF_WPTR_WR_PTR); bdx_tx_transmit() 1706 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); bdx_tx_transmit() 1739 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK; bdx_tx_cleanup() 1742 while (f->m.wptr != f->m.rptr) { bdx_tx_cleanup() 1763 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz); bdx_tx_cleanup() 1775 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR); bdx_tx_cleanup() 1798 while (db->rptr != db->wptr) { bdx_tx_free_skbs() 1833 int i = f->m.memsz - f->m.wptr; bdx_tx_push_desc() 1839 memcpy(f->m.va + f->m.wptr, data, size); bdx_tx_push_desc() 1840 f->m.wptr += size; bdx_tx_push_desc() 1842 memcpy(f->m.va + f->m.wptr, data, i); bdx_tx_push_desc() 1843 f->m.wptr = size - i; bdx_tx_push_desc() 1844 memcpy(f->m.va, data + i, f->m.wptr); bdx_tx_push_desc() 1846 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); bdx_tx_push_desc() 1864 /* we substruct 8 because when fifo is full rptr == wptr bdx_tx_push_desc_safe()
|
H A D | tehuti.h | 146 u32 rptr, wptr; /* cached values of RPTR and WPTR registers, member in struct:fifo 202 struct tx_map *wptr; /* points to the next element to write */ member in struct:txdb
|
/linux-4.4.14/drivers/net/ppp/ |
H A D | bsd_comp.c | 580 unsigned char *wptr; bsd_compress() local 586 if (wptr) \ bsd_compress() 588 *wptr++ = (unsigned char) (v); \ bsd_compress() 591 wptr = NULL; \ bsd_compress() 630 wptr = obuf; bsd_compress() 639 if (wptr) bsd_compress() 641 *wptr++ = PPP_ADDRESS(rptr); bsd_compress() 642 *wptr++ = PPP_CONTROL(rptr); bsd_compress() 643 *wptr++ = 0; bsd_compress() 644 *wptr++ = PPP_COMP; bsd_compress() 645 *wptr++ = db->seqno >> 8; bsd_compress() 646 *wptr++ = db->seqno; bsd_compress() 782 if (wptr == NULL) bsd_compress() 843 unsigned char *wptr; bsd_decompress() local 893 wptr = obuf; bsd_decompress() 894 *wptr++ = adrs; bsd_decompress() 895 *wptr++ = ctrl; bsd_decompress() 896 *wptr++ = 0; bsd_decompress() 994 wptr += codelen; bsd_decompress() 995 p = wptr; bsd_decompress() 1040 *wptr++ = finchar; bsd_decompress()
|
H A D | ppp_deflate.c | 193 unsigned char *wptr; z_compress() local 207 wptr = obuf; z_compress() 212 wptr[0] = PPP_ADDRESS(rptr); z_compress() 213 wptr[1] = PPP_CONTROL(rptr); z_compress() 214 put_unaligned_be16(PPP_COMP, wptr + 2); z_compress() 215 wptr += PPP_HDRLEN; z_compress() 216 put_unaligned_be16(state->seqno, wptr); z_compress() 217 wptr += DEFLATE_OVHD; z_compress() 219 state->strm.next_out = wptr; z_compress()
|
/linux-4.4.14/drivers/infiniband/hw/cxgb3/ |
H A D | cxio_hal.c | 435 PDBG("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n", cxio_flush_hw_cq() 608 PDBG("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n", cxio_hal_ctrl_qp_write_mem() 609 __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len, cxio_hal_ctrl_qp_write_mem() 613 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr, cxio_hal_ctrl_qp_write_mem() 617 rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i); cxio_hal_ctrl_qp_write_mem() 620 rdev_p->ctrl_qp.wptr, cxio_hal_ctrl_qp_write_mem() 629 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % cxio_hal_ctrl_qp_write_mem() 671 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % cxio_hal_ctrl_qp_write_mem() 674 /* wptr in the WRID[31:0] */ cxio_hal_ctrl_qp_write_mem() 675 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr; cxio_hal_ctrl_qp_write_mem() 682 Q_GENBIT(rdev_p->ctrl_qp.wptr, cxio_hal_ctrl_qp_write_mem() 688 rdev_p->ctrl_qp.wptr++; cxio_hal_ctrl_qp_write_mem() 706 u32 wptr; __cxio_tpt_op() local 754 wptr = rdev_p->ctrl_qp.wptr; __cxio_tpt_op() 759 wptr))) __cxio_tpt_op() 767 u32 wptr; cxio_write_pbl() local 777 wptr = rdev_p->ctrl_qp.wptr; cxio_write_pbl() 784 wptr))) cxio_write_pbl() 1120 u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2); advance_oldest_read() local 1122 while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) { advance_oldest_read() 1336 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1))) cxio_poll_cq() 1337 || ((cq->rptr - cq->wptr) >= 128)) { cxio_poll_cq() 1338 *credit = cq->rptr - cq->wptr; cxio_poll_cq() 1339 cq->wptr = cq->rptr; cxio_poll_cq()
|
H A D | cxio_wr.h | 46 #define Q_EMPTY(rptr,wptr) ((rptr)==(wptr)) 47 #define Q_FULL(rptr,wptr,size_log2) ( (((wptr)-(rptr))>>(size_log2)) && \ 48 ((rptr)!=(wptr)) ) 50 #define Q_FREECNT(rptr,wptr,size_log2) ((1UL<<size_log2)-((wptr)-(rptr))) 51 #define Q_COUNT(rptr,wptr) ((wptr)-(rptr)) 697 u32 wptr; /* idx to next available WR slot */ member in struct:t3_wq 718 u32 wptr; member in struct:t3_cq
|
H A D | iwch_qp.c | 176 Q_PTR2IDX((wq->wptr+1), wq->size_log2)); build_memreg() 178 Q_GENBIT(wq->wptr + 1, wq->size_log2), build_memreg() 385 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2); iwch_post_send() 444 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2), iwch_post_send() 453 qhp->wq.wptr += wr_cnt; iwch_post_send() 495 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2); iwch_post_receive() 509 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2), iwch_post_receive() 515 ++(qhp->wq.wptr); iwch_post_receive() 562 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2); iwch_bind_mw() 599 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2), 0, iwch_bind_mw() 601 ++(qhp->wq.wptr); iwch_bind_mw()
|
H A D | cxio_hal.h | 68 u32 wptr; member in struct:cxio_hal_ctrl_qp
|
H A D | iwch_provider.c | 272 if (cqe < Q_COUNT(chp->cq.rptr, chp->cq.wptr)) { iwch_resize_cq()
|
/linux-4.4.14/drivers/staging/media/lirc/ |
H A D | lirc_parallel.c | 85 static unsigned int wptr; variable 210 nwptr = (wptr + 1) & (RBUF_SIZE - 1); rbuf_write() 217 rbuf[wptr] = signal; rbuf_write() 218 wptr = nwptr; rbuf_write() 338 if (rptr != wptr) { lirc_read() 457 if (rptr != wptr) lirc_poll() 524 wptr = 0; lirc_open()
|
/linux-4.4.14/drivers/tty/serial/ |
H A D | men_z135_uart.c | 301 u32 wptr; men_z135_handle_tx() local 323 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); men_z135_handle_tx() 324 txc = (wptr >> 16) & 0x3ff; men_z135_handle_tx() 325 wptr &= 0x3ff; men_z135_handle_tx() 341 if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr)) men_z135_handle_tx() 342 n = 4 - BYTES_TO_ALIGN(wptr); men_z135_handle_tx() 463 u32 wptr; men_z135_tx_empty() local 466 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); men_z135_tx_empty() 467 txc = (wptr >> 16) & 0x3ff; men_z135_tx_empty()
|
/linux-4.4.14/drivers/scsi/qla2xxx/ |
H A D | qla_sup.c | 550 uint16_t cnt, chksum, *wptr; qla2xxx_find_flt_start() local 611 wptr = (uint16_t *)req->ring; qla2xxx_find_flt_start() 614 chksum += le16_to_cpu(*wptr++); qla2xxx_find_flt_start() 668 uint16_t *wptr; qla2xxx_get_flt_info() local 689 wptr = (uint16_t *)req->ring; qla2xxx_get_flt_info() 694 if (*wptr == cpu_to_le16(0xffff)) qla2xxx_get_flt_info() 706 chksum += le16_to_cpu(*wptr++); qla2xxx_get_flt_info() 884 uint16_t *wptr; qla2xxx_get_fdt_info() local 891 wptr = (uint16_t *)req->ring; qla2xxx_get_fdt_info() 895 if (*wptr == cpu_to_le16(0xffff)) qla2xxx_get_fdt_info() 903 chksum += le16_to_cpu(*wptr++); qla2xxx_get_fdt_info() 983 uint32_t *wptr; qla2xxx_get_idc_param() local 990 wptr = (uint32_t *)req->ring; qla2xxx_get_idc_param() 994 if (*wptr == cpu_to_le32(0xffffffff)) { qla2xxx_get_idc_param() 998 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr++); qla2xxx_get_idc_param() 999 ha->fcoe_reset_timeout = le32_to_cpu(*wptr); qla2xxx_get_idc_param() 1035 uint16_t *wptr; qla2xxx_flash_npiv_conf() local 1077 for (wptr = data, chksum = 0; cnt; cnt--) qla2xxx_flash_npiv_conf() 1078 chksum += le16_to_cpu(*wptr++); qla2xxx_flash_npiv_conf() 1325 uint16_t *wptr; qla2x00_read_nvram_data() local 1329 wptr = (uint16_t *)buf; qla2x00_read_nvram_data() 1332 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, qla2x00_read_nvram_data() 1365 uint16_t *wptr; qla2x00_write_nvram_data() local 1377 wptr = (uint16_t *)buf; qla2x00_write_nvram_data() 1380 cpu_to_le16(*wptr)); qla2x00_write_nvram_data() 1381 wptr++; qla2x00_write_nvram_data()
|
H A D | qla_isr.c | 266 uint16_t __iomem *wptr; qla2x00_mbx_completion() local 281 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1); qla2x00_mbx_completion() 285 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8); qla2x00_mbx_completion() 287 ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr); qla2x00_mbx_completion() 289 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); qla2x00_mbx_completion() 291 wptr++; qla2x00_mbx_completion() 304 uint16_t __iomem *wptr; qla81xx_idc_event() local 309 wptr = (uint16_t __iomem *)®24->mailbox1; qla81xx_idc_event() 311 wptr = (uint16_t __iomem *)®82->mailbox_out[1]; qla81xx_idc_event() 315 for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++) qla81xx_idc_event() 316 mb[cnt] = RD_REG_WORD(wptr); qla81xx_idc_event() 2489 uint16_t __iomem *wptr; qla24xx_mbx_completion() local 2504 wptr = (uint16_t __iomem *)®->mailbox1; qla24xx_mbx_completion() 2508 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); qla24xx_mbx_completion() 2511 wptr++; qla24xx_mbx_completion()
|
H A D | qla_mr.c | 2867 uint32_t __iomem *wptr; qlafx00_mbx_completion() local 2877 wptr = (uint32_t __iomem *)®->mailbox17; qlafx00_mbx_completion() 2880 ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr); qlafx00_mbx_completion() 2881 wptr++; qlafx00_mbx_completion()
|
H A D | qla_nx.c | 1987 uint16_t __iomem *wptr; qla82xx_mbx_completion() local 1990 wptr = (uint16_t __iomem *)®->mailbox_out[1]; qla82xx_mbx_completion() 1997 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); qla82xx_mbx_completion() 1998 wptr++; qla82xx_mbx_completion()
|
/linux-4.4.14/drivers/tty/ |
H A D | moxa.c | 275 u16 rptr, wptr, mask, len; moxa_low_water_check() local 279 wptr = readw(ofsAddr + RXwptr); moxa_low_water_check() 281 len = (wptr - rptr) & mask; moxa_low_water_check() 1997 u16 rptr, wptr, mask; MoxaPortTxQueue() local 2000 wptr = readw(ofsAddr + TXwptr); MoxaPortTxQueue() 2002 return (wptr - rptr) & mask; MoxaPortTxQueue() 2008 u16 rptr, wptr, mask; MoxaPortTxFree() local 2011 wptr = readw(ofsAddr + TXwptr); MoxaPortTxFree() 2013 return mask - ((wptr - rptr) & mask); MoxaPortTxFree() 2019 u16 rptr, wptr, mask; MoxaPortRxQueue() local 2022 wptr = readw(ofsAddr + RXwptr); MoxaPortRxQueue() 2024 return (wptr - rptr) & mask; MoxaPortRxQueue()
|
/linux-4.4.14/drivers/scsi/ |
H A D | qla1280.c | 608 uint16_t *wptr; qla1280_read_nvram() local 620 wptr = (uint16_t *)&ha->nvram; qla1280_read_nvram() 624 *wptr = qla1280_get_nvram_word(ha, cnt); qla1280_read_nvram() 625 chksum += *wptr & 0xff; qla1280_read_nvram() 626 chksum += (*wptr >> 8) & 0xff; qla1280_read_nvram() 627 wptr++; qla1280_read_nvram() 636 *wptr = qla1280_get_nvram_word(ha, cnt); qla1280_read_nvram() 637 chksum += *wptr & 0xff; qla1280_read_nvram() 638 chksum += (*wptr >> 8) & 0xff; qla1280_read_nvram() 639 wptr++; qla1280_read_nvram() 3420 uint16_t *wptr; qla1280_isr() local 3441 wptr = &mailbox[0]; qla1280_isr() 3442 *wptr++ = RD_REG_WORD(®->mailbox0); qla1280_isr() 3443 *wptr++ = RD_REG_WORD(®->mailbox1); qla1280_isr() 3444 *wptr = RD_REG_WORD(®->mailbox2); qla1280_isr() 3446 wptr++; qla1280_isr() 3447 *wptr++ = RD_REG_WORD(®->mailbox3); qla1280_isr() 3448 *wptr++ = RD_REG_WORD(®->mailbox4); qla1280_isr() 3449 wptr++; qla1280_isr() 3450 *wptr++ = RD_REG_WORD(®->mailbox6); qla1280_isr() 3451 *wptr = RD_REG_WORD(®->mailbox7); qla1280_isr() 3550 wptr = &mailbox[0]; qla1280_isr() 3551 memcpy((uint16_t *) ha->mailbox_out, wptr, qla1280_isr()
|
/linux-4.4.14/drivers/scsi/qla4xxx/ |
H A D | ql4_nx.c | 3721 uint16_t *wptr; qla4_8xxx_get_flt_info() local 3729 wptr = (uint16_t *)ha->request_ring; qla4_8xxx_get_flt_info() 3744 if (*wptr == __constant_cpu_to_le16(0xffff)) qla4_8xxx_get_flt_info() 3756 chksum += le16_to_cpu(*wptr++); qla4_8xxx_get_flt_info() 3835 uint16_t *wptr; qla4_82xx_get_fdt_info() local 3844 wptr = (uint16_t *)ha->request_ring; qla4_82xx_get_fdt_info() 3849 if (*wptr == __constant_cpu_to_le16(0xffff)) qla4_82xx_get_fdt_info() 3858 chksum += le16_to_cpu(*wptr++); qla4_82xx_get_fdt_info() 3898 uint32_t *wptr; qla4_82xx_get_idc_param() local 3902 wptr = (uint32_t *)ha->request_ring; qla4_82xx_get_idc_param() 3906 if (*wptr == __constant_cpu_to_le32(0xffffffff)) { qla4_82xx_get_idc_param() 3910 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); qla4_82xx_get_idc_param() 3911 ha->nx_reset_timeout = le32_to_cpu(*wptr); qla4_82xx_get_idc_param()
|
/linux-4.4.14/drivers/net/ethernet/micrel/ |
H A D | ks8851_mll.c | 544 * @wptr: buffer address to save data 548 static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len) ks_inblk() argument 552 *wptr++ = (u16)ioread16(ks->hw_addr); ks_inblk() 558 * @wptr: buffer address 562 static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len) ks_outblk() argument 566 iowrite16(*wptr++, ks->hw_addr); ks_outblk()
|
/linux-4.4.14/drivers/gpu/drm/amd/include/ |
H A D | kgd_kfd_interface.h | 151 uint32_t queue_id, uint32_t __user *wptr);
|
/linux-4.4.14/drivers/net/ethernet/sun/ |
H A D | cassini.c | 4162 u32 wptr, rptr; cas_link_timer() local 4174 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR); cas_link_timer() 4176 if ((val == 0) && (wptr != rptr)) { cas_link_timer() 4179 val, wptr, rptr); cas_link_timer()
|
/linux-4.4.14/drivers/net/fddi/skfp/h/ |
H A D | supern_2.h | 339 #define FM_SWPR2 0x6a /* r/w the shadow wptr. for rec. q. 2 */
|