/linux-4.4.14/drivers/net/ethernet/broadcom/bnx2x/ |
H A D | bnx2x_link.c | 1950 u32 wb_data[2]; bnx2x_update_pfc_bmac1() local 1961 wb_data[0] = val; bnx2x_update_pfc_bmac1() 1962 wb_data[1] = 0; bnx2x_update_pfc_bmac1() 1963 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); bnx2x_update_pfc_bmac1() 1971 wb_data[0] = val; bnx2x_update_pfc_bmac1() 1972 wb_data[1] = 0; bnx2x_update_pfc_bmac1() 1973 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); bnx2x_update_pfc_bmac1() 1983 u32 wb_data[2]; bnx2x_update_pfc_bmac2() local 1994 wb_data[0] = val; bnx2x_update_pfc_bmac2() 1995 wb_data[1] = 0; bnx2x_update_pfc_bmac2() 1996 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); bnx2x_update_pfc_bmac2() 2005 wb_data[0] = val; bnx2x_update_pfc_bmac2() 2006 wb_data[1] = 0; bnx2x_update_pfc_bmac2() 2007 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); bnx2x_update_pfc_bmac2() 2012 wb_data[0] = 0x0; bnx2x_update_pfc_bmac2() 2013 wb_data[0] |= (1<<0); /* RX */ bnx2x_update_pfc_bmac2() 2014 wb_data[0] |= (1<<1); /* TX */ bnx2x_update_pfc_bmac2() 2015 wb_data[0] |= (1<<2); /* Force initial Xon */ bnx2x_update_pfc_bmac2() 2016 wb_data[0] |= (1<<3); /* 8 cos */ bnx2x_update_pfc_bmac2() 2017 wb_data[0] |= (1<<5); /* STATS */ bnx2x_update_pfc_bmac2() 2018 wb_data[1] = 0; bnx2x_update_pfc_bmac2() 2020 wb_data, 2); bnx2x_update_pfc_bmac2() 2022 wb_data[0] &= ~(1<<2); bnx2x_update_pfc_bmac2() 2026 wb_data[0] = 0x8; bnx2x_update_pfc_bmac2() 2027 wb_data[1] = 0; bnx2x_update_pfc_bmac2() 2030 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); bnx2x_update_pfc_bmac2() 2041 wb_data[0] = val; bnx2x_update_pfc_bmac2() 2042 wb_data[1] = 0; bnx2x_update_pfc_bmac2() 2044 wb_data, 2); bnx2x_update_pfc_bmac2() 2056 wb_data[0] = val; bnx2x_update_pfc_bmac2() 2057 wb_data[1] = 0; bnx2x_update_pfc_bmac2() 2058 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); bnx2x_update_pfc_bmac2() 2286 u32 wb_data[2]; bnx2x_bmac1_enable() local 2292 wb_data[0] = 0x3c; bnx2x_bmac1_enable() 2293 wb_data[1] = 0; bnx2x_bmac1_enable() 2295 wb_data, 2); bnx2x_bmac1_enable() 2298 wb_data[0] = ((params->mac_addr[2] << 24) | bnx2x_bmac1_enable() 2302 wb_data[1] = ((params->mac_addr[0] << 8) | bnx2x_bmac1_enable() 2304 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); bnx2x_bmac1_enable() 2312 wb_data[0] = val; bnx2x_bmac1_enable() 2313 wb_data[1] = 0; bnx2x_bmac1_enable() 2314 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); bnx2x_bmac1_enable() 2317 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; bnx2x_bmac1_enable() 2318 wb_data[1] = 0; bnx2x_bmac1_enable() 2319 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); bnx2x_bmac1_enable() 2324 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; bnx2x_bmac1_enable() 2325 wb_data[1] = 0; bnx2x_bmac1_enable() 2326 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); bnx2x_bmac1_enable() 2329 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; bnx2x_bmac1_enable() 2330 wb_data[1] = 0; bnx2x_bmac1_enable() 2331 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); bnx2x_bmac1_enable() 2334 wb_data[0] = 0x1000200; bnx2x_bmac1_enable() 2335 wb_data[1] = 0; bnx2x_bmac1_enable() 2337 wb_data, 2); bnx2x_bmac1_enable() 2350 u32 wb_data[2]; bnx2x_bmac2_enable() local 2354 wb_data[0] = 0; bnx2x_bmac2_enable() 2355 wb_data[1] = 0; bnx2x_bmac2_enable() 2356 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); bnx2x_bmac2_enable() 2360 wb_data[0] = 0x3c; bnx2x_bmac2_enable() 2361 wb_data[1] = 0; bnx2x_bmac2_enable() 2363 wb_data, 2); bnx2x_bmac2_enable() 2368 wb_data[0] = ((params->mac_addr[2] << 24) | bnx2x_bmac2_enable() 2372 wb_data[1] = ((params->mac_addr[0] << 8) | bnx2x_bmac2_enable() 2375 wb_data, 2); bnx2x_bmac2_enable() 2380 wb_data[0] = 0x1000200; bnx2x_bmac2_enable() 2381 wb_data[1] = 0; bnx2x_bmac2_enable() 2383 wb_data, 2); bnx2x_bmac2_enable() 2387 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; bnx2x_bmac2_enable() 2388 wb_data[1] = 0; bnx2x_bmac2_enable() 2389 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); bnx2x_bmac2_enable() 2393 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; bnx2x_bmac2_enable() 2394 wb_data[1] = 0; bnx2x_bmac2_enable() 2395 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); bnx2x_bmac2_enable() 2398 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; bnx2x_bmac2_enable() 2399 wb_data[1] = 0; bnx2x_bmac2_enable() 2400 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); bnx2x_bmac2_enable() 2456 u32 wb_data[2]; bnx2x_set_bmac_rx() local 2468 REG_RD_DMAE(bp, bmac_addr, wb_data, 2); bnx2x_set_bmac_rx() 2470 wb_data[0] |= BMAC_CONTROL_RX_ENABLE; bnx2x_set_bmac_rx() 2472 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; bnx2x_set_bmac_rx() 2473 REG_WR_DMAE(bp, bmac_addr, wb_data, 2); bnx2x_set_bmac_rx() 13649 u32 wb_data[2]; bnx2x_check_half_open_conn() local 13658 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); bnx2x_check_half_open_conn() 13659 lss_status = (wb_data[0] > 0); bnx2x_check_half_open_conn()
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H A D | bnx2x_init_ops.h | 878 u32 wb_data[2] = {0, 0}; bnx2x_qm_set_ptr_table() local 882 bnx2x_init_wr_wb(bp, reg + i*8, wb_data, 2); bnx2x_qm_set_ptr_table()
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H A D | bnx2x_main.c | 576 u32 *data = bnx2x_sp(bp, wb_data[0]); bnx2x_write_dmae() 611 u32 *data = bnx2x_sp(bp, wb_data[0]); bnx2x_read_dmae() 630 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); bnx2x_read_dmae() 631 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); bnx2x_read_dmae() 6701 val = *bnx2x_sp(bp, wb_data[0]); bnx2x_int_mem_test() 6757 val = *bnx2x_sp(bp, wb_data[0]); bnx2x_int_mem_test() 7444 val = *bnx2x_sp(bp, wb_data[0]); bnx2x_init_hw_common() 8222 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), bnx2x_init_hw_func() 10384 u32 wb_data[2]; bnx2x_prev_unload_close_mac() local 10397 wb_data[0] = REG_RD(bp, base_addr + offset); bnx2x_prev_unload_close_mac() 10398 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); bnx2x_prev_unload_close_mac() 10400 vals->bmac_val[0] = wb_data[0]; bnx2x_prev_unload_close_mac() 10401 vals->bmac_val[1] = wb_data[1]; bnx2x_prev_unload_close_mac() 10402 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; bnx2x_prev_unload_close_mac() 10403 REG_WR(bp, vals->bmac_addr, wb_data[0]); bnx2x_prev_unload_close_mac() 10404 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); bnx2x_prev_unload_close_mac() 15131 u32 wb_data[2]; bnx2x_cyclecounter_read() local 15135 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2); bnx2x_cyclecounter_read() 15136 phc_cycles = wb_data[1]; bnx2x_cyclecounter_read() 15137 phc_cycles = (phc_cycles << 32) + wb_data[0]; bnx2x_cyclecounter_read() 15324 u32 wb_data[2]; bnx2x_configure_ptp() local 15345 wb_data[0] = 0; bnx2x_configure_ptp() 15346 wb_data[1] = 0; bnx2x_configure_ptp() 15347 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2); bnx2x_configure_ptp()
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H A D | bnx2x.h | 179 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 184 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 185 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 1280 u32 wb_data[4]; member in struct:bnx2x_slowpath
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H A D | bnx2x_sp.c | 803 u32 wb_data[2]; bnx2x_set_mac_in_nig() local 820 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) | bnx2x_set_mac_in_nig() 822 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]); bnx2x_set_mac_in_nig() 824 REG_WR_DMAE(bp, reg_offset, wb_data, 2); bnx2x_set_mac_in_nig()
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