1950 	u32 wb_data[2];  in bnx2x_update_pfc_bmac1()  local
1961 	wb_data[0] = val;  in bnx2x_update_pfc_bmac1()
1962 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac1()
1963 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac1()
1971 	wb_data[0] = val;  in bnx2x_update_pfc_bmac1()
1972 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac1()
1973 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac1()
1983 	u32 wb_data[2];  in bnx2x_update_pfc_bmac2()  local
1994 	wb_data[0] = val;  in bnx2x_update_pfc_bmac2()
1995 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
1996 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac2()
2005 	wb_data[0] = val;  in bnx2x_update_pfc_bmac2()
2006 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2007 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac2()
2012 		wb_data[0] = 0x0;  in bnx2x_update_pfc_bmac2()
2013 		wb_data[0] |= (1<<0);  /* RX */  in bnx2x_update_pfc_bmac2()
2014 		wb_data[0] |= (1<<1);  /* TX */  in bnx2x_update_pfc_bmac2()
2015 		wb_data[0] |= (1<<2);  /* Force initial Xon */  in bnx2x_update_pfc_bmac2()
2016 		wb_data[0] |= (1<<3);  /* 8 cos */  in bnx2x_update_pfc_bmac2()
2017 		wb_data[0] |= (1<<5);  /* STATS */  in bnx2x_update_pfc_bmac2()
2018 		wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2020 			    wb_data, 2);  in bnx2x_update_pfc_bmac2()
2022 		wb_data[0] &= ~(1<<2);  in bnx2x_update_pfc_bmac2()
2026 		wb_data[0] = 0x8;  in bnx2x_update_pfc_bmac2()
2027 		wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2030 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac2()
2041 	wb_data[0] = val;  in bnx2x_update_pfc_bmac2()
2042 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2044 		    wb_data, 2);  in bnx2x_update_pfc_bmac2()
2056 	wb_data[0] = val;  in bnx2x_update_pfc_bmac2()
2057 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2058 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac2()
2286 	u32 wb_data[2];  in bnx2x_bmac1_enable()  local
2292 	wb_data[0] = 0x3c;  in bnx2x_bmac1_enable()
2293 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2295 		    wb_data, 2);  in bnx2x_bmac1_enable()
2298 	wb_data[0] = ((params->mac_addr[2] << 24) |  in bnx2x_bmac1_enable()
2302 	wb_data[1] = ((params->mac_addr[0] << 8) |  in bnx2x_bmac1_enable()
2304 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);  in bnx2x_bmac1_enable()
2312 	wb_data[0] = val;  in bnx2x_bmac1_enable()
2313 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2314 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);  in bnx2x_bmac1_enable()
2317 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;  in bnx2x_bmac1_enable()
2318 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2319 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);  in bnx2x_bmac1_enable()
2324 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;  in bnx2x_bmac1_enable()
2325 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2326 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);  in bnx2x_bmac1_enable()
2329 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;  in bnx2x_bmac1_enable()
2330 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2331 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);  in bnx2x_bmac1_enable()
2334 	wb_data[0] = 0x1000200;  in bnx2x_bmac1_enable()
2335 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2337 		    wb_data, 2);  in bnx2x_bmac1_enable()
2350 	u32 wb_data[2];  in bnx2x_bmac2_enable()  local
2354 	wb_data[0] = 0;  in bnx2x_bmac2_enable()
2355 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2356 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);  in bnx2x_bmac2_enable()
2360 	wb_data[0] = 0x3c;  in bnx2x_bmac2_enable()
2361 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2363 		    wb_data, 2);  in bnx2x_bmac2_enable()
2368 	wb_data[0] = ((params->mac_addr[2] << 24) |  in bnx2x_bmac2_enable()
2372 	wb_data[1] = ((params->mac_addr[0] << 8) |  in bnx2x_bmac2_enable()
2375 		    wb_data, 2);  in bnx2x_bmac2_enable()
2380 	wb_data[0] = 0x1000200;  in bnx2x_bmac2_enable()
2381 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2383 		    wb_data, 2);  in bnx2x_bmac2_enable()
2387 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;  in bnx2x_bmac2_enable()
2388 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2389 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);  in bnx2x_bmac2_enable()
2393 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;  in bnx2x_bmac2_enable()
2394 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2395 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);  in bnx2x_bmac2_enable()
2398 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;  in bnx2x_bmac2_enable()
2399 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2400 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);  in bnx2x_bmac2_enable()
2456 	u32 wb_data[2];  in bnx2x_set_bmac_rx()  local
2468 		REG_RD_DMAE(bp, bmac_addr, wb_data, 2);  in bnx2x_set_bmac_rx()
2470 			wb_data[0] |= BMAC_CONTROL_RX_ENABLE;  in bnx2x_set_bmac_rx()
2472 			wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;  in bnx2x_set_bmac_rx()
2473 		REG_WR_DMAE(bp, bmac_addr, wb_data, 2);  in bnx2x_set_bmac_rx()
13649 		u32 wb_data[2];  in bnx2x_check_half_open_conn()  local
13658 		REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);  in bnx2x_check_half_open_conn()
13659 		lss_status = (wb_data[0] > 0);  in bnx2x_check_half_open_conn()