Searched refs:wait_for (Results 1 - 28 of 28) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_sideband.c54 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { vlv_sideband_rw()
65 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { vlv_sideband_rw()
218 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, intel_sbi_read()
232 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, intel_sbi_read()
248 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, intel_sbi_write()
263 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, intel_sbi_write()
H A Dintel_uncore.c1385 return wait_for(i915_reset_complete(dev), 500); i915_do_reset()
1398 return wait_for(g4x_reset_complete(dev), 500); g33_do_reset()
1408 ret = wait_for(g4x_reset_complete(dev), 500); g4x_do_reset()
1418 ret = wait_for(g4x_reset_complete(dev), 500); g4x_do_reset()
1438 ret = wait_for((I915_READ(ILK_GDSR) & ironlake_do_reset()
1445 ret = wait_for((I915_READ(ILK_GDSR) & ironlake_do_reset()
1469 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); gen6_do_reset()
1482 return wait_for((I915_READ(reg) & mask) == value, timeout_ms); wait_for_register()
H A Dintel_dsi_pll.c267 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & vlv_enable_dsi_pll()
311 if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE) bxt_disable_dsi_pll()
552 if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) { bxt_enable_dsi_pll()
H A Dintel_runtime_pm.c272 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & hsw_set_power_well()
599 if (wait_for((I915_READ(SKL_FUSE_STATUS) & skl_set_power_well()
653 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & skl_set_power_well()
676 * waiting using wait_for function. skl_set_power_well()
678 wait_for((state = intel_csr_load_status_get(dev_priv)) != skl_set_power_well()
694 if (wait_for((I915_READ(SKL_FUSE_STATUS) & skl_set_power_well()
698 if (wait_for((I915_READ(SKL_FUSE_STATUS) & skl_set_power_well()
799 if (wait_for(COND, 100)) vlv_set_power_well()
1087 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10)) assert_chv_phy_status()
1118 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) chv_dpio_cmn_power_well_enable()
1361 if (wait_for(COND, 100)) chv_set_pipe_power_well()
H A Dintel_dsi.c59 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) wait_for_dsi_fifo_empty()
125 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) intel_dsi_host_transfer()
136 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { intel_dsi_host_transfer()
145 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) intel_dsi_host_transfer()
235 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) dpi_send_cmd()
610 if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT) intel_dsi_clear_device_ready()
H A Dintel_crt.c297 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, intel_ironlake_crt_detect_hotplug()
334 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, valleyview_crt_detect_hotplug()
390 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & intel_crt_detect_hotplug()
H A Dintel_psr.c446 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) & vlv_psr_disable()
526 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) & intel_psr_work()
532 if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) & intel_psr_work()
H A Di915_drv.c1325 err = wait_for(COND, 20); vlv_force_gfx_clock()
1348 err = wait_for(COND, 1); vlv_allow_gt_wake()
1376 err = wait_for(COND, 3); vlv_wait_for_gt_wells()
H A Dintel_dp_mst.c222 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_ACT_SENT), intel_mst_enable_dp()
H A Dintel_lvds.c227 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) intel_enable_lvds()
249 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) intel_disable_lvds()
H A Dintel_i2c.c304 return wait_for(C, 10); gmbus_wait_idle()
H A Dintel_ringbuffer.c537 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, intel_ring_setup_status_page()
550 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { stop_ring()
632 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && init_ring_common()
2463 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & gen6_bsd_ring_write_tail()
H A Dintel_display.c1142 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, intel_wait_for_pipe_off()
1147 if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) intel_wait_for_pipe_off()
1619 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) vlv_enable_pll()
1668 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) chv_enable_pll()
1861 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) vlv_wait_port_ready()
2016 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) ironlake_enable_pch_transcoder()
2047 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) lpt_enable_pch_transcoder()
2069 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) ironlake_disable_pch_transcoder()
2089 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) lpt_disable_pch_transcoder()
4365 if (wait_for(I915_READ(dslreg) != temp, 5)) { cpt_verify_modeset()
4366 if (wait_for(I915_READ(dslreg) != temp, 5)) cpt_verify_modeset()
4608 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) hsw_enable_ips()
4627 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) hsw_disable_ips()
5538 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), broxton_set_cdclk()
5553 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) broxton_set_cdclk()
5726 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) skl_dpll0_enable()
5822 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) skl_uninit_cdclk()
5882 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & valleyview_set_cdclk()
5902 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & valleyview_set_cdclk()
5958 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & cherryview_set_cdclk()
9434 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) hsw_disable_lcpll()
9442 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, hsw_disable_lcpll()
9489 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) hsw_restore_lcpll()
H A Dintel_ddi.c2618 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) skl_ddi_pll_enable()
2690 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) broxton_phy_init()
2754 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, broxton_phy_init()
H A Dintel_fbc.c77 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { i8xx_fbc_disable()
H A Dintel_opregion.c305 if (wait_for(C, dslp)) { swsci()
H A Dintel_drv.h66 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
H A Dintel_pm.c255 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & chv_set_memory_dvfs()
4044 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
7165 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, sandybridge_pcode_read()
7189 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, sandybridge_pcode_write()
H A Di915_gem.c4900 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & i915_gem_init()
H A Dintel_dp.c3684 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), intel_dp_set_idle_link_train()
/linux-4.4.14/drivers/mmc/host/
H A Dsh_mmcif.c245 enum sh_mmcif_wait_for wait_for; member in struct:sh_mmcif_host
596 host->state, host->wait_for); sh_mmcif_error_manage()
600 host->state, host->wait_for); sh_mmcif_error_manage()
604 host->state, host->wait_for); sh_mmcif_error_manage()
636 host->wait_for = MMCIF_WAIT_FOR_READ; sh_mmcif_single_read()
660 host->wait_for = MMCIF_WAIT_FOR_READ_END; sh_mmcif_read_block()
676 host->wait_for = MMCIF_WAIT_FOR_MREAD; sh_mmcif_multi_read()
716 host->wait_for = MMCIF_WAIT_FOR_WRITE; sh_mmcif_single_write()
740 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; sh_mmcif_write_block()
756 host->wait_for = MMCIF_WAIT_FOR_MWRITE; sh_mmcif_multi_write()
968 host->wait_for = MMCIF_WAIT_FOR_CMD; sh_mmcif_start_cmd()
991 host->wait_for = MMCIF_WAIT_FOR_STOP; sh_mmcif_stop_cmd()
1263 wait_work = host->wait_for; sh_mmcif_irqt()
1273 host->state, host->wait_for); sh_mmcif_irqt()
1334 if (host->wait_for != MMCIF_WAIT_FOR_STOP) { sh_mmcif_irqt()
1350 host->wait_for = MMCIF_WAIT_FOR_REQUEST; sh_mmcif_irqt()
1415 host->wait_for, mrq->cmd->opcode); sh_mmcif_timeout_work()
1424 switch (host->wait_for) { sh_mmcif_timeout_work()
1444 host->wait_for = MMCIF_WAIT_FOR_REQUEST; sh_mmcif_timeout_work()
/linux-4.4.14/drivers/gpu/drm/gma500/
H A Dintel_gmbus.c51 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
278 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & gmbus_xfer()
307 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & gmbus_xfer()
324 if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50)) gmbus_xfer()
H A Dcdv_intel_display.c136 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
143 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); cdv_sb_read()
155 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); cdv_sb_read()
178 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); cdv_sb_write()
191 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); cdv_sb_write()
H A Dcdv_intel_dp.c248 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
430 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { cdv_intel_edp_panel_on()
464 if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) { cdv_intel_edp_panel_off()
/linux-4.4.14/drivers/gpu/drm/vc4/
H A Dvc4_drv.h104 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
H A Dvc4_hdmi.c377 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & vc4_hdmi_encoder_enable()
389 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & vc4_hdmi_encoder_enable()
421 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & vc4_hdmi_encoder_enable()
H A Dvc4_crtc.c268 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); vc4_crtc_disable()
/linux-4.4.14/drivers/scsi/
H A Dscsi_lib.c829 unsigned long wait_for = (cmd->allowed + 1) * req->timeout; scsi_io_completion() local
1029 time_before(cmd->jiffies_at_alloc + wait_for, jiffies)) scsi_io_completion()
1621 unsigned long wait_for = (cmd->allowed + 1) * rq->timeout; scsi_softirq_done() local
1632 time_before(cmd->jiffies_at_alloc + wait_for, jiffies)) { scsi_softirq_done()
1635 wait_for/HZ); scsi_softirq_done()

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