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Searched refs:uvd (Results 1 – 16 of 16) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Damdgpu_uvd.c100 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); in amdgpu_uvd_sw_init()
136 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); in amdgpu_uvd_sw_init()
143 r = amdgpu_ucode_validate(adev->uvd.fw); in amdgpu_uvd_sw_init()
147 release_firmware(adev->uvd.fw); in amdgpu_uvd_sw_init()
148 adev->uvd.fw = NULL; in amdgpu_uvd_sw_init()
152 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; in amdgpu_uvd_sw_init()
159 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | in amdgpu_uvd_sw_init()
167 NULL, NULL, &adev->uvd.vcpu_bo); in amdgpu_uvd_sw_init()
173 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); in amdgpu_uvd_sw_init()
175 amdgpu_bo_unref(&adev->uvd.vcpu_bo); in amdgpu_uvd_sw_init()
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Duvd_v6_0.c99 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); in uvd_v6_0_sw_init()
111 ring = &adev->uvd.ring; in uvd_v6_0_sw_init()
114 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); in uvd_v6_0_sw_init()
145 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v6_0_hw_init()
204 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v6_0_hw_fini()
262 lower_32_bits(adev->uvd.gpu_addr)); in uvd_v6_0_mc_resume()
264 upper_32_bits(adev->uvd.gpu_addr)); in uvd_v6_0_mc_resume()
267 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); in uvd_v6_0_mc_resume()
291 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v6_0_start()
754 amdgpu_fence_process(&adev->uvd.ring); in uvd_v6_0_process_interrupt()
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Duvd_v5_0.c99 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); in uvd_v5_0_sw_init()
111 ring = &adev->uvd.ring; in uvd_v5_0_sw_init()
114 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); in uvd_v5_0_sw_init()
145 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v5_0_hw_init()
210 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v5_0_hw_fini()
264 lower_32_bits(adev->uvd.gpu_addr)); in uvd_v5_0_mc_resume()
266 upper_32_bits(adev->uvd.gpu_addr)); in uvd_v5_0_mc_resume()
269 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); in uvd_v5_0_mc_resume()
293 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v5_0_start()
770 amdgpu_fence_process(&adev->uvd.ring); in uvd_v5_0_process_interrupt()
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Duvd_v4_2.c103 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); in uvd_v4_2_sw_init()
115 ring = &adev->uvd.ring; in uvd_v4_2_sw_init()
118 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); in uvd_v4_2_sw_init()
149 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v4_2_hw_init()
214 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v4_2_hw_fini()
263 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v4_2_start()
583 addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v4_2_mc_resume()
584 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; in uvd_v4_2_mc_resume()
599 addr = (adev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_mc_resume()
603 addr = (adev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_mc_resume()
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Damdgpu_fence.c441 if (ring != &adev->uvd.ring) { in amdgpu_fence_driver_start_ring()
446 index = ALIGN(adev->uvd.fw->size, 8); in amdgpu_fence_driver_start_ring()
447 ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index; in amdgpu_fence_driver_start_ring()
448 ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index; in amdgpu_fence_driver_start_ring()
Damdgpu_kms.c228 ring_mask = adev->uvd.ring.ready ? 1 : 0; in amdgpu_info_ioctl()
306 fw_info.ver = adev->uvd.fw_version; in amdgpu_info_ioctl()
Damdgpu_ring.c526 static int r600_uvd_index = offsetof(struct amdgpu_device, uvd.ring);
Damdgpu_test.c248 if (ring == &adev->uvd.ring) { in amdgpu_test_create_and_emit_fence()
Damdgpu_cs.c116 *out_ring = &adev->uvd.ring; in amdgpu_cs_get_ring()
Damdgpu.h2078 struct amdgpu_uvd uvd; member
/linux-4.4.14/drivers/gpu/drm/radeon/
Dradeon_uvd.c69 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); in radeon_uvd_init()
145 NULL, &rdev->uvd.vcpu_bo); in radeon_uvd_init()
151 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); in radeon_uvd_init()
153 radeon_bo_unref(&rdev->uvd.vcpu_bo); in radeon_uvd_init()
158 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM, in radeon_uvd_init()
159 &rdev->uvd.gpu_addr); in radeon_uvd_init()
161 radeon_bo_unreserve(rdev->uvd.vcpu_bo); in radeon_uvd_init()
162 radeon_bo_unref(&rdev->uvd.vcpu_bo); in radeon_uvd_init()
167 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr); in radeon_uvd_init()
173 radeon_bo_unreserve(rdev->uvd.vcpu_bo); in radeon_uvd_init()
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Duvd_v4_2.c44 addr = rdev->uvd.gpu_addr >> 3; in uvd_v4_2_resume()
60 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_resume()
64 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_resume()
Duvd_v2_2.c113 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume()
129 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume()
133 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
Duvd_v1_0.c121 addr = (rdev->uvd.gpu_addr >> 3) + 16; in uvd_v1_0_resume()
137 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v1_0_resume()
141 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v1_0_resume()
144 WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); in uvd_v1_0_resume()
Dradeon_fence.c818 rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index; in radeon_fence_driver_start_ring()
819 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index; in radeon_fence_driver_start_ring()
Dradeon.h2389 struct radeon_uvd uvd; member