99 	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);  in uvd_v5_0_sw_init()
111 	ring = &adev->uvd.ring;  in uvd_v5_0_sw_init()
114 			     &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);  in uvd_v5_0_sw_init()
145 	struct amdgpu_ring *ring = &adev->uvd.ring;  in uvd_v5_0_hw_init()
210 	struct amdgpu_ring *ring = &adev->uvd.ring;  in uvd_v5_0_hw_fini()
264 			lower_32_bits(adev->uvd.gpu_addr));  in uvd_v5_0_mc_resume()
266 			upper_32_bits(adev->uvd.gpu_addr));  in uvd_v5_0_mc_resume()
269 	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);  in uvd_v5_0_mc_resume()
293 	struct amdgpu_ring *ring = &adev->uvd.ring;  in uvd_v5_0_start()
770 	amdgpu_fence_process(&adev->uvd.ring);  in uvd_v5_0_process_interrupt()
832 	adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs;  in uvd_v5_0_set_ring_funcs()
842 	adev->uvd.irq.num_types = 1;  in uvd_v5_0_set_irq_funcs()
843 	adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs;  in uvd_v5_0_set_irq_funcs()