103 	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);  in uvd_v4_2_sw_init()
115 	ring = &adev->uvd.ring;  in uvd_v4_2_sw_init()
118 			     &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);  in uvd_v4_2_sw_init()
149 	struct amdgpu_ring *ring = &adev->uvd.ring;  in uvd_v4_2_hw_init()
214 	struct amdgpu_ring *ring = &adev->uvd.ring;  in uvd_v4_2_hw_fini()
263 	struct amdgpu_ring *ring = &adev->uvd.ring;  in uvd_v4_2_start()
583 	addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;  in uvd_v4_2_mc_resume()
584 	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;  in uvd_v4_2_mc_resume()
599 	addr = (adev->uvd.gpu_addr >> 28) & 0xF;  in uvd_v4_2_mc_resume()
603 	addr = (adev->uvd.gpu_addr >> 32) & 0xFF;  in uvd_v4_2_mc_resume()
823 	amdgpu_fence_process(&adev->uvd.ring);  in uvd_v4_2_process_interrupt()
893 	adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs;  in uvd_v4_2_set_ring_funcs()
903 	adev->uvd.irq.num_types = 1;  in uvd_v4_2_set_irq_funcs()
904 	adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs;  in uvd_v4_2_set_irq_funcs()