Searched refs:train_set (Results 1 – 6 of 6) sorted by relevance
| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | atombios_dp.c | 209 u8 train_set[4]) in amdgpu_atombios_dp_get_adjust_train()
241 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train()
500 u8 train_set[4]; member
512 0, dp_info->train_set[0]); /* sets all lanes at once */ in amdgpu_atombios_dp_update_vs_emph()
516 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph()
610 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr()
634 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in amdgpu_atombios_dp_link_train_cr()
642 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in amdgpu_atombios_dp_link_train_cr()
651 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in amdgpu_atombios_dp_link_train_cr()
655 dp_info->train_set); in amdgpu_atombios_dp_link_train_cr()
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| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | atombios_dp.c | 260 u8 train_set[4]) in dp_get_adjust_train()
292 train_set[lane] = v | p; in dp_get_adjust_train()
575 u8 train_set[4]; member
587 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
591 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
702 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
726 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
734 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
743 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
746 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr()
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| /linux-4.4.14/drivers/gpu/drm/i915/ |
| D | intel_dp.c | 3156 uint8_t train_set = intel_dp->train_set[0]; in vlv_signal_levels() local
3160 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_signal_levels()
3163 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels()
3186 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels()
3205 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels()
3220 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels()
3247 static bool chv_need_uniq_trans_scale(uint8_t train_set) in chv_need_uniq_trans_scale() argument
3249 return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 && in chv_need_uniq_trans_scale()
3250 (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3; in chv_need_uniq_trans_scale()
3260 uint8_t train_set = intel_dp->train_set[0]; in chv_signal_levels() local
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| D | intel_ddi.c | 2267 uint8_t train_set = intel_dp->train_set[0]; in ddi_signal_levels() local
2268 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in ddi_signal_levels()
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| D | intel_drv.h | 746 uint8_t train_set[4]; member
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| /linux-4.4.14/drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 269 uint8_t train_set[4]; member
1329 intel_dp->train_set[lane] = v | p; in cdv_intel_get_adjust_train()
1420 intel_dp->train_set, in cdv_intel_dplink_set_level()
1425 intel_dp->train_set[0], intel_dp->lane_count); in cdv_intel_dplink_set_level()
1525 memset(intel_dp->train_set, 0, 4); in cdv_intel_dp_start_link_train()
1537 intel_dp->train_set[0], in cdv_intel_dp_start_link_train()
1544 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); in cdv_intel_dp_start_link_train()
1565 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdv_intel_dp_start_link_train()
1571 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in cdv_intel_dp_start_link_train()
1577 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in cdv_intel_dp_start_link_train()
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