3156 	uint8_t train_set = intel_dp->train_set[0];  in vlv_signal_levels()  local
3160 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {  in vlv_signal_levels()
3163 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {  in vlv_signal_levels()
3186 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {  in vlv_signal_levels()
3205 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {  in vlv_signal_levels()
3220 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {  in vlv_signal_levels()
3247 static bool chv_need_uniq_trans_scale(uint8_t train_set)  in chv_need_uniq_trans_scale()  argument
3249 	return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&  in chv_need_uniq_trans_scale()
3250 		(train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;  in chv_need_uniq_trans_scale()
3260 	uint8_t train_set = intel_dp->train_set[0];  in chv_signal_levels()  local
3265 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {  in chv_signal_levels()
3267 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {  in chv_signal_levels()
3290 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {  in chv_signal_levels()
3308 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {  in chv_signal_levels()
3322 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {  in chv_signal_levels()
3398 		if (chv_need_uniq_trans_scale(train_set))  in chv_signal_levels()
3450 		intel_dp->train_set[lane] = v | p;  in intel_get_adjust_train()
3454 gen4_signal_levels(uint8_t train_set)  in gen4_signal_levels()  argument
3458 	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {  in gen4_signal_levels()
3473 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {  in gen4_signal_levels()
3493 gen6_edp_signal_levels(uint8_t train_set)  in gen6_edp_signal_levels()  argument
3495 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |  in gen6_edp_signal_levels()
3521 gen7_edp_signal_levels(uint8_t train_set)  in gen7_edp_signal_levels()  argument
3523 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |  in gen7_edp_signal_levels()
3558 	uint8_t train_set = intel_dp->train_set[0];  in intel_dp_set_signal_levels()  local
3572 		signal_levels = gen7_edp_signal_levels(train_set);  in intel_dp_set_signal_levels()
3575 		signal_levels = gen6_edp_signal_levels(train_set);  in intel_dp_set_signal_levels()
3578 		signal_levels = gen4_signal_levels(train_set);  in intel_dp_set_signal_levels()
3586 		train_set & DP_TRAIN_VOLTAGE_SWING_MASK);  in intel_dp_set_signal_levels()
3588 		(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>  in intel_dp_set_signal_levels()
3602 	uint8_t buf[sizeof(intel_dp->train_set) + 1];  in intel_dp_set_link_train()
3617 		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);  in intel_dp_set_link_train()
3632 		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));  in intel_dp_reset_link_train()
3653 				intel_dp->train_set, intel_dp->lane_count);  in intel_dp_update_link_train()
3768 			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)  in intel_dp_link_training_clock_recovery()
3784 		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {  in intel_dp_link_training_clock_recovery()
3792 		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;  in intel_dp_link_training_clock_recovery()