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Searched refs:tiling_flags (Results 1 – 26 of 26) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Dradeon_object.c580 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate()
585 lobj->tiling_flags = lobj->robj->tiling_flags; in radeon_bo_list_validate()
601 if (!bo->tiling_flags) in radeon_bo_get_surface_reg()
640 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg()
662 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument
670 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
671 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in radeon_bo_set_tiling_flags()
672 …mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TIL… in radeon_bo_set_tiling_flags()
673 …tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; in radeon_bo_set_tiling_flags()
674 …stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCI… in radeon_bo_set_tiling_flags()
[all …]
Dradeon_fb.c112 u32 tiling_flags = 0; in radeonfb_create_pinned_object() local
139 tiling_flags = RADEON_TILING_MACRO; in radeonfb_create_pinned_object()
144 tiling_flags |= RADEON_TILING_SWAP_32BIT; in radeonfb_create_pinned_object()
147 tiling_flags |= RADEON_TILING_SWAP_16BIT; in radeonfb_create_pinned_object()
153 if (tiling_flags) { in radeonfb_create_pinned_object()
155 tiling_flags | RADEON_TILING_SURFACE, in radeonfb_create_pinned_object()
Dradeon_object.h147 u32 tiling_flags, u32 pitch);
149 u32 *tiling_flags, u32 *pitch);
Dr200.c221 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
223 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
293 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
295 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
Dr300.c720 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
722 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
724 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
789 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
791 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
793 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
874 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
876 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
878 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
Devergreen_cs.c92 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) in evergreen_cs_get_aray_mode() argument
94 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode()
96 else if (tiling_flags & RADEON_TILING_MICRO) in evergreen_cs_get_aray_mode()
1180 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1181 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1182 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1185 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1365 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1366 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1383 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
[all …]
Dradeon_legacy_crtc.c381 uint32_t tiling_flags; in radeon_crtc_do_set_base() local
463 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base()
465 if (tiling_flags & RADEON_TILING_MICRO) in radeon_crtc_do_set_base()
483 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
499 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
Datombios_crtc.c1147 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in dce4_crtc_do_set_base() local
1188 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base()
1261 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base()
1262 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1334 } else if (tiling_flags & RADEON_TILING_MICRO) in dce4_crtc_do_set_base()
1464 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in avivo_crtc_do_set_base() local
1503 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base()
1564 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
1566 else if (tiling_flags & RADEON_TILING_MICRO) in avivo_crtc_do_set_base()
1569 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
[all …]
Dr100.c1283 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1285 if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset()
1625 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1627 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1706 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1708 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
3096 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument
3103 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
3106 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3109 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
[all …]
Dr600_cs.c1044 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1143 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1146 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1474 u32 tiling_flags) in r600_check_texture_resource() argument
1496 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource()
1498 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource()
1967 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
1969 else if (reloc->tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
1985 reloc->tiling_flags); in r600_packet3_check()
Dradeon_gem.c502 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl()
523 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
Dradeon_vm.c146 list[0].tiling_flags = 0; in radeon_vm_get_bos()
158 list[idx].tiling_flags = 0; in radeon_vm_get_bos()
Dradeon_display.c513 uint32_t tiling_flags, pitch_pixels; in radeon_crtc_page_flip() local
560 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); in radeon_crtc_page_flip()
568 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip()
Dradeon.h347 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
463 uint32_t tiling_flags; member
495 u32 tiling_flags; member
1941 uint32_t tiling_flags, uint32_t pitch,
Dradeon_asic.h91 uint32_t tiling_flags, uint32_t pitch,
339 uint32_t tiling_flags, uint32_t pitch,
Devergreen.c1106 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, in evergreen_tiling_fields() argument
1110 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in evergreen_tiling_fields()
1111 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in evergreen_tiling_fields()
1112 …*mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TI… in evergreen_tiling_fields()
1113 …*tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MA… in evergreen_tiling_fields()
Dr600.c3026 uint32_t tiling_flags, uint32_t pitch, in r600_set_surface_reg() argument
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Damdgpu_object.c518 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) in amdgpu_bo_set_tiling_flags() argument
520 if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
523 bo->tiling_flags = tiling_flags; in amdgpu_bo_set_tiling_flags()
527 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) in amdgpu_bo_get_tiling_flags() argument
531 if (tiling_flags) in amdgpu_bo_get_tiling_flags()
532 *tiling_flags = bo->tiling_flags; in amdgpu_bo_get_tiling_flags()
Damdgpu_fb.c112 u32 tiling_flags = 0; in amdgpufb_create_pinned_object() local
139 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); in amdgpufb_create_pinned_object()
145 if (tiling_flags) { in amdgpufb_create_pinned_object()
147 tiling_flags); in amdgpufb_create_pinned_object()
Damdgpu_object.h156 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
157 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
Ddce_v8_0.c1987 uint64_t fb_location, tiling_flags; in dce_v8_0_crtc_do_set_base() local
2029 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); in dce_v8_0_crtc_do_set_base()
2032 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base()
2104 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
2107 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
2108 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
2109 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
2110 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
2111 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
2120 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
Damdgpu_display.c180 u64 tiling_flags; in amdgpu_crtc_page_flip() local
231 amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags); in amdgpu_crtc_page_flip()
Ddce_v11_0.c2038 uint64_t fb_location, tiling_flags; in dce_v11_0_crtc_do_set_base() local
2080 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); in dce_v11_0_crtc_do_set_base()
2083 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base()
2162 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2165 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2166 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2167 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
2168 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2169 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
2182 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
Ddce_v10_0.c2050 uint64_t fb_location, tiling_flags; in dce_v10_0_crtc_do_set_base() local
2092 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); in dce_v10_0_crtc_do_set_base()
2095 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
2174 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
2177 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
2178 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
2179 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
2180 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
2181 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
2194 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
Damdgpu.h531 u64 tiling_flags; member
/linux-4.4.14/include/uapi/drm/
Dradeon_drm.h854 uint32_t tiling_flags; member
860 uint32_t tiling_flags; member